JP2009266329A - Static ram - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an SRAM for optimizing sense amplifier start-up timing and reducing access time. <P>SOLUTION: A sense amplifier start-up timing control circuit 60 includes: a dummy bit line DBL reset to VDD; a plurality of replica cells connected to the dummy bit line DBL and selected upon the selection of a memory cell; a reset circuit resetting the electric potential of the dummy bit line DBL to VDD when the dummy bit line DBL decreases to VDD/2 after the selection of the memory cell; and a sense amplifier start-up timing signal generation part generating a sense amplifier start-up timing signal STCLK when the dummy bit line DBL decreases to VDD/2 the second time after the selection of the memory cell. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a static random access memory (hereinafter referred to as SRAM) having a sense amplifier activation timing control circuit that controls the activation timing of a sense amplifier that amplifies a voltage read from a memory cell to an optimum timing.

  FIG. 8 is a circuit diagram showing a part of an example of a conventional SRAM. In FIG. 8, 1 is a memory cell, WL is a word line, BL and BLx are bit lines, DB and DBx are data buses, 2 is a sense amplifier, 3 is a sense amplifier activation timing control circuit, and 4 is a sense amplifier activation signal generation circuit. It is.

  The memory cell 1 has a flip-flop 7 in which CMOS inverters 5 and 6 are cross-connected as a storage medium. In the CMOS inverters 5 and 6, 8 and 9 are PMOS transistors, and 10 and 11 are NMOS transistors. Reference numerals 12 and 13 denote NMOS transistors forming transfer gates.

  The sense amplifier 2 includes PMOS transistors 14 and 15 and NMOS transistors 16 to 18. The PMOS transistors 14 and 15 and the PMOS transistors 16 and 17 operate as a latch type amplifier. The NMOS transistor 18 is ON / OFF controlled by a sense amplifier activation signal SAE.

  Here, when the sense amplifier activation signal SAE is at L level, the NMOS transistor 18 is turned OFF and the sense amplifier 2 is inactivated. On the other hand, when the sense amplifier activation signal SAE is at the H level, the NMOS transistor 18 is turned on and the sense amplifier 2 is activated.

  The sense amplifier activation timing control circuit 3 generates a sense amplifier activation timing signal STCLK. The sense amplifier activation signal generation circuit 4 receives the sense amplifier activation timing signal STCLK output from the sense amplifier activation timing control circuit 3 and generates a sense amplifier activation signal SAE.

  FIG. 9 is a circuit diagram showing a configuration of the sense amplifier activation timing control circuit 3. In FIG. 9, 20 is a self-reset circuit, and 21 is an inverter that inverts the output signal OUT of the self-reset circuit 20 and outputs a sense amplifier start timing signal STCLK.

  In the self-reset circuit 20, DWLL is a dummy word line, DBL is a dummy bit line, 22 is a VDD power supply line for supplying a power supply voltage VDD, 23 is a PMOS transistor, 24 is an inverter, and 25-1 and 25-N are replica cells. is there. The replica cells 25-2 to 25- (N-1) are not shown. The replica cells 25-1 to 25-N are configured using transistors having the same size as the transistors included in the memory cell 1.

  The PMOS transistor 23 precharges the potential of the dummy bit line DBL to the power supply potential VDD, the source is connected to the VDD power supply line 22, the drain is connected to the dummy bit line DBL, and the gate is connected to the dummy word line DWLL. Connected. The inverter 24 detects a potential change of the dummy bit line DBL and outputs a dummy bit line potential detection signal OUT, and has a threshold potential of 0.5 × VDD.

  The replica cell 25-1 has a flip-flop 28-1 formed by cross-connecting CMOS inverters 26-1 and 27-1 as a storage medium. In the CMOS inverters 26-1 and 27-1, 29-1 and 30-1 are PMOS transistors, and 31-1 and 32-1 are NMOS transistors.

  Reference numerals 33-1 and 34-1 are NMOS transistors forming transfer gates. The NMOS transistor 33-1 has a source connected to the dummy bit line DBL, a drain connected to the storage node 35-1, and a gate connected to the dummy word line DWLL. The NMOS transistor 34-1 has an open source, a drain connected to the storage node 36-1, and a gate connected to the dummy word line DWLL.

  The storage node 36-1 is connected to the VDD power supply line. Therefore, after the power is turned on, in the replica cell 25-1, the PMOS transistor 29-1 is always OFF, the NMOS transistor 31-1 is ON, the PMOS transistor 30-1 is ON, and the NMOS transistor 32-1 is OFF.

  The replica cell 25-N has a flip-flop 28-N formed by cross-connecting CMOS inverters 26-N and 27-N as a storage medium. In the CMOS inverters 26-N and 27-N, 29-N and 30-N are PMOS transistors, and 31-N and 32-N are NMOS transistors.

  33-N and 34-N are NMOS transistors forming transfer gates. The NMOS transistor 33-N has a source connected to the dummy bit line DBL, a drain connected to the storage node 35-N, and a gate connected to the dummy word line DWLL. The NMOS transistor 34-N has an open source, a drain connected to the storage node 36-N, and a gate connected to the dummy word line DWLL.

  The storage node 36-N is connected to the VDD power supply line. Therefore, after the power is turned on, in the replica cell 25-N, the PMOS transistor 29-N is always OFF, the NMOS transistor 31-N is ON, the PMOS transistor 30-N is ON, and the NMOS transistor 32-N is OFF.

  The replica cells 25-2 to 25- (N-1) not shown are also configured in the same manner as the replica cells 25-1 and 25-N, and the dummy word lines DWLL and dummy cells are configured in the same manner as the replica cells 25-1 and 25-N. Connected to the bit line DBL.

  FIG. 10 is a waveform diagram showing the operation of the sense amplifier activation timing control circuit 3. (A) is the potential of the dummy bit line DWLL, (B) is the potential of the dummy bit line DBL, (C) is the dummy bit line potential detection signal OUT output from the self-reset circuit 20, and (D) is the sense amplifier activation timing control. A sense amplifier activation timing signal STCLK output from the circuit 3 is shown.

  Here, when the potential of the dummy word line DWLL is at L level, the PMOS transistor 23 is ON, and the NMOS transistors 33-1 to 33-N are OFF. As a result, the dummy bit line DBL is charged via the PMOS transistor 23, the potential of the dummy bit line DBL is the power supply potential VDD, the dummy bit line potential detection signal OUT is L level, and the sense amplifier activation timing signal STCLK is H level. It has become.

  From this state, when the potential of the dummy word line DWLL is set to H level, the PMOS transistor 23 is turned off and the NMOS transistors 33-1 to 33-N are turned on. As a result, in the replica cell 25-i (where i = 1, 2,..., N), a current flows from the dummy bit line DBL to the ground side via the NMOS transistors 33-i and 31-i. The potential of the dummy bit line DBL starts to drop toward the ground potential 0V. After that, when the potential of the dummy bit line DBL reaches the threshold potential (0.5 × VDD) of the inverter 24, the dummy bit line potential detection signal OUT becomes H level and the sense amplifier activation signal STCLK becomes L level.

  Thereafter, when the potential of the dummy word line DWLL is returned to the L level, the PMOS transistor 23 is turned on and the NMOS transistors 33-1 to 33-N are turned off. As a result, the dummy bit line DBL is charged via the PMOS transistor 23, and the potential of the dummy bit line DBL rises toward the power supply potential VDD. Thereafter, when the potential of the dummy bit line DBL reaches the threshold potential of the inverter 24, the dummy bit line potential detection signal OUT returns to the L level and the sense amplifier activation timing signal STCLK returns to the H level.

  FIG. 11 is a circuit diagram showing a configuration of the sense amplifier activation signal generation circuit 4. In FIG. 11, 38 is an inverter, 39 is a delay circuit, 40 is a NAND circuit, and 41 is an inverter. The inverter 38 inverts the sense amplifier activation timing signal OUT. The delay circuit 39 delays the sense amplifier activation timing signal STCLK, and is configured by cascading inverters. The NAND circuit 40 performs NAND processing on the output signal of the inverter 38 and the output signal of the delay circuit 39. The inverter 41 inverts the output signal of the NAND circuit 40 and outputs a sense amplifier activation signal SAE.

  FIG. 12 is a waveform diagram showing the operation of the sense amplifier activation signal generation circuit 4. (A) is the sense amplifier activation timing signal STCLK, (B) is the output signal of the inverter 38, (C) is the output signal of the delay circuit 39, (D) is the output signal of the NAND circuit 40, and (E) is the sense amplifier activation. Signal SAE is shown.

  When the sense amplifier activation timing signal STCLK is at H level, the output signal of the inverter 38 is L level, the output signal of the delay circuit 39 is H level, the output signal of the NAND circuit 40 is H level, and the sense amplifier activation signal SAE. Becomes L level.

  From this state, when the sense amplifier activation timing signal STCLK becomes L level, the output signal of the inverter 38 becomes H level, the output signal of the NAND circuit 40 becomes L level, and the sense amplifier activation signal SAE becomes H level. Thereafter, when the delay time of the delay circuit 39 elapses, the output signal of the delay circuit 39 becomes L level. As a result, the output signal of the NAND circuit 40 becomes H level, and the sense amplifier activation signal SAE returns to L level.

  That is, when the sense amplifier activation timing signal STCLK transitions from the H level to the L level, the sense amplifier activation signal generation circuit 4 sets the sense amplifier activation signal SAE to the H level and sets the sense amplifier activation signal SAE to the H level for a certain period of time. As a result, the sense amplifier 2 is activated only during the H level period of the sense amplifier activation signal SAE.

  FIG. 13 is a waveform diagram showing an operation example when data is read from the memory cell 1 of the conventional SRAM shown in FIG. FIG. 13 shows that when the memory cell 1 stores “0”, that is, in the memory cell 1, the PMOS transistor 8 is turned off, the NMOS transistor 10 is turned on, the PMOS transistor 9 is turned on, and the NMOS transistor 11 is turned off. The case where the potential of the storage node 43 is the ground potential 0 V and the potential of the storage node 44 is the power supply potential VDD is taken as an example.

  (A) is the potential of the word line WL, (B) is the potential of the bit lines BL and BLx, (C) is the potential of the data buses DB and DBx, (D) is the potential of the dummy word line DWLL, and (E) is the dummy. The potential of the bit line DBL, (F) shows the sense amplifier activation timing signal STCLK, and (G) shows the sense amplifier activation signal SAE. 13 (D), (E), and (F) correspond to FIGS. 10 (A), (B), and (D), respectively, and FIGS. 13 (F) and (G) each correspond to FIG. 12 (A). , (E).

  In the conventional SRAM shown in FIG. 8, before the memory cell is selected at the time of reading, the bit lines BL and BLx and the data buses DB and DBx are electrically disconnected by a column selection circuit (not shown). Thus, the bit lines BL and BLx and the data buses DB and DBx are each precharged to the power supply potential VDD. For example, when the memory cell 1 is selected, the word line WL and the dummy word line DWLL are simultaneously set to the H level, and the bit lines BL and BLx and the data buses DB and DBx are connected via the column selection circuit. Are electrically connected.

  Here, since the word line WL is set to the H level, the NMOS transistors 12 and 13 forming the transfer gate of the memory cell 1 are turned on. In this case, since the NMOS transistor 10 is ON, a current starts to flow from the bit line BL to the ground side via the NMOS transistors 12 and 10, and the potential of the bit line BL starts to decrease toward the ground potential 0V. . Therefore, the potential of the data bus DB also starts to decrease toward the ground potential 0V.

  On the other hand, since the NMOS transistor 11 is OFF, no current flows from the bit line BLx to the ground side via the NMOS transistors 13 and 11, and the potential of the bit line BLx is maintained at the power supply potential VDD. Therefore, the potential of the data bus DBx is also maintained at the power supply potential VDD.

  Further, since the dummy word line DWLL is set to the H level, as described above, the potential of the dummy bit line DBL also starts to decrease toward the ground potential 0V. Thereafter, when the potential of the dummy bit line DBL reaches the threshold potential of the inverter 24, the sense amplifier activation timing signal STCLK becomes L level.

  Here, when the sense amplifier activation timing signal STCLK changes from H level to L level, the sense amplifier activation signal generation circuit 4 sets the sense amplifier activation signal SAE to H level. As a result, the NMOS transistor 18 of the sense amplifier 2 is turned on, and the sense amplifier 2 is activated. On the other hand, the word line WL is returned to the L level, the column selection circuit between the bit lines BL and BLx and the data buses DB and DBx is turned off, and the potentials of the bit lines BL and BLx are reset to the power supply potential VDD. The

  In this case, since the potential of the data bus DB <the potential of the data bus DBx, in the sense amplifier 2, the PMOS transistor 14 is OFF, the NMOS transistor 16 is ON, the PMOS transistor 15 is ON, and the NMOS transistor 17 is It becomes OFF. As a result, the potential of the data bus DB is lowered to the ground potential 0V, and the potential of the data bus DBx is maintained at the power supply potential VDD. Thereafter, the dummy word line DWLL is returned to the L level, the potential of the dummy bit line DBL is reset to the power supply potential VDD, and the potentials of the data buses DB and DBx are reset to the power supply potential VDD.

  As described above, the conventional SRAM shown in FIG. 8 uses the fact that there is a correlation between the characteristics of the real memory cell 1 and the characteristics of the replica cells 25-1 to 25-N to activate the sense amplifier. The signal STCLK is obtained. In the sense amplifier activation timing control circuit 3, the dummy bit line DBL is provided so that the load of the replica cells 25-1 to 25-N is the same as the load of the real memory cell 1, and the replica cells 25-1 to 25-1 The output terminal of 25-N on which “0” is output is connected to the dummy bit line DBL.

  As a result, the current flowing from the dummy bit line DBL to the ground side via the replica cells 25-1 to 25-N is N times the current flowing from the bit line BL or the bit line BLx to the ground side via the memory cell 1. Largely, the potential of the dummy bit line DBL changes at a speed N times the potential change of the bit line BL or the bit line BLx. In this example, the sense amplifier activation timing is determined by receiving the potential of the dummy bit line DBL by the inverter 24. Therefore, the timing when the potential of the dummy bit line DBL falls to the threshold potential of the inverter 24 is the sense amplifier activation timing. It will be determined that there is.

  On the other hand, the read voltage from the memory cell 1 is received by the sense amplifier 2, but the voltage difference between the data buses DB and DBx necessary for 0/1 determination of the read data from the memory cell 1 is, for example, about 100 to 150 mV. It is. Therefore, for example, when the sense amplifier 2 is designed to start when the voltage difference between the data buses DB and DBx is 125 mV, the potential of the dummy bit line DBL is 0.5 × VDD [V] when the sense amplifier 2 is started. It is necessary to become. Here, since 0.125 [V] = 0.5 × VDD / N [V], the required number N of replica cells in parallel is N = 0.5 × VDD / 0.125.

  In recent years, the voltage of SRAM has been lowered, and 1 [V] has become commonplace as the power supply potential VDD. In this case, the required number N of replica cells in parallel is N = 0.5 × 1 / 0.125 = 4. For example, in the case of a conventional SRAM in which the power supply potential VDD is 2.5 [V], the required number N of replica cells in parallel is N = 0.5 × 2.5 / 0.125 = 10. It becomes a piece.

  Here, as shown in FIG. 13, after the word line WL transitions from the L level to the H level, the time until the sense amplifier activation signal SAE starts transition from the L level to the H level is the sense amplifier activation time tslf. It is defined as Then, the variation in the sense amplifier activation time tslf is 1 / √N with respect to the parallel number N of replica cells. Therefore, as the number N of replica cells in parallel increases, the sense amplifier activation timing signal STCLK with less variation can be generated.

  On the other hand, when the number N of replica cells in parallel decreases, the variation in replica cells is not averaged, and the variation in the sense amplifier activation time tslf increases. The variation of the sense amplifier start-up time tslf is as follows. When the variation per replica cell is σ1 [sec] and the variation when N replica cells are parallel is σ2 [sec], the variation when N replica cells are parallel is N σ2 can be expressed by σ2 = σ1 / √N.

  Therefore, when designing an SRAM having a sense amplifier start timing control circuit with a small number of replica cells in parallel, in order to increase the yield, it is necessary to provide a large margin in the timing design in order to cover the variation in the chip. There is. For this reason, when a sense amplifier activation timing control circuit with a small number of replica cells in parallel is provided, there is a problem that the SRAM becomes a low-performance (low access time) SRAM.

  FIG. 14 is a diagram showing the appearance probability of the sense amplifier activation timing in the sense amplifier activation timing control circuit 3. The horizontal axis represents time t after the dummy word line DWLL transits from the L level to the H level, and the vertical axis represents sense at the time when the time t has elapsed since the dummy word line DWLL transited from the L level to the H level. The probability of appearance of amplifier activation timing is taken.

  In FIG. 14, reference numerals 47 and 48 denote sense amplifier activation timing appearance probability functions indicating the sense amplifier activation timing appearance probability when the time t has elapsed since the dummy word line DWLL transited from the L level to the H level. The sense amplifier activation timing appearance probability function 47 is when the variation of the sense amplifier activation timing is small, and the sense amplifier activation timing appearance probability function 48 is when the variation of the sense amplifier activation timing is large.

  Here, as shown by the sense amplifier activation timing appearance probability function 48, when the variation in the sense amplifier activation timing is large, in order to secure a sufficient yield, the design center value of the sense amplifier activation time tslf is set to time t2, It is necessary to include up to the time t4 when the sense amplifier activation timing is the latest as a specification.

  On the other hand, if the sense amplifier activation timing appearance probability characteristic shown by the sense amplifier activation timing appearance probability function 47 can be obtained, the design center value of the sense amplifier activation time tslf is set to secure a sufficient yield. It is sufficient to include the time t1 and the specification up to the time t3 when the sense amplifier activation timing is the latest, so that an SRAM with a fast access time can be designed. Note that t0 is the minimum time required until the sense amplifier is activated.

Here, if the number N of replica cells in parallel is increased, the in-chip variation of the sense amplifier activation timing can be reduced at a ratio of √N. If the number is increased, the sense amplifier activation timing is advanced, and the sense amplifier 2 is activated when the potential difference between the data buses DB and DBx is not sufficient, resulting in an erroneous reading.
JP 2002-367377 A JP 2001-84775 A Japanese Patent Laid-Open No. 11-203877

  In view of the above, an object of the present invention is to provide an SRAM capable of optimizing the sense amplifier activation timing more than before and shortening the access time.

  The SRAM disclosed herein includes a memory cell connected to a bit line precharged to a first potential, a sense amplifier that amplifies a voltage read from the memory cell, and a sense amplifier activation signal to the sense amplifier. A sense amplifier activation signal generation circuit that activates the sense amplifier by giving a sense amplifier activation timing signal to the sense amplifier activation signal generation circuit, and a sense amplifier activation timing control circuit that controls the activation timing of the sense amplifier have.

  The sense amplifier activation timing control circuit includes a dummy bit line precharged to the first potential, a plurality of replica cells connected to the dummy bit line and selected when the memory cell is selected, After the selection of the memory cell, when the dummy bit line changes to the second potential, a reset circuit that resets the potential of the dummy bit line to the first potential, and after the selection of the memory cell, the dummy bit line And a sense amplifier activation timing signal generation unit that generates the sense amplifier activation timing signal when the second potential is reached a predetermined number of times.

  In the disclosed SRAM, the reset circuit resets the potential of the dummy bit line to the first potential when the dummy bit line changes to the second potential after selection of the memory cell, and the sense amplifier The activation timing signal generation unit generates the sense amplifier activation timing signal when the dummy bit line becomes the second potential a predetermined number of times after the memory cell is selected.

  Therefore, even if the number of the replica cells is increased, the optimum number of the replica cells, that is, the time when the dummy bit line changes to the second potential at a predetermined number of times is the optimum sense amplifier activation timing. By setting such a number, it is possible to reduce variations in the sense amplifier activation timing after selection of the memory cells, shorten the time when the sense amplifier activation timing is the latest, and shorten the access time.

  FIG. 1 is a circuit diagram showing a part of an embodiment of the present invention. In FIG. 1, 51-0 and 51-255 are memory cells. The memory cells 51-1 to 51-254 provided between the memory cells 51-0 and 51-255 are not shown. The memory cells 51-0 to 51-255 are connected to the bit lines BL and BLx, and are configured to be selected via the word lines WL0 to WL255. The word lines WL1 to WL254 are not shown.

  Reference numeral 52 denotes a precharge circuit for the bit lines BL and BLx. An inverter 53 generates a precharge control signal PC that inverts the column selection signal CS and applies the same to the precharge circuit 52. DB and DBx are data buses. A column selection circuit 54 is connected between the bit lines BL and BLx and the data buses DB and DBx.

  The column selection circuit 54 includes PMOS transistors 55 and 56. The PMOS transistor 55 is configured such that the source is connected to the bit line BL, the drain is connected to the data bus DB, and the column selection signal CS is supplied to the gate. The PMOS transistor 56 is configured such that the source is connected to the bit line BLx, the drain is connected to the data bus DBx, and the column selection signal CS is supplied to the gate.

  In the column selection circuit 54 configured as described above, when the column selection signal CS is at L level, the PMOS transistors 55 and 56 are turned on, and the bit lines BL and BLx are electrically connected to the data buses DB and DBx. The On the other hand, when the column selection signal CS is at the H level, the PMOS transistors 55 and 56 are turned off, and the bit lines BL and BLx are not electrically connected to the data buses DB and DBx.

  Reference numeral 57 denotes a precharge circuit for the data buses DB and DBx. The precharge circuit 57 is supplied with a precharge control signal EQDM. Reference numeral 58 denotes a sense amplifier provided corresponding to the data buses DB and DBx. Reference numeral 59 denotes an I / O circuit provided corresponding to the data buses DB and DBx. DATA_OUT is read data output from the I / O circuit 59.

  Reference numeral 60 denotes a sense amplifier activation timing control circuit. The sense amplifier activation timing control circuit 60 receives the clock signal CK and generates a predecoder control signal DEC and a sense amplifier activation timing signal STCLK.

  Reference numeral 61 denotes a sense amplifier activation signal generation circuit. The sense amplifier activation signal generation circuit 61 receives the sense amplifier activation timing signal STCLK output from the sense amplifier activation timing control circuit 60 and generates a sense amplifier activation signal SAE to be given to the sense amplifier 58. The sense amplifier activation signal generation circuit 61 has the same configuration as the sense amplifier activation signal generation circuit 4 shown in FIG. 8 (FIG. 11).

  A0 to A7 are row address signals given from the outside, and 62, 63 and 64 are predecoders. The predecoder 62 decodes the row address signals A0 to A2 and outputs an 8-bit predecode signal. The predecoder 63 decodes the row address signals A3 to A5 and outputs an 8-bit predecode signal. The predecoder 64 decodes the address signals A6 and A7 and outputs a 4-bit predecode signal.

  The basic configuration of the predecoders 62, 63 and 64 is a conventionally known configuration using a NAND circuit and an inverter. In this example, a predecoder control signal is given to the NAND circuit, and the predecoder control signal DEC Is inactive when L is at L level, and is activated when predecoder control signal DEC is at H level.

  65-0 is a main decoder provided corresponding to the word line WL0, and 65-255 is a main decoder provided corresponding to the word line WL255. The main decoders 65-1 to 65-254 provided corresponding to the word lines WL1 to WL254 are not shown.

  The main decoder 65-0 includes a NAND circuit 66-0 and an inverter 67-0. NAND circuit 66-0 corresponds to one corresponding predecode signal in the 8-bit predecode signal output from predecoder 62 and one corresponding predecode in the 8-bit predecode signal output from predecoder 63. The signal and one corresponding predecode signal in the 4-bit predecode signal output from the predecoder 64 are input. The inverter 67-0 inverts the output of the NAND circuit 66-0 and drives the word line WL0.

  The main decoder 65-255 has NAND circuits 66-255 and inverters 67-255. NAND circuits 66-255 respectively correspond to one predecode signal in the 8-bit predecode signal output from predecoder 62 and one corresponding predecode in the 8-bit predecode signal output from predecoder 63. The signal and one corresponding predecode signal in the 4-bit predecode signal output from the predecoder 64 are input. The inverter 67-255 inverts the output of the NAND circuit 66-255 and drives the word line WL255.

  FIG. 2 is a circuit diagram showing the configuration of the memory cell 51-0 and the precharge circuit 52 for the bit lines BL and BLx. The memory cell 51-0 has a flip-flop 72 formed by cross-connecting CMOS inverters 70 and 71. In the CMOS inverters 70 and 71, 73 and 74 are PMOS transistors, and 75 and 76 are NMOS transistors.

  The memory cell 51-0 has NMOS transistors 77 and 78 that form transfer gates. The NMOS transistor 77 has a drain connected to the storage node 79, a source connected to the bit line BL, and a gate connected to the word line WL0. The NMOS transistor 78 has a drain connected to the storage node 80, a source connected to the bit line BLx, and a gate connected to the word line WL0. The memory cells 51-1 to 51-255 are configured similarly.

  The precharge circuit 52 for the bit lines BL and BLx has PMOS transistors 81 to 83. The PMOS transistor 81 has a source connected to the VDD power supply line, a drain connected to the bit line BL, and a gate connected to the output terminal of the inverter 53. The PMOS transistor 82 has a source connected to the VDD power supply line, a drain connected to the bit line BLx, and a gate connected to the output terminal of the inverter 53. The PMOS transistor 83 has a source connected to the bit line BL, a drain connected to the bit line BLx, and a gate connected to the output terminal of the inverter 53.

  Here, when the column selection signal CS is at the H level, the precharge control signal PC is at the L level, and the PMOS transistors 81 to 83 are turned on. As a result, the bit lines BL and BLx are precharged to the power supply potential VDD. On the other hand, when the column selection signal CS is at the L level, the precharge control signal PC is at the H level, and the PMOS transistors 81 to 83 are turned off.

  FIG. 3 is a circuit diagram showing the configuration of the precharge circuit 57 and the sense amplifier 58 for the data buses DB and DBx. The precharge circuit 57 for the data buses DB and DBx includes PMOS transistors 86 to 88.

  The PMOS transistor 86 is configured such that the source is connected to the VDD power supply line, the drain is connected to the data bus DB, and the precharge control signal EQDM is supplied to the gate. The PMOS transistor 87 is configured such that the source is connected to the VDD power supply line, the drain is connected to the data bus DBx, and the precharge control signal EQDM is supplied to the gate. The PMOS transistor 88 is configured such that the source is connected to the data bus DB, the drain is connected to the data bus DBx, and the precharge control signal EQDM is supplied to the gate.

  Here, when the precharge control signal EQDM is at the L level, the PMOS transistors 86 to 88 are turned on, and the data buses DB and DBx are precharged to the power supply potential VDD. On the other hand, when the precharge control signal EQDM is at the H level, the PMOS transistors 86 to 88 are turned off.

  The sense amplifier 58 includes PMOS transistors 89 and 90 and NMOS transistors 91 to 93. The PMOS transistors 89 and 90 and the NMOS transistors 91 and 92 operate as a latch type amplifier. The NMOS transistor 93 is controlled to be turned on and off by the sense amplifier activation signal SAE.

  The PMOS transistor 89 has a source connected to the VDD power supply line, and the NMOS transistor 91 has a source connected to the drain of the NMOS transistor 93. The gate of the PMOS transistor 89 and the gate of the NMOS transistor 91 are connected, and the connection point is connected to the data bus DBx. The drain of the PMOS transistor 89 and the drain of the NMOS transistor 91 are connected, and the connection point is connected to the data bus DB.

  The PMOS transistor 90 has a source connected to the VDD power supply line, and the NMOS transistor 92 has a source connected to the drain of the NMOS transistor 93. The gate of the PMOS transistor 90 and the gate of the NMOS transistor 92 are connected, and the connection point is connected to the data bus DB. The drain of the PMOS transistor 90 and the drain of the NMOS transistor 92 are connected, and the connection point is connected to the data bus DBx. The NMOS transistor 93 is configured such that the source is grounded and the sense amplifier activation signal SAE is supplied to the gate.

  In the sense amplifier 58 configured as described above, when the sense amplifier activation signal SAE is at the H level, the NMOS transistor 93 is turned on and the sense amplifier 58 is activated. On the other hand, when the sense amplifier activation signal SAE is at L level, the NMOS transistor 93 is turned off and the sense amplifier 58 is inactivated.

  FIG. 4 shows potential changes of the word line WL0, the bit lines BL and BLx, the column selection signal CS, the sense amplifier activation signal SAE, the data buses DB and DBx, and the precharge control signal EQDM when data is read from the memory cell 51-0. FIG. 4 shows that when the memory cell 51-0 stores “0”, that is, in the memory cell 51-0, the PMOS transistor 73 is OFF, the NMOS transistor 75 is ON, the PMOS transistor 74 is ON, and the NMOS transistor 76 is ON. In the example, the potential of the storage node 79 is set to the ground potential 0 V and the potential of the storage node 80 is set to the power supply potential VDD.

  In one embodiment of the present invention, before the memory cell 51-0 is selected, the word lines WL0 to WL255 are at the L level, the column selection signal CS is at the H level, the sense amplifier activation signal SAE is at the L level, and the precharge is performed. Control signal EQDM is at L level. Here, since the word lines WL0 to WL255 are set to the L level, the flip-flops in the memory cells 51-0 to 51-255 are electrically disconnected from the bit lines BL and BLx.

  Since the column selection signal CS is set to the H level, the PMOS transistors 55 and 56 of the column selection circuit 54 are turned off, and the bit lines BL and BLx are not electrically connected to the data buses DB and DBx. . Further, since the precharge control signal PC becomes H level, the PMOS transistors 81 to 83 of the precharge circuit 52 for the bit lines BL and BLx are turned on. As a result, the bit lines BL and BLx are precharged to the power supply potential VDD by the precharge circuit 52 for the bit lines BL and BLx.

  Further, since the sense amplifier activation signal SAE is set to the L level, the NMOS transistor 93 of the sense amplifier 58 is turned off and the sense amplifier 58 is inactivated. Further, since the precharge control signal EQDM is set to the L level, the PMOS transistors 86 to 88 of the precharge circuit 57 for the data buses DB and DBx are turned on. As a result, the data buses DB and DBx are precharged to the power supply potential VDD by the precharge circuit 57 for the data buses DB and DBx.

  When memory cell 51-0 is selected from this state, the potential of word line WL0 is set to H level, column selection signal CS is set to L level, and precharge control signal EQDM is set to H level. Here, since the word line WL0 is set to the H level, the flip-flop 72 of the memory cell 51-0 is electrically connected to the bit lines BL and BLx.

  Further, since the column selection signal CS is set to the L level, the PMOS transistors 55 and 56 of the column selection circuit 54 are turned on, and the bit lines BL and BLx are electrically connected to the data buses DB and DBx. Further, since the precharge control signal PC is set to the H level, the PMOS transistors 81 to 83 of the precharge circuit 52 for the bit lines BL and BLx are turned off. Further, since the precharge control signal EQDM is set to the L level, the PMOS transistors 86 to 88 of the precharge circuit 57 for the data buses DB and DBx are turned off.

  Here, since the NMOS transistor 75 in the memory cell 51-0 is turned ON, a current flows from the bit line BL to the ground side through the NMOS transistors 77 and 75 of the memory cell 51-0, and the bit line BL The potential starts to drop from the power supply potential VDD toward the ground potential 0V. Therefore, the potential of the data bus DBx also starts to drop from the power supply potential VDD toward the ground potential 0V.

  On the other hand, since the NMOS transistor 76 is OFF, no current flows from the bit line BLx to the ground side via the NMOS transistors 78 and 76, and the potential of the bit line BLx is maintained at the power supply potential VDD. Therefore, the potential of the data bus DBx is also maintained at the power supply potential VDD.

  At the sense amplifier activation timing, the sense amplifier activation signal SAE becomes H level, and the sense amplifier 58 is activated. On the other hand, the word line WL0 is returned to the L level, and the NMOS transistors 77 and 78 forming the transfer gate of the memory cell 51-0 are turned off. Further, the column selection signal CS is set to the H level, and the PMOS transistors 55 and 56 of the column selection circuit 54 are turned off. In this case, since the precharge control signal PC is at the L level, the PMOS transistors 81 to 83 of the precharge circuit 52 are turned on. As a result, the potentials of the bit lines BL and BLx are reset to the power supply potential VDD.

  In this case, in the data buses DB and DBx, since the potential of the data bus DB <the potential of the data bus DBx, in the sense amplifier 58, the PMOS transistor 89 is OFF, the NMOS transistor 91 is ON, and the PMOS transistor 90 is ON, and the NMOS transistor 92 is OFF. As a result, the potential of the data bus DB is lowered to the ground potential 0V, and the potential of the data bus DBx is maintained at the power supply potential VDD.

  Thereafter, the sense amplifier drive signal SAE is set to L level, and the sense amplifier 58 is inactivated. Further, the precharge control signal EQDM is set to L level, the PMOS transistors 86 to 88 of the precharge circuit 57 are turned on, and the data buses DB and DBx are reset to the power supply potential VDD.

  FIG. 5 is a circuit diagram showing a configuration of the sense amplifier activation timing control circuit 60. In FIG. 5, reference numeral 96 denotes a counter clear signal generating circuit that inputs a clock signal CK and generates a counter clear signal STA. In the counter clear signal generation circuit 96, 97 is a delay circuit that delays the clock signal CK, 98 is an inverter that inverts the output signal of the delay circuit 97, and 99 is a counter that performs NAND processing on the clock signal CK and the output signal of the inverter 98. It is a NAND circuit that outputs a clear signal STA.

  Reference numeral 100 denotes an RS flip-flop. In the RS flip-flop 100, the counter clear signal STA output from the counter clear signal generation circuit 96 is supplied to the set input terminal / S, the sense amplifier activation timing signal STCLK is supplied to the reset input terminal / R, and the positive phase The predecoder control signal DEC is output to the output terminal Q.

  Further, 101 is a buffer, 102 is a self-reset circuit, 103 is an inverter, 104 is a delay circuit, 105 is a NAND circuit, and 106 is an inverter. The buffer 101 amplifies the predecoder control signal DEC. The self-reset circuit 102 has the same configuration as the self-reset circuit 20 shown in FIG. However, the number of replica cells is twice that of the self-reset circuit 20. For convenience of explanation, the reference numerals shown in FIG. 9 are used for elements in the self-reset circuit 102.

  The inverter 103 inverts the bit line potential detection signal OUT output from the self-reset circuit 102. The delay circuit 104 delays the output signal CUP of the inverter 103. The NAND circuit 105 performs NAND processing on the output signal DWL of the buffer 101 and the output signal LPC of the delay circuit 104. The inverter 106 inverts the output signal of the NAND circuit 105 and drives the dummy word line DWLL.

  Reference numeral 107 denotes an M-bit counter, 108 denotes a comparator, and 109 denotes a NAND circuit. The M-bit counter 107 is provided with the output signal CUP of the inverter 103 at the count signal input terminal, and the counter clear signal STA output from the counter clear signal generation circuit 96 is provided at the clear input terminal CLR.

  The comparator 108 compares the output value A of the M-bit counter 107 with the number of times specified value R. In one embodiment of the present invention, the number-of-times designation value R is 1. The output signal CB of the comparator 108 is H level when the output value A of the M-bit counter 107 matches the number-of-times specified value R, and when the output value A of the M-bit counter 107 does not match the number-of-times specified value R. L level.

  The NAND circuit 109 NAND-processes the bit line potential detection signal OUT output from the self-reset circuit 102 and the output signal CB of the comparator 108, and outputs a sense amplifier activation timing signal STCLK. The sense amplifier activation timing signal STCLK is supplied to the sense amplifier activation signal generation circuit 61.

  FIG. 6 is a waveform diagram showing the operation of one embodiment of the present invention. 6 shows that when the memory cell 51-0 stores “0”, that is, in the memory cell 51-0, the PMOS transistor 73 is OFF, the NMOS transistor 75 is ON, the PMOS transistor 74 is ON, and the NMOS transistor. An example is shown in which 76 is turned OFF, the potential of the storage node 79 is the ground potential 0 V, and the potential of the storage node 80 is the power supply potential VDD.

  (A) is the clock signal CK, (B) is the counter clear signal STA, (C) is the predecoder control signal DEC, (D) is the potential of the word line WL0, (E) is the potentials of the bit lines BL and BLx, ( F) is the output signal DWL of the buffer 101, (G) is the potential of the dummy word line DWLL, (H) is the potential of the dummy bit line DBL, (I) is the bit line potential detection signal OUT output from the self-reset circuit 102, (J) is the output signal LPC of the delay circuit 104, (K) is the output signal CUP of the inverter 103, (L) is the count value A of the M-bit counter 107, (M) is the output signal CB of the comparator 108, (N ) Shows the sense amplifier start timing signal STCLK, (O) shows the sense amplifier start signal SAE, and (P) shows the output data DATA_OUT.

  In one embodiment of the present invention, as shown in FIG. 6A, when the clock signal CK becomes H level, the counter clear signal generation circuit 96 generates a counter clear signal STA as shown in FIG. Is L level. As a result, the M-bit counter 107 is cleared and its count value A is set to 0 as shown in FIG.

  Further, since the counter clear signal STA is set to L level, the RS flip-flop 100 sets the predecoder control signal DEC to H level as shown in FIG. As a result, the predecoders 62 to 64 predecode the row address signals A0 to A7.

  Further, as shown in FIG. 6C, when the predecoder control signal DEC becomes H level and the memory cell 51-0 is selected, as shown in FIG. The line WL0 is set to the H level. As a result, the NMOS transistors 77 and 78 forming the transfer gate of the memory cell 51-0 are turned on, and the bit line BL starts to drop toward the ground potential 0V as shown in FIG.

  Further, as shown in FIG. 6C, when the predecoder control signal DEC becomes H level, as shown in FIG. 6F, the output signal DWL of the buffer 101 becomes H level, and FIG. As shown, the potential of the dummy word line DWLL becomes H level. As a result, in the self-reset circuit 102, the NMOS transistors 33-1 to 33-N, which form the transfer gates of the replica cells 25-1 to 25-N, are turned on, and the replica cells 25-1 to 25-N are connected to the dummy bit lines. As shown in FIG. 6H, the potential of the dummy bit line DBL starts to drop toward the ground potential 0V.

  When the potential of the dummy bit line DBL reaches the threshold potential of the inverter 24, as shown in FIG. 6 (I), the bit line potential detection signal OUT output from the self-reset circuit 102 becomes H level, and FIG. ), The output signal CUP of the inverter 103 becomes L level.

  Further, as shown in FIG. 6 (K), when the output signal CUP of the inverter 103 becomes L level, it is delayed by the delay time of the delay circuit 104, and as shown in FIG. 6 (J), the output of the delay circuit 104. The signal LPC becomes L level, and the potential of the dummy word line DWLL becomes L level as shown in FIG. As a result, the replica cells 25-1 to 25-N are electrically disconnected from the dummy bit line DBL, and the PMOS transistor 23 is turned on. As shown in FIG. It starts to rise toward the power supply potential VDD.

  When the potential of the dummy bit line DBL exceeds the threshold potential of the inverter 24, as shown in FIG. 6 (I), the bit line transition detection signal OUT output from the inverter 24 becomes L level, and FIG. As shown, the output signal CUP of the inverter 103 becomes H level. As a result, as shown in FIG. 6 (L), the count value A of the M-bit counter 107 becomes 1, and the count value A of the M-bit counter 107 matches the number-of-times designation value R, as shown in FIG. Thus, the output signal CB of the comparator 108 becomes H level. Further, the output signal CUP of the inverter 103 is delayed by the delay time of the delay circuit 104, and the output signal LPC of the delay circuit 104 becomes H level as shown in FIG.

  Here, when the output signal LPC of the delay circuit 104 becomes H level, the potential of the dummy word line DWLL becomes H level, and the replica cells 25-1 to 25-N are electrically connected to the dummy bit line DBL. The PMOS transistor 23 is turned off. As a result, as shown in FIG. 6H, the potential of the dummy bit line DBL starts to decrease again toward the ground potential 0V.

  When the potential of the dummy bit line DBL reaches the threshold potential of the inverter 24 for the second time, as shown in FIG. 6I, the bit line potential detection signal OUT output from the self-reset circuit 102 becomes H level. As a result, the sense amplifier activation timing signal STCLK becomes L level as shown in FIG. 6 (N), and the sense amplifier activation signal SAE becomes H level as shown in FIG. 6 (O).

  Further, when the bit line potential detection signal OUT output from the self-reset circuit 102 becomes H level, the output signal CUP of the inverter 103 becomes L level as shown in FIG. Further, when the output signal CUP of the inverter 103 becomes L level, it is delayed by the delay time of the delay circuit 104, and as shown in FIG. 6J, the output signal LPC of the delay circuit 104 becomes L level, and the dummy word The line DWLL becomes L level. As a result, the replica cells 25-1 to 25-N are electrically disconnected from the dummy bit line DBL, and the PMOS transistor 23 is turned on. As shown in FIG. It starts to rise toward the power supply potential VDD.

  When the potential of the dummy bit line DBL exceeds the threshold potential of the inverter 24, the bit line potential detection signal OUT output from the self-reset circuit 102 becomes L level as shown in FIG. N), the sense amplifier activation timing signal STCLK returns to the H level.

  Further, when the bit line potential detection signal OUT returns to L level, the output signal CUP of the inverter 103 becomes H level as shown in FIG. As a result, as shown in FIG. 6 (L), the count value A of the counter 107 becomes 2, and as shown in FIG. 6 (M), the output signal CB of the comparator 108 becomes L level. As shown in FIG. 6 (O), when the sense amplifier drive signal SAE becomes H level, the sense amplifier 58 is activated. In this example, as shown in FIG. 6 (P), the read data DATA_OUT “0” is output.

  FIG. 7 is a diagram for explaining the effect of the embodiment of the present invention. (A) is a figure which shows the sense amplifier starting timing appearance probability in one Embodiment of this invention. The horizontal axis represents the time t after the dummy word line DWL transitions from the L level to the H level, and the vertical axis represents the sense when the time t has elapsed since the dummy word line DWL transitioned from the L level to the H level. The probability of appearance of amplifier activation timing is taken.

  (B) shows the number of times of transition of the dummy bit line DBL, the number of parallel replica cells, and the design center value t1 of the sense amplifier activation time tslf when the minimum necessary time until activation of the sense amplifier is t0. This shows the relationship between the in-chip variation ratio S2 and the time t2 at which the sense amplifier activation is slowest / the time t0 that is the minimum required until the sense amplifier activation. The “ratio” indicates t2 / t0 when t2 / t0 is 1.00 when the number of transitions of the dummy bit line DBL is 1.

  Here, when the ratio of the variation value at the in-chip variation 3σ point by one replica cell to the design center value t1 of the sense amplifier activation time tslf is S1, the sense amplifier activation time when N replica cells are connected in parallel Since the ratio S2 of the variation value at the in-chip variation 3σ point to the design center value t1 of tslf is S2 = S1 / √N, for example, when S1 is 0.2, S2 is equal to FIG. ) As shown.

  In FIG. 7B, the number of transitions of the dummy bit line DBL = 1 is the case of the conventional SRAM shown in FIG. 8, and the number of transitions of the dummy bit line DBL = 2 is one embodiment of the present invention. It is the case of form. As described above, in the embodiment of the present invention, the ratio S2 of the in-chip variation of the design center value t1 of the sense amplifier activation time tslf can be reduced, and the variation of the sense amplifier activation time tslf can be reduced. Can do. If the number of parallel replica cells is 12, 16, or 20, and the number of transitions of the dummy bit line DBL is 3, 4, or 5, the variation in the appearance probability of the sense amplifier activation timing tslf is further reduced. can do.

  As described above, in one embodiment of the present invention, the self-reset circuit 102 reduces the potential of the dummy bit line DBL to the power supply potential when the potential of the dummy bit line DBL drops to the threshold potential of the inverter 24 when the memory cell is selected. The sense amplifier activation timing control circuit 60 resets the sense amplifier activation timing signal STCLK to the L level when the dummy bit line DBL becomes the threshold potential of the inverter 24 for the second time when the memory cell is selected. .

  That is, even when the number of replica cells is doubled as compared with the conventional SRAM shown in FIG. Since the reference is set to the L level, the variation in the sense amplifier activation timing after selection of the memory cells can be reduced, the time when the sense amplifier activation timing is the latest can be shortened, and the SRAM having the fast access time can be obtained. it can.

  As described above, the number of parallel replica cells is increased as compared with the embodiment of the present invention. For example, the number of parallel replica cells is 12, 16, or 20, and the number of transitions of the dummy bit line DBL is increased. Since the variation in the appearance probability of the sense amplifier activation timing tslf can be further reduced by setting the number to 3, 4, or 5, the sense amplifier activation timing control circuit 60 may be configured in this way.

  In the embodiment of the present invention, the M-bit counter 107 is used as a counting circuit for counting the number of transitions of the dummy bit line DBL. Instead, a binary counter or a shift register may be used. it can.

It is a circuit diagram showing a part of one embodiment of the present invention. 1 is a circuit diagram showing a configuration of a memory cell and a bit line precharge circuit included in an embodiment of the present invention; FIG. 1 is a circuit diagram showing a configuration of a data bus precharge circuit and a sense amplifier included in an embodiment of the present invention; FIG. FIG. 4 is a waveform diagram showing potential changes of a word line, a bit line, a column selection signal, a sense amplifier activation signal, a data bus, and a precharge control signal for the data bus when data is read from a memory cell according to an embodiment of the present invention. is there. It is a circuit diagram which shows the structure of the sense amplifier starting timing control circuit with which one Embodiment of this invention is provided. It is a wave form diagram which shows operation | movement of one Embodiment of this invention. It is a figure for demonstrating the effect of one Embodiment of this invention. It is a circuit diagram which shows a part of example of the conventional SRAM (Static Random Access Memory). FIG. 9 is a circuit diagram showing a configuration of a sense amplifier activation timing control circuit included in the conventional SRAM shown in FIG. 8. FIG. 9 is a waveform diagram showing an operation of a sense amplifier start timing control circuit included in the conventional SRAM shown in FIG. 8. FIG. 9 is a circuit diagram illustrating a configuration of a sense amplifier activation signal generation circuit included in the conventional SRAM illustrated in FIG. 8. FIG. 9 is a waveform diagram showing an operation of a sense amplifier activation signal generation circuit included in the conventional SRAM shown in FIG. 8. FIG. 9 is a waveform diagram showing an operation example when data is read from the memory cell of the conventional SRAM shown in FIG. 8. FIG. 9 is a diagram illustrating a sense amplifier activation timing appearance probability in a sense amplifier activation timing control circuit included in the conventional SRAM illustrated in FIG. 8.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Memory cell 2 ... Sense amplifier 3 ... Sense amplifier starting timing control circuit 4 ... Sense amplifier starting signal generation circuit 5, 6 ... CMOS inverter 7 ... Flip-flop 8, 9 ... PMOS transistor 10-13 ... NMOS transistor 14, 15 ... PMOS transistor 16-18 ... NMOS transistor 20 Self-reset circuit 21 ... Inverter 22 ... VDD power supply line 23 ... PMOS transistor 24 ... Inverter 25-1, 25-N ... Replica cell 26-1, 27-1, 26-N, 27 -N: CMOS inverter 28-1, 28-N: Flip-flops 29-1, 30-1, 29-N, 30-N: PMOS transistors 31-1 to 34-1, 31-N to 34-N: NMOS Transistors 35-1, 36-1, 35-N, 36-N Storage node 38 ... Inverter 39 ... Delay circuit 40 ... NAND circuit 41 ... Inverter 43, 44 ... Storage node 47, 48 ... Sense amplifier activation timing appearance probability function 51-0, 51-255 ... Memory cell 52 ... Precharge circuit 53 ... Inverter 54 ... Column selection circuit 55, 56 ... PMOS transistor 57 ... Precharge circuit 58 ... Sense amplifier 59 ... I / O circuit 60 ... Sense amplifier activation timing control circuit 61 ... Sense amplifier activation signal generation circuit 62-64 ... Predecoder 65 -0, 65-255 ... main decoders 66-0, 66-255 ... NAND circuits 67-0, 67-255 ... inverters 70, 71 ... CMOS inverters 72 ... flip-flops 73, 74 ... PMOS transistors 75-78 ... NMOS transistors DESCRIPTION OF SYMBOLS 9, 80 ... Memory node 81-83 ... PMOS transistor 86-90 ... PMOS transistor 91-93 ... NMOS transistor 96 ... Counter clear signal generation circuit 97 ... Delay circuit 98 ... Inverter 99 ... NAND circuit 100 ... RS flip-flop 101 ... Buffer DESCRIPTION OF SYMBOLS 102 ... Self-reset circuit 103 ... Inverter 104 ... Delay circuit 105 ... NAND circuit 106 ... Inverter 107 ... M bit counter 108 ... Comparator 109 ... NAND circuit

Claims (2)

A memory cell connected to a bit line precharged to a first potential;
A sense amplifier that amplifies the voltage read from the memory cell;
A sense amplifier activation signal generation circuit for applying a sense amplifier activation signal to the sense amplifier to activate the sense amplifier;
A sense amplifier activation timing control circuit for providing a sense amplifier activation timing signal to the sense amplifier activation signal generation circuit to control the activation timing of the sense amplifier;
Have
The sense amplifier activation timing control circuit is
A dummy bit line precharged to the first potential;
A plurality of replica cells connected to the dummy bit line and selected when the memory cell is selected;
A reset circuit that resets the potential of the dummy bit line to the first potential when the dummy bit line changes to the second potential after the memory cell is selected;
A sense amplifier activation timing signal generator for generating the sense amplifier activation timing signal when the dummy bit line reaches the second potential at a predetermined number of times after the memory cell is selected;
A static RAM characterized by comprising: The sense amplifier activation timing signal generator is
A counting circuit that counts the number of transitions of the dummy bit line to the second potential;
A comparator for comparing the count value of the counting circuit with a predetermined value;
A sense amplifier activation timing signal generation circuit for generating the sense amplifier activation timing signal by inputting an output signal of the comparator and an output signal of a dummy bit line potential detection circuit for detecting the potential of the dummy bit line;
The static RAM according to claim 1, further comprising:

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