CN118013914A - VBA-based calculation method for electroplating area of semiconductor metal layer - Google Patents
VBA-based calculation method for electroplating area of semiconductor metal layer Download PDFInfo
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- CN118013914A CN118013914A CN202311564487.1A CN202311564487A CN118013914A CN 118013914 A CN118013914 A CN 118013914A CN 202311564487 A CN202311564487 A CN 202311564487A CN 118013914 A CN118013914 A CN 118013914A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 69
- 239000002184 metal Substances 0.000 title claims abstract description 69
- 238000009713 electroplating Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004364 calculation method Methods 0.000 title claims abstract description 9
- 238000013461 design Methods 0.000 claims abstract description 27
- 238000009966 trimming Methods 0.000 claims abstract description 9
- 230000005611 electricity Effects 0.000 claims abstract description 6
- 238000012795 verification Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 17
- 238000010586 diagram Methods 0.000 claims description 4
- 230000006870 function Effects 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000000007 visual effect Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001768 cations Chemical class 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000002198 insoluble material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000000053 physical method Methods 0.000 description 1
Abstract
The invention discloses a calculation method of a semiconductor metal layer electroplating area based on VBA, which comprises the following steps: inputting data of a wafer to be electroplated into a program, wherein the size of a single chip is used as calibration data; program identifying the metal layer and the size of a single chip in the design drawing of the wafer to be electroplated, comparing with the input size of the single chip, and performing the next step after verification; program identification design drawing corresponding to single chip metal layer, calculating metal layer to be electroplated area and single chip total area; calculating to obtain an area ratio P to be electroplated; obtaining the radius of an effective area of the wafer to be electroplated according to the diameter and the trimming size data of the wafer to be electroplated, and calculating the total area Stotal of the effective area of the wafer; and calculating to obtain the total area S electricity to be electroplated of the wafer according to the following formula: selectricity=pstotal. The invention can effectively avoid various human errors, greatly improve the accuracy of drawing data, avoid reworking, ensure the most possible exchange period and save the cost.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a method for calculating the electroplating area of a semiconductor metal layer based on VBA.
Background
In the process of manufacturing a wafer, an electroplating process is required to be performed on the wafer, that is, a conductive metal layer is formed on the wafer by electroplating, and then the metal layer is processed to form a conductive circuit.
Electroplating refers to a process of plating a thin layer of other metals or alloys on the surface of a wafer using electrochemical principles, with the purpose of plating a metal coating on a chip to change the surface properties or dimensions of the wafer. During electroplating, plating metal or other insoluble materials are used as an anode, a wafer to be plated is used as a cathode, and cations of the plating metal are reduced on the surface of the wafer under the action of an electric field to form a metal interconnection layer (RDL) or a metal bump.
The wafer is used as a basic material of a chip, the requirement on the electroplated metal layer is extremely high, and the uniformity of the metal layer is ensured when the wafer is electroplated, so that the quality of the wafer can be ensured.
In conventional designs, the plated area of the metal layer is typically calculated manually by physical measurement. The traditional method for manually calculating the electroplating area is easy to generate errors due to uncontrollability of manual operation, and has unstable factors in the production process of products, thus being extremely easy to cause disqualification and reworking of the products. With the continuous development of semiconductor packaging technology, the electroplating requirements on the metal layer of the wafer are increased increasingly, and the probability of errors such as dimension writing errors, metal layer pattern proportion calculating errors and the like is also increased by adopting a method of manually calculating the electroplating area, so that the risk of reworking products is increased, the cost is increased, and the production efficiency of the products is also affected.
Therefore, a new method for calculating the plating area of the metal layer is needed to solve the above-mentioned problems.
Disclosure of Invention
In order to solve the problems, the invention discloses a method for calculating the electroplating area of a semiconductor metal layer based on VBA, which can solve the traditional problems.
The invention discloses a calculation method of a semiconductor metal layer electroplating area based on VBA, which comprises the following steps:
inputting the diameter of the wafer to be electroplated, the size of a single chip in the wafer to be electroplated and the trimming size data of the wafer to be electroplated, wherein the size of the single chip is used as calibration data
The program identifies the metal layer and the size of a single chip in the design drawing of the wafer to be electroplated, compares the metal layer and the size with the input size of the single chip, and carries out the next step after the verification is consistent, otherwise, reports errors;
program identification is carried out on a metal layer corresponding to a single chip in a design drawing of a wafer to be electroplated, and the area to be electroplated and the total area of the single chip of the metal layer corresponding to the single chip are calculated respectively; calculating to obtain an area ratio P to be electroplated;
p=the area to be electroplated of the metal layer corresponding to the single chip/the total area of the single chip;
Obtaining the radius of an effective area of the wafer to be electroplated according to the diameter and the trimming size data of the wafer to be electroplated, and calculating the total area Stotal of the effective area of the wafer by using a mathematical formula pi r 2;
and calculating to obtain the total area S electricity to be electroplated of the wafer according to the following formula:
Selectricity=pstotal.
In some embodiments, the dimensions of the individual chips comprise the dimensions of dicing streets.
In some embodiments, the metal layer of the single chip is provided with at least one layer, and each layer of metal layer is provided with at least 1 graph, and the graph is an area formed by end-to-end closed lines.
In some embodiments, the area to be electroplated of the metal layer corresponding to the single chip in the design drawing is the sum of all the pattern areas; the total area of a single chip in the design drawing is the product of the parameter values of the single chip in the X direction and the Y direction in the design drawing.
In some embodiments, when calculating the total area of a single chip in a design drawing, comparing the total area of the single chip in the design drawing with the size of the single chip of an input program, and calculating the area ratio P to be electroplated if the data are the same; the data is different, and the data is confirmed manually.
Compared with the prior art, the invention has the beneficial effects that:
The invention provides a CAD expansion program for automatically calculating the electroplating area of a semiconductor metal layer. The expansion program is based on Visual Basic macro language, corresponding program functions are written in VBA, and then the expansion program is applied to CAD to realize the required functions.
According to the method, any metal layer is automatically identified through a program, the area to be electroplated of the corresponding metal layer is calculated, the area to be electroplated of the corresponding metal layer is divided by the total area of a single chip to obtain the proportion P of the area to be electroplated, and the proportion P of the area to be electroplated is multiplied by the total area S of the effective area of the wafer to obtain the total area S electricity to be electroplated of the wafer.
According to the method, the S electric data calculated by the program is utilized to carry out electroplating operation, so that the required metal interconnection layer (RDL) or metal convex blocks are obtained, various human errors of the traditional manual calculation of the area to be electroplated can be effectively avoided, the accuracy of drawing data is greatly improved, reworking is avoided, the maximum possible exchange period is ensured, and the cost is saved.
Drawings
Fig. 1 is a schematic structural diagram of a metal layer corresponding to a single chip in a design diagram according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments.
The embodiment provides a calculation method of the electroplating area of a semiconductor metal layer based on VBA, which is a CAD expansion program. The expansion program is based on Visual Basic macro language, corresponding program functions are written in VBA, and then the expansion program is applied to CAD to realize the required functions.
Specifically, the VBA-based method for calculating the electroplating area of the semiconductor metal layer disclosed in this embodiment includes the following steps:
Firstly, inputting the diameter of a wafer to be electroplated, the size of a single chip in the wafer to be electroplated and the trimming size data of the wafer to be electroplated into a program, wherein the size of the single chip is used as calibration data. The data in this step are based on the product of the wafer to be electroplated, the diameter of the wafer to be electroplated is generally eight inches (200 mm) and twelve inches (300 mm) which are common in the art, and the size of a single chip in the wafer to be electroplated and the trimming size data of the wafer to be electroplated are designed according to the requirements of each product. The size of the individual chips includes the size of the scribe lanes.
Secondly, recognizing the metal layer and the size of a single chip in the design drawing of the wafer to be electroplated through a program, comparing the metal layer and the size with the input size of the single chip, and carrying out the next step after the verification is consistent, otherwise reporting errors; the error reporting module is designed to avoid error drawing of the design drawing, drawing multiple error or error of manually measured data input value, so as to improve the accuracy of the calculation method. The metal layer of a single chip in the design drawing can have multiple layers. At least 1 graph is arranged in each metal graph layer, and the graph is an area formed by closed lines connected end to end. The area of the non-closed line is not calculated, so the VBA program has the function of identifying whether each metal layer contains the non-closed line pattern or not, and can report errors after the program is run.
Further, the program identifies the metal layers corresponding to the single chips in the design drawing of the wafer to be electroplated, and calculates the areas to be electroplated of the metal layers corresponding to the single chips respectively; the total area of the single chip; calculating to obtain an area ratio P to be electroplated;
p=the area to be electroplated of the metal layer corresponding to the single chip/the total area of the single chip;
Obtaining the radius of an effective area of the wafer to be electroplated according to the diameter and the trimming size data of the wafer to be electroplated, and calculating the total area Stotal of the effective area of the wafer by using a mathematical formula pi r 2;
and calculating to obtain the total area S electricity to be electroplated of the wafer according to the following formula:
Selectricity=pstotal.
In this embodiment, the trimming dimension of the wafer to be electroplated refers to removing the outer ring area of the wafer to be electroplated, i.e. the inner ring dimension of the wafer to be electroplated. Since the outer ring region of the wafer does not need to be electroplated, the area is not calculated, and the outer ring region is not calculated when inputting a program.
As shown in fig. 1, the metal pattern layer corresponding to a single chip in the design drawing is identified, 15 patterns are contained in the metal pattern layer, so that the area to be electroplated of the metal pattern layer corresponding to the single chip is the sum of the areas of the 15 patterns, and the area of the single pattern is shown as a reference numeral 2; the total area of the single chip is the product of the parameter values of the single chip in the X direction and the Y direction in the design drawing, and generally, the single chip is rectangular, and then the rectangular area is long, i.e. the total area of the single chip is the part indicated by the reference numeral 1in the drawing. When the total area of the single chip in the design drawing is calculated, comparing the total area of the single chip in the design drawing with the size of the single chip of the manual input program, and calculating the area ratio P to be electroplated if the data are the same; the data is different, and the data is confirmed manually.
From this, the area ratio to be plated can be calculated, p=the area to be plated of the metal layer corresponding to the single chip/the total area of the single chip.
According to the method, any metal layer is automatically identified through a program, the area to be electroplated of the corresponding metal layer is calculated, the area to be electroplated of the corresponding metal layer is divided by the total area of a single chip to obtain the area proportion P to be electroplated, the area proportion P to be electroplated is multiplied by the total area S of the effective area of the wafer to obtain the total area S electricity to be electroplated of the wafer, and the speed of calculating the total area to be electroplated of the wafer is greatly improved. The error reporting program is also arranged in the program, so that errors of drawing errors of the design drawing, drawing multiple errors or manually measured data input values can be avoided, and the accuracy of the calculation method is improved.
The S electric data calculated by the method is subjected to electroplating operation to obtain the required metal interconnection layer (RDL) or metal convex blocks, so that various human errors can be effectively avoided, the accuracy of drawing data is greatly improved, reworking is avoided, the intersection period is ensured to the greatest extent, and the cost is saved.
While only certain embodiments of the present invention have been described, it will be apparent to those skilled in the art that other modifications and improvements can be made without departing from the inventive concept of the present invention.
Claims (5)
1. The calculation method of the electroplating area of the semiconductor metal layer based on VBA is characterized by comprising the following steps:
inputting the diameter of a wafer to be electroplated, the size of a single chip in the wafer to be electroplated and the trimming size data of the wafer to be electroplated into a program, wherein the size of the single chip is used as calibration data;
The program identifies the metal layer and the size of a single chip in the design drawing of the wafer to be electroplated, compares the metal layer and the size with the input size of the single chip, and carries out the next step after the verification is consistent, otherwise, reports errors;
program identification is carried out on a metal layer corresponding to a single chip in a design drawing of a wafer to be electroplated, and the area to be electroplated and the total area of the single chip of the metal layer corresponding to the single chip are calculated respectively; calculating to obtain an area ratio P to be electroplated;
p=the area to be electroplated of the metal layer corresponding to the single chip/the total area of the single chip;
Obtaining the radius of an effective area of the wafer to be electroplated according to the diameter and the trimming size data of the wafer to be electroplated, and calculating the total area Stotal of the effective area of the wafer by using a mathematical formula pi r 2;
and calculating to obtain the total area S electricity to be electroplated of the wafer according to the following formula:
Selectricity=pstotal.
2. The method of claim 1, wherein the dimensions of the individual die comprise dimensions of scribe lanes.
3. The method for calculating the electroplating area of the semiconductor metal layer based on VBA as claimed in claim 2, wherein the metal layer of the single chip is provided with at least one layer, each layer of metal layer is provided with at least 1 graph, and the graph is an area formed by end-to-end closed lines.
4. The method for calculating the electroplating area of the semiconductor metal layer based on VBA according to claim 3, wherein the area to be electroplated of the metal layer corresponding to the single chip in the design drawing is the sum of all the pattern areas; the total area of a single chip in the design drawing is the product of the parameter values of the single chip in the X direction and the Y direction in the design drawing.
5. The method for calculating the electroplating area of the semiconductor metal layer based on VBA according to claim 4, wherein when the total area of a single chip in a design diagram is calculated, the total area of the single chip in the design diagram is compared with the size of the single chip of an input program, and if the data are the same, the area ratio P to be electroplated is calculated; the data is different, and the data is confirmed manually.
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| Publication Number | Publication Date |
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| CN118013914A true CN118013914A (en) | 2024-05-10 |
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