CN118011939A - Low-power consumption management system of multi-power-domain MCU - Google Patents

Abstract

The invention discloses a low-power consumption management system of a multi-power domain MCU, which comprises a VDD domain, a VDDA domain and a VCORE domain, wherein the VDD domain comprises PMU0, an isolation transformer circuit, a linear voltage regulator tube and a reset management unit 0, the VDDA domain comprises an analog peripheral module, and the VCORE domain comprises a CPU module, a reset management unit 1, PMU1, a system configuration module and a digital peripheral module; the PMU0 and the PMU1 are connected through an isolation voltage transformation circuit, a linear voltage stabilizing tube supplies power to the CPU module, and a wake-up circuit and a reset management unit 0 control the PMU0 to reset; the analog peripheral module converts an externally input analog signal into a first digital signal and sends the first digital signal to a VCORE domain; the digital peripheral module inputs the second digital signal, the CPU module generates a sleep mode signal, the PMU1 sets a plurality of low-power modes, and the CPU module selects any low-power mode to switch. The invention sets a plurality of low power consumption modes, effectively reduces the power consumption of the MCU in multiple power domains, reduces the use of special components and reduces the complexity of the circuit.

Description

Low-power consumption management system of multi-power-domain MCU

Technical Field

The invention relates to the field of chips, in particular to a low-power consumption management system of a multi-power-domain MCU.

Background

MCU is totally called Microcontroller Unit, is a little control unit, is also a chip, and in MCU's sustainable development process, its performance and consumption are the important index all the time, and especially along with the sustainable development of thing networking, MCU's demand to the power consumption control further continuously promotes. The low power consumption can not only improve the service life of the system in the battery power supply environment, but also reduce the working temperature of the MCU chip so as to prolong the service life.

At present, the main low-power consumption processing system of the MCU is divided into a plurality of power domains, more clocks and power supplies in the MCU are turned off as much as possible when the CPU does not work, the control of the low-power consumption of the MCU is usually completed by a Power Management Unit (PMU) in cooperation with a clock reset power switch and the like, and meanwhile, the MCU is required to have a response function.

However, the PMU is used for controlling the MCU low power consumption, and the PMU is required to be placed under the normally open domain as a whole, so that the power consumption of the normally open domain is increased; furthermore, the use of PMUs requires the connection of multiple complex special units because of the large amount of interaction signals between the PMUs and the power-down capable domain, which require isolation and voltage transformation during communication, which undoubtedly increases the complexity of the circuit and greatly increases the difficulty of practical circuit design.

Disclosure of Invention

The technical problems to be solved by the invention are as follows: how to reduce the power consumption of the MCU with multiple power domains, and reduce the use of special units and the complexity of circuits.

Aiming at the technical problems, a low-power consumption management system of a multi-power-domain MCU is provided; the method is realized by the following technical scheme:

The low-power consumption management system of the MCU of the multiple power domains comprises a VDD domain, a VDDA domain and a VCORE domain, wherein the VDD domain comprises PMU0, an isolation transformation circuit, a wake-up circuit, clock management unit 0, a linear voltage regulator tube and reset management unit 0, the VDDA domain comprises an analog peripheral module, and the VCORE domain comprises a CPU module, reset management unit 1, PMU1, clock management unit 1, a system configuration module and a digital peripheral module;

The PMU0 and the PMU1 are connected through an isolation transformer circuit, the linear voltage regulator supplies power to the CPU module, the clock management unit 0 is used for providing clock signals for the PMU0, the wake-up circuit is used for sending wake-up signals to the PMU0, and the reset management unit 0 is used for controlling the PMU0 to reset; the analog peripheral module is used for converting an externally input analog signal into a first digital signal and transmitting the first digital signal to the VCORE domain; the digital peripheral module is used for inputting a second digital signal, the CPU module is used for generating a sleep mode signal, the PMU1 sets a plurality of low-power modes based on the first digital signal, the second digital signal and the sleep mode signal, the CPU module selects any low-power mode for switching through the system configuration module, the reset management unit 1 is used for carrying out reset management when the CPU module switches the low-power mode, and the clock management unit 1 is used for providing clock signals for the PMU 1.

A plurality of low-power consumption modes are designed for the MCU in the multiple power domains through the PMU1, so that the MCU in the multiple power domains selects the most suitable low-power consumption mode, and the power consumption is effectively reduced; and the two PMUs are connected by using a simple isolation voltage transformation circuit, so that a plurality of special units which are required to be connected when the PMUs are used are omitted, the complexity of the circuit is reduced, and the design difficulty of an actual circuit is effectively reduced.

Preferably, the low power consumption mode includes a sleep mode, a stop mode, a standby mode, and an off mode. And a plurality of low-power consumption modes are set, so that the MCU with multiple power domains is reasonably selected, and the power consumption can be effectively reduced.

Preferably, the CPU module is provided with a core master clock; when the CPU module enters a sleep mode, the core master clock stops running, and the CPU module stops the current operation; when the digital peripheral module sends any interrupt signal to the CPU module, the CPU module is awakened from the sleep mode. The core master clock and the interrupt signal are utilized to control the sleep mode, so that the operation speed is high, and the method is simple and effective.

Preferably, the clock management unit 1 at least includes a wake-up clock, a reset clock and a turn-off clock; the stop mode is to combine the first digital signal and the second digital signal on the basis of the sleep mode, and stop the operation of other clocks except the wake-up clock in the VCORE domain; when the digital peripheral module sends any interrupt signal to the CPU module, the CPU module is awakened from the stop mode. The stop mode is based on a sleep mode, and the multi-power MCU can enter a lower power consumption state.

Preferably, the standby mode is to power down the VCORE domain in combination with PMU1 based on the sleep mode; after the PMU1 receives the wake-up signal from the wake-up circuit, the CPU module wakes up from the standby mode. And a standby mode is set on the basis of the sleep mode, and the power supply of part of power domains is disconnected, so that the power supply consumption is reduced, and the power consumption is reduced.

Preferably, the off mode is to turn off the linear regulator on the basis of the standby mode; after the PMU1 receives the wake-up signal from the wake-up circuit, the CPU module wakes up from the off mode. The power supply responsible for the linear voltage stabilizing tube can be disconnected by setting the turn-off mode on the basis of the sleep mode, so that the consumption is reduced.

Preferably, the isolation transformer circuit includes an isolation unit and a level shift unit; when PMU1 sends a control signal related to a low power consumption mode to PMU0, an isolation unit is used to generate an isolation signal, the control signal is isolated by the isolation signal, and the isolated control signal is controlled to be in a low level state by a level shifting unit. The control signal is kept in a low level state, so that the subsequent process of entering the low power consumption mode is prevented from being influenced.

Preferably, each of the clock management unit 0 and the clock management unit 1 includes a plurality of clock sources, selectors and gating circuits; the selector is used for selecting a plurality of clock sources, and the gating circuit is used for independently gating each clock source. The selector and the gate control circuit can be used for effectively selecting and controlling the clock source, so that the smooth operation of the chip is ensured.

Preferably, the VDD domain also includes a watchdog circuit that forces the multi-power MCU to restart when the watchdog circuit detects a PMU0 fault. The PMU0 can be effectively monitored by using the watchdog circuit, so that the PMU0 can be timely found and restarted when the operation is in error.

Preferably, the multi-power domain MCU is connected with an nrst reset unit, the wake-up circuit is connected with the nrst reset unit, and the wake-up circuit sends a wake-up signal to the PMU0 when the wake-up circuit obtains a reset signal of the nrst reset unit.

Compared with the prior art, the invention has the following beneficial effects:

The technical scheme of the invention designs a plurality of low-power modes, so that the MCU in a multi-power domain can select a corresponding low-power mode according to actual conditions, thereby effectively reducing power consumption; in addition, two PMUs are used as main components for controlling the low-power consumption mode in two power domains, so that the cost is effectively reduced; in addition, the power-domain transmission of PMU0 and PMU1 is realized by using a simple isolation transformer circuit, the circuit is simplified on the basis of keeping a low-power consumption mode and stably running, the use of redundant special units is omitted, and the cost and the circuit complexity are effectively reduced.

Drawings

FIG. 1 is a schematic diagram of a low power management system of a multi-power domain MCU;

fig. 2 is a schematic diagram of a structure of a isolated transformer circuit in a low power management system of a multi-power domain MCU.

Detailed Description

The following describes the technical solution in the embodiment of the present invention in detail with reference to the drawings in the embodiment of the present invention.

As shown in fig. 1, a structure diagram of a low power management system of a multi-power domain MCU is shown, the multi-power domain includes a VDD domain, a VDDA domain and a VCORE domain, the VDD domain is a main power domain, the VDDA domain is an analog power domain, and the VCORE domain is a core power domain. VDD. The VDD domain is provided with a PMU0, an isolation transformer circuit, a wake-up circuit, a switch 0, a clock management unit 0, a real-time clock, a linear voltage regulator and a reset management unit 0; the VDDA domain is an analog peripheral module, and a switch 1, an ADC, a temperature sensor and a phase-locked loop are arranged in the analog peripheral module; the VCORE domain is provided with a CPU module, a reset management unit 1, a PMU1, a clock management unit 1, a system configuration module and a digital peripheral module, and different modules and different units are connected through buses inside the VCORE domain.

In this embodiment, for the VDD domain, power may be supplied through the external power pin VDD, and the external power pin VDD may supply power to the CPU module through the linear regulator and the switch 0; the clock management unit 0 is responsible for managing clock sources generated in a crystal oscillator inside the crystal oscillator, the crystal oscillator comprises a high-speed internal oscillator (HSI), a high-speed external oscillator (HSE), a low-speed internal oscillator (LSI), a low-speed external oscillator (LSE) and a phase-locked loop (PLL), the phase-locked loop also belongs to one of the oscillators, and a corresponding oscillator or phase-locked loop can be used according to actual requirements, so that corresponding clocks such as an interrupt clock, a reset clock, a wake-up clock and the like are generated for transmitting reset signals to the PMU0, for example, power supply reset, power-off reset, PMU control reset, internal software reset and the like, and the reset management unit can transmit specific reset signals to other devices needing the reset signals through the PMU 0. The wake-up circuit is responsible for connecting an nrst reset unit outside the MCU of the multiple power domains, and when the PMU0 needs to be awakened, the nrst reset unit generates an awakening signal by sending a reset signal to the wake-up circuit and then sends the awakening signal to the PMU0 for awakening operation; the real-time clock is used for generating an alarm clock wake-up signal, transmitting the alarm clock wake-up signal to the PMU0, and setting a fixed time period for the real-time clock, and periodically transmitting the wake-up signal to the PMU0 according to the set time period after entering the low power consumption mode each time, so that the PMU0 returns to a normal working state.

It should be noted that, the multi-power domain MCU of the present invention includes three power domains, and if one power domain enters the low power mode, it is equivalent to the multi-power domain MCU entering the low power mode; if two power domains or even three power domains enter the low power consumption mode, the MCU enters the low power consumption mode in the same way as the MCU with multiple power domains.

In this embodiment, for the VDDA domain, the analog peripheral module receives an external analog power supply, controls the power supply of the analog power supply by using the switch 1, and the temperature sensor receives an external temperature signal, then converts the temperature signal into an analog signal and sends the analog signal to the ADC analog-to-digital converter, the analog signal is converted into a first digital signal by the ADC analog-to-digital converter, and then the first digital signal is adjusted by a signal of the phase-locked loop, so as to ensure that the phase of the first digital signal is stable and clock synchronization when the first digital signal is transmitted to the VCORE domain.

Specifically, the first digital signal is transmitted to the digital peripheral module in the VCORE domain, and then is sent to the CPU module for corresponding processing through the digital peripheral module and the bus. In addition, since the digital peripheral module itself can transmit the second digital signal to the CPU module through the bus, the CPU module can process the signal in three cases: 1) Only the first digital signal is generated, the second digital signal is not generated, and the CPU module processes the first digital signal; 2) Only the second digital signal, the first digital signal is not generated, and the CPU module processes the second digital signal; 3) The method comprises the steps that a first digital signal and a second digital signal exist, priorities are set for the two signals in a CPU module at the moment, and signals with high priorities are processed first; the priority setting standard can be the sequence of two signals entering the CPU module, or the first digital signal is set in advance or the second digital signal is set in advance, and the specific priority can be set by oneself according to the actual production requirement and the functional requirement.

In this embodiment, for the VCORE domain, the clock management unit 1 has the same structure as the clock management unit 0, and the digital peripheral module is used for inputting the second digital signal, and the CPU module is built in with a sleep mode, so that the CPU module can generate a sleep mode signal. At any time, the digital signal in the VCORE domain may have only the first digital signal, may have only the second digital signal, and may have both the first digital signal and the second digital signal, so that the PMU1 needs to set multiple low power modes based on the digital signal and the sleep mode signal that the CPU module currently needs to process, the CPU module may determine the low power mode to be selected by reading the register file in the system configuration module to perform mode switching, the reset management unit 1 is configured to send a reset signal to the unit or module to be reset through the bus when the CPU module switches the low power mode, and the clock management unit 1 is responsible for providing the corresponding clock needed when resetting for the PMU 1.

In this embodiment, a storage module is further provided in the VCORE domain, where the storage module includes a DMA, a FLASH memory, and an SRAM memory, and the three components are all connected to a bus, where the DMA is a direct memory access module, and is capable of performing data access; FLASH memory is a non-volatile memory capable of storing data after power failure; the SRAM memory is a random access memory, and can access, read or write data at any position at any given time, and the speed is high. When the first digital signal or the second digital signal is processed, the DMA data access memory may be needed, or the random access of the SRAM memory may be used, and when the low power consumption mode requiring power failure is entered, the FLASH FLASH memory can also store the data, so that other units and modules can work normally after power is supplied again.

In this embodiment, five clock sources are respectively disposed in the two clock management units, and the working clocks in different modes can be provided for the whole multi-power domain MCU by software control and selecting clocks corresponding to specific clock sources by the power management unit. Specifically, a selector, a frequency divider and a gating circuit are further arranged in each clock management unit, the selector is used for selecting clock sources, the distributor can divide frequency of clock signals generated by part of the clock sources, and the gating circuit can realize independent gating of different peripheral clocks through software control and hard control words of corresponding PMUs.

In this embodiment, each reset management unit has a plurality of reset sources therein, where the reset sources include a power-on reset, a power-off reset, an under-voltage reset, an external pin reset, an internal software reset, and a power management unit control reset. The power-on reset signal is used for controlling the MCU in the multiple power domains to start reset; the power-down reset is used for generating power domain MCU reset when the voltage drops; the under-voltage reset is used for generating power domain MCU reset when under-voltage conditions occur; the external pin reset is used for external enabling reset, wherein enabling is an enabling state or an enabling signal, and is generally used for inputting and outputting control signals; the internal software reset is used for resetting the peripheral in the software execution process; the power management unit controls the reset to control the power down domain to reset when the low power consumption mode is executed. Each reset management unit is connected with the corresponding power management unit, and when the corresponding reset is needed, the corresponding reset source and the corresponding power management unit are directly used for completing the corresponding reset.

Regarding the low power consumption mode, the CPU configures different registers to enter different low power consumption modes through the PMU1, the PMU1 generates enabling signals corresponding to different low power consumption modes, such as sleep_en enabling signals for sleep modes, en is totally called enable, en represents enabling, stop_en for stop mode, standby_en for standby mode and shutdown_en for off mode, and state control of the MCU in multiple power domains is realized through related circuits connected through the PMU 1.

In this embodiment, the low power consumption modes include a sleep mode, a stop mode, a standby mode and an off mode, and the operation modes of the respective modules in the four different low power consumption modes are as follows:

(1) Sleep mode, i.e. sleep mode

The sleep mode is based on the CPU module, the CPU module core master clock is closed to realize low power consumption, and the CPU module core master clock is opened when the wake-up is needed. When entering the sleep mode, the main clock of the CPU module kernel is stopped, and the execution of the instruction is suspended; the interrupt signal of any peripheral module can wake up the CPU module from the sleep mode. In addition, other peripheral devices can be connected to the VCORE domain, and a part of clocks of the VCORE domain can be further turned off through software control of the peripheral devices, so that power consumption is reduced again.

(2) Stop mode, i.e. stop mode

The stop mode is implemented in combination with a clock control mechanism of the peripheral based on a sleep mode of the CPU module core, which may be responsible for transmission by the first digital signal or the second digital signal. In the VCORE domain in the stop mode, other clocks stop running except the free running clock serving as a wake-up module in the CPU module core, and the functions of HSI and HSE are forbidden; LSIs and LSEs remain operational for timing and interrupting the current stop mode and interrupting the free running clock of the CPU module core when wakeup is required.

(3) Standby mode, i.e. standby mode

The standby mode is realized by combining the power control of the PMU1 on the basis of the sleep mode of the kernel module of the CPU module, the power switch of the VCORE domain is closed, the VCORE domain is completely powered off, namely, other digital circuits except the VDD domain are powered off, and the power switch of the VDDA domain is closed. Only the actual pins corresponding to the wake-up circuit are lifted, and various reset signals can wake up the MCU from the standby mode.

(4) Off mode, i.e. shutdown mode

The off mode turns off more modules on the basis of the standby mode, the power consumption is lower, and the difference between the off mode and the standby mode is that the off mode further turns off the linear voltage stabilizing tube, so that the low-speed crystal oscillator in the crystal oscillator is enabled to be invalid, the electricity and the power consumption are further saved, and only the rising and falling of the actual pins corresponding to the wake-up circuit and the external nrst reset unit have wake-up functions.

In this embodiment, the PMU is a main module for controlling the low power consumption function. The PMU is divided into a PMU0 part and a PMU1 part according to a power domain, the PMU0 and the PMU1 are connected through an isolation transformer circuit, wherein the PMU0 is positioned in a VDD domain, a control state machine circuit 0 and a circuit for controlling a crystal oscillator switch and a power switch are mainly arranged in the PMU, and the PMU1 is positioned in a VCORE domain, and is mainly provided with a control state machine circuit 1, a clock gating generation circuit and a kernel handshake circuit. A control state machine circuit; the clock gating generation circuit can generate gating and hard control words corresponding to the gating so as to be matched with the clock management unit; the kernel handshake circuit can detect whether a sleep signal of the CPU module is valid, and generates an enable sleep_en signal under the condition that the sleep signal is valid, so that subsequent low-power-consumption mode switching operation is performed.

As shown in FIG. 2, the isolation unit circuit is composed of isolation cell isolation cells and LEVELSHIFT CELL level shifting cells, since PMU0 is in the VDD domain, PMU1 is in the VCORE domain, signals need to be transmitted across the power domain when performing low power control, and specifically designed enable sum signals include en_stop, en_stdby, en_ stdn, sleep_en of PMU1 enable control PMU0 and APB interface signals for configuring the VDD domain registers, the signals for generating isolation signal isolation_n are isolated before PMU0 controls the VCORE domain to power down, the level is changed to be low level 0, and after the VCORE domain is powered down, the signals continue to keep low level, avoiding affecting the subsequent low power control flow.

In this embodiment, the VDD domain is further provided with a watchdog circuit, the watchdog circuit is connected to the PMU0 and monitors the running condition of the PMU0 in real time, and when the watchdog circuit monitors that the PMU0 is in error, the watchdog circuit can force the multi-power MCU to restart, so as to avoid the influence of error data.

Specific application example:

In the multi-power domain MCU, the multi-power domain includes a VDD domain, a VDDA domain, which is a main power domain, and a VCORE domain, which is an analog power domain. The VDD domain is provided with a PMU0, an isolation transformer circuit, a wake-up circuit, a switch 0, a clock management unit 0, a real-time clock, a watchdog circuit, a linear voltage regulator and a reset management unit 0; the VDDA domain is an analog peripheral module, and a switch 1, an ADC, a temperature sensor and a phase-locked loop are arranged in the analog peripheral module; the VCORE domain is provided with a CPU module, a reset management unit 1, a PMU1, a clock management unit 1, a storage module, a system configuration module and a digital peripheral module, and different modules and different units are connected through buses inside the VCORE domain.

The MCU in multiple power domains starts to normally Run and is in a Run state, the external pin of the VDD domain supplies 3.3V to the VDD domain, and the power is supplied to the CPU module by 1.2V through the voltage reduction of the linear voltage stabilizing tube and the closed switch 0. The real-time clock monitors the PMU0 timestamp and a fixed wake-up time period is set, and the watchdog circuit also monitors PMU0 in real-time and restarts PMU0 when it is detected that it is running in error.

The switch 1 is closed in the VDDA domain, the temperature sensor receives a temperature signal, converts the temperature signal into an analog signal and inputs the analog signal into the ADC, the analog signal is converted into a first digital signal, and then the first digital signal is subjected to signal synchronization adjustment of the phase-locked loop and then is sent to the digital peripheral module of the VCORE domain, and the digital peripheral module has no signal to be sent at the moment, namely, only one first digital signal needs to be executed and processed at the moment in the VCORE domain. The CPU module reads the first digital signal from the bus, reads the corresponding data required by the signal from the memory module, and then executes the first digital signal.

According to the information contained in the first digital signal, the multi-power domain MCU needs to enter a stop mode for a period of time. Then, the low power consumption instruction corresponding to sleep mode is executed in the CPU module kernel, and the CPU module kernel outputs three signals: sleep signal, sleep signal active and GATEHCLK; and turning off the free running clock HCLK of the CPU module kernel according to GATEHCLK, and stopping the HCLK. After the core handshake circuit of the PMU1 detects that the sleep signal is valid, the core handshake is completed, and an enable sleep_en signal is generated. The PMU1 controls the clock of the digital peripheral module to be turned off according to the sleep_en signal and the data in the register of the system configuration module, controls the memory module to enter a sleep mode, and generates an en_stop signal after the completion; the en_stop signal is transmitted via an isolation transformer to PMU0, through which PMU0 turns off HSI, PLL, HSE in the clock generation block while the HSI_stable (HSI stable flag) is cleared, at which point the MCU enters a stop mode. At this time, in the isolation transformer, the isolation unit inside the isolation transformer generates an isolation signal to isolate the en_stop signal, and the level shift unit inside the isolation transformer controls the signal in a low level state. After entering a stop mode for a period of time, the digital peripheral module sends a stop mode interrupt signal to the CPU module through a bus, the CPU module outputs a wake-up signal at the moment, a core handshake circuit of the PMU1 invalidates a sleep_en signal after detecting the wake-up signal, the corresponding en_stop is invalidated, then the HSI is opened and reaches a threshold value through the counting of an HSI counter, and the HSI_stable signal is changed into valid again; the reset management unit 1 sends a reset signal to the clock management unit 1 through a bus, the clock management unit 1 regenerates a clock adopted in normal operation, and the PMU1 regenerates the clock corresponding to the normal operation; then, PMU1 sends a reset signal to PMU0 through the isolation transformer, and PMU0 also controls clock management unit 0 and reset management unit 0 to perform a reset after receiving the reset signal. Then the MCU in the multiple power domains successfully exits the stop mode and returns to the normal Run state again, namely returns to the normal running state again.

After the digital peripheral module inputs the second digital signal, the CPU module receives and executes the signal and then discovers that the MCU with multiple power domains needs to enter a standby mode for a period of time. Then, the low power instruction corresponding to sleep mode is executed first in the CPU module core, the CPU module core output GATEHCLK, SLEEPING and the sleep signal are valid, and the free running clock HCLK of the CPU module core is turned off according to GATEHCLK. After the core handshake circuit of the PMU1 detects that the sleep signal is valid, the core handshake is completed, and an enable sleep_en signal is generated. The PMU1 controls and turns off the clock of the digital peripheral module according to the sleep_en signal and the data in the register file, generates an en_ stdby signal after the clock is completed, turns off a phase-locked loop (PLL) and an HSE (high speed) in the clock generation module through the signal, pulls up an isolation signal, enables a reset signal of a VCORE domain, enables an invalid power switch after the reset signal is effective, so that the VCORE domain is powered off, enables invalid en_hsi, namely, invalidates a high-speed clock signal in a crystal oscillator, then turns off the HSI, simultaneously clears the HSI_stable, and the MCU enters a standby mode. After entering a standby mode for a period of time, the digital peripheral module inputs a wake-up signal again to generate a wake-up flag, the wake-up signal controls to turn on an HSI and a power switch, after the count of the HSI counter reaches a threshold value, the HSI_stable signal becomes effective again, the PMU1 regains a clock corresponding to normal operation, the reset management unit 1 releases the reset signal, the clock management unit generates a clock corresponding to the normal operation state, the multi-power domain MCU exits from the standby mode and returns to the normal operation state again.

Finally, the digital peripheral module inputs new digital signals, the COU module finds that the MCU in the multiple power domains needs to be put into an off mode for a period of time for rest, and then firstly enters the standby mode according to the method for entering the standby mode, the HSI_stable is emptied, the linear voltage stabilizing tube is closed, and the MCU in the multiple power domains enters the off mode. After entering the off mode for a period of time, a fixed wake-up period set by the real-time clock is not reached, but at the moment, the wake-up circuit receives a wake-up signal of the nrst reset unit, generates wakeup_flag and transmits the wakeup_flag into the PMU0, the PMU0 controls to open the HSI and the linear voltage stabilizing tube according to the signal, after the count of the HSI counter reaches a threshold value, the HSI_stable signal becomes effective again, the PMU1 restarts to operate, the reset management unit 1 releases the reset signal to the PMU1, the CPU module and the clock management unit 1, the VCORE domain returns to a normal operating state, the multi-power domain MCU exits from the off mode and returns to the normal operating state again.

In summary, the invention designs a plurality of low power consumption modes for the multi-power supply MCU, so that the multi-power supply domain MCU can select a corresponding low power consumption mode according to actual conditions, thereby effectively reducing power consumption; in addition, the PMU is used as a main component for controlling the low-power consumption mode, so that the cost is effectively reduced; in addition, the power-domain transmission of PMU0 and PMU1 is realized by using a simple isolation transformer circuit, the circuit is simplified on the basis of keeping a low-power consumption mode and stably running, the use of redundant special units is omitted, and the cost and the circuit complexity are effectively reduced.

The above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereto, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the present invention.

Claims (10)

1. The low-power consumption management system of the MCU in the multiple power domains comprises a VDD domain, a VDDA domain and a VCORE domain, and is characterized in that the VDD domain comprises a PMU0, an isolation transformer circuit, a wake-up circuit, a clock management unit 0, a linear voltage regulator tube and a reset management unit 0, the VDDA domain comprises an analog peripheral module, and the VCORE domain comprises a CPU module, a reset management unit 1, a PMU1, a clock management unit 1, a system configuration module and a digital peripheral module;

The PMU0 and the PMU1 are connected through an isolation transformer circuit, the linear voltage regulator supplies power to the CPU module, the clock management unit 0 is used for providing clock signals for the PMU0, the wake-up circuit is used for sending wake-up signals to the PMU0, and the reset management unit 0 is used for controlling the PMU0 to reset; the analog peripheral module is used for converting an externally input analog signal into a first digital signal and transmitting the first digital signal to the VCORE domain; the digital peripheral module is used for inputting a second digital signal, the CPU module is used for generating a sleep mode signal, the PMU1 sets a plurality of low-power modes based on the first digital signal, the second digital signal and the sleep mode signal, the CPU module selects any low-power mode for switching through the system configuration module, the reset management unit 1 is used for carrying out reset management when the CPU module switches the low-power mode, and the clock management unit 1 is used for providing clock signals for the PMU 1.

2. The low power management system of a multi-power domain MCU of claim 1, wherein the low power modes include a sleep mode, a stop mode, a standby mode, and an off mode.

3. The low power consumption management system of the multi-power domain MCU according to claim 2, wherein the CPU module is provided with a core master clock; when the CPU module enters a sleep mode, the core master clock stops running, and the CPU module stops the current operation; when the digital peripheral module sends any interrupt signal to the CPU module, the CPU module is awakened from the sleep mode.

4. The low power consumption management system of a multi-power domain MCU according to claim 2, wherein the clock management unit 1 comprises at least a wake-up clock, a reset clock and a turn-off clock; the stopping mode is to combine the first digital signal and the second digital signal on the basis of the sleep mode, and stop the operation of other clocks except the wake-up clock in the VCORE domain; when the digital peripheral module sends any interrupt signal to the CPU module, the CPU module is awakened from the stop mode.

5. The low power management system of a multi-power domain MCU of claim 2, wherein the standby mode is to power down the VCORE domain in combination with PMU1 on a sleep mode basis; after the PMU1 receives the wake-up signal from the wake-up circuit, the CPU module wakes up from the standby mode.

6. The low power management system of a multi-power domain MCU of claim 2, wherein the off mode is to turn off a linear regulator on a standby mode basis; after the PMU1 receives the wake-up signal from the wake-up circuit, the CPU module wakes up from the off mode.

7. The low power consumption management system of the multi-power domain MCU of claim 1, wherein the isolation transformer circuit comprises an isolation unit and a level shift unit; when PMU1 sends a control signal related to a low power consumption mode to PMU0, the isolation unit is used for generating an isolation signal, the control signal is isolated by the isolation signal, and the isolated control signal is controlled to be in a low level state by the level shifting unit.

8. The low power consumption management system of a multi-power domain MCU according to claim 1, wherein each of the clock management unit 0 and the clock management unit 1 comprises a plurality of clock sources, selectors and gating circuits; the selector is used for selecting a plurality of clock sources, and the gating circuit is used for independently gating each clock source.

9. The low power management system of a multi-power domain MCU of claim 1, wherein the VDD domain further comprises a watchdog circuit that forces the multi-power MCU to restart when the watchdog circuit detects a PMU0 error.

10. The low power consumption management system of the multi-power domain MCU according to claim 1, wherein the multi-power domain MCU is connected with an nrst reset unit, the wake-up circuit is connected with the nrst reset unit, and the wake-up circuit sends a wake-up signal to the PMU0 when the wake-up circuit obtains a reset signal of the nrst reset unit.