CN115392161A - Power consumption management circuit and method for multi-core processor - Google Patents

Power consumption management circuit and method for multi-core processor Download PDF

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Publication number
CN115392161A
CN115392161A CN202211001986.5A CN202211001986A CN115392161A CN 115392161 A CN115392161 A CN 115392161A CN 202211001986 A CN202211001986 A CN 202211001986A CN 115392161 A CN115392161 A CN 115392161A
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power consumption
state machine
power
management circuit
consumption state
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田泽
郭蒙
李彬
马晗
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Xian Xiangteng Microelectronics Technology Co Ltd
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Xian Xiangteng Microelectronics Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

The invention relates to a power consumption management circuit and a power consumption management method for a multi-core processor. The circuit comprises a power consumption control unit, wherein the power consumption control unit comprises a power consumption state machine, a power consumption state conversion state machine and a power supply control state machine, the power consumption state machine is connected with the power consumption state conversion state machine, and the power consumption state conversion state machine is connected with the power supply control state machine. The invention realizes the definition of various low power consumption states through various power domain divisions, realizes the power consumption management of each level of the kernel, the cluster and the chip, can effectively reduce the static power consumption of the multi-core processor, and improves the reliability of the processor.

Description

Power consumption management circuit and method for multi-core processor
Technical Field
The invention belongs to the field of digital integrated circuit design, and particularly relates to a power consumption management circuit of a multi-core processor.
Background
With the development of integrated circuit technology, from the earliest vacuum tube and transistor circuit to the latter medium and small scale integrated circuit, and then to the present very large scale integrated circuit and System On Chip (soc), the integrated circuit industry is constantly developing towards the direction of high performance, high integration and high complexity, and each field of military, civil affairs and other industries increasingly depends On the development of the integrated circuit industry.
In the early development stage of integrated circuits, the power consumption problem of the circuits is not obvious because the circuit scale is not large and the circuit function requirement is not high. The circuit performance is enhanced due to the Complementary Metal Oxide Semiconductor (CMOS), the circuit area is reduced, the circuit power consumption is optimized, and the circuit cost is greatly reduced, so that the power consumption problem is relatively rarely considered. Taking the first generation of personal computer as an example, using the 8088 central processing unit of Intel corporation at that time, a 31am process is adopted, which includes 2.9 ten thousand transistors, and the peak value of power consumption for the processor chip to operate is only 1.7W. With the continuous upgrade of semiconductor processes, the advent of the latest deep sub-micron scale processes has created a series of design challenges. When a semiconductor process enters a deep submicron stage, namely a process starts from 130nm, a chip integrates tens of millions of transistors, the working frequency of the chip is increased sharply, the power consumption density and the overall power consumption of the chip are increased greatly, the power consumption of a multi-core processor chip can even reach 100-150W, the average power consumption density per square centimeter is as high as 50.75W, the power consumption of local hot spots is multiple times of the average power consumption density, and the power consumption problem of a circuit cannot be ignored. In the field of very large scale integrated circuits, with the continuous progress of semiconductor manufacturing technology, especially after reaching the mainstream nanometer-scale process at present, the problem of circuit power consumption can cause a series of problems. Too high power consumption may affect the reliability of the chip. The power consumption generated by the chip operation is dissipated in the form of heat, and the chip operation temperature is increased when the circuit power consumption is too large. The physical characteristics of the transistor can be changed when the temperature rises to a certain degree, and the normal operation of the chip is influenced. Studies have shown that the failure rate of circuit operation doubles every 10 degrees of temperature rise, compared to the temperature under normal operating conditions. The high and low power consumption determines the packaging form of the chip. The chip with lower working temperature adopts a plastic packaging form; the chip with higher working temperature needs to adopt a ceramic packaging form with higher cost to prevent the chip from being burnt; under the condition that the working temperature of the chip is higher, more complex cooling devices such as liquid cooling, air cooling and the like are required. The power consumption of the chip directly determines the packaging and heat dissipation costs. These issues have caused more designers to be concerned with low power design issues, where power consumption may in some cases even replace performance as a major guide for chip design.
The total power consumption of the chip comprises two parts of dynamic power consumption and static power consumption. When a semiconductor process enters a 90nm stage, leakage current exponentially increases, so that static power consumption becomes inconsiderable in the whole power consumption of a chip, in some 65nm chip designs, the leakage current is almost as large as dynamic current, the proportion of the static power consumption in the total power consumption is increasingly large, and the static power consumption which can be ignored in the design becomes to be considered as the dynamic power consumption. Therefore, low power consumption design featuring static power consumption reduction becomes a new focus of current Ic designers, and the size of static power consumption directly affects the market prospect of mobile devices, and determines the success or failure of chip design.
Disclosure of Invention
In order to solve the technical problems in the background technology, the invention provides a power consumption management circuit and a power consumption management method for a multi-core processor.
The technical solution of the invention is as follows: the invention relates to a power consumption management circuit of a multi-core processor, which is characterized in that: the multi-core processor power consumption management circuit comprises a power consumption control unit, wherein the power consumption control unit comprises a power consumption state machine, a power consumption state conversion state machine and a power supply control state machine, the power consumption state machine is connected with the power consumption state conversion state machine, and the power consumption state conversion state machine is connected with the power supply control state machine.
Further, the power consumption state machine is a kernel power consumption state machine or a Cluster power consumption state machine.
Further, when the power consumption state machine is a kernel power consumption state machine, the power control state machine is connected with a kernel of the processor through a P-Channel interface.
Furthermore, when the power consumption state machine is a Cluster power consumption state machine, the power supply control state machine is connected with the Cluster of the processor through a P-Channel interface.
Furthermore, the power consumption control units are in a plurality of groups.
Furthermore, the multi-core processor power consumption management circuit further comprises a register module, and the register module is respectively connected with the multiple groups of power consumption control units.
Furthermore, the power consumption management circuit of the core processor also comprises an APB interface, and the APB interface is connected with the register module.
A method for realizing the power consumption management circuit of the multi-core processor is characterized in that: the method comprises the following steps:
1) The power-off process:
writing the power-off configuration information into a register module through an APB interface, controlling a power consumption state machine through an internal signal by the register module to initiate power consumption state conversion, initiating a power consumption state conversion request and controlling the power supply control state machine to start through a P-Channel interface by the power consumption state conversion state machine, controlling the kernel or a Cluster power domain of a processor to perform power-off operation by the power supply control state machine, controlling the actions of a power switch, an isolation unit and a reset unit according to the configuration information of the register module in the power-on and power-off process of a power supply, completing the power-off operation according to the correct sequence, and enabling the kernel or the Cluster to enter a power-off mode;
2) And (3) electrifying:
writing the power-on configuration information into a register module through an APB interface, controlling a power consumption state machine through an internal signal by the register module, initiating power consumption state conversion, initiating a power consumption state conversion request and controlling the start of a power supply control state machine through a P-Channel interface by the power consumption state conversion state machine, and controlling a kernel or a Cluster power domain to carry out power-on operation by the power supply control state machine; in the power supply electrifying process, the actions of the power switch, the isolation unit and the reset unit are controlled according to the configuration information of the register module, the electrifying operation is completed according to the correct sequence, and the kernel or the Cluster enters a normal working mode.
The power consumption management circuit and method of the multi-core processor provided by the invention utilize a design method combining software and hardware and a traditional low-power-consumption design means, combine a low-power-consumption design flow based on UPF, provide a support technology by hardware and optimize the power consumption of a chip by software driving. The hardware implementation defines various low-power consumption states to realize the power consumption management of the kernel, the cluster and each level of the chip through clock gating and various power domain divisions. All power consumption mode conversion is controlled by a chip mode management module of the system management circuit. The power states of the processors are configured by the user at the startup phase according to application requirements. According to the power consumption requirement, the processor can be selectively placed in different power consumption management states.
Drawings
FIG. 1 is a schematic circuit diagram of the present invention;
FIG. 2 is a diagram illustrating the transition between power states of the core according to the present invention;
fig. 3 is a schematic diagram of Cluster power consumption state transition according to the present invention.
The reference numerals are illustrated below:
1. a core0 power consumption control unit; 2. a core1 power consumption control unit; 3. a Cluster0 power consumption control unit; 4. a core3 power consumption control unit; 5. a core4 power consumption control unit; 6. a Cluster1 power consumption control unit; 7. a core5 power consumption control unit; 8. a core6 power consumption control unit; 9. a Cluster2 power consumption control unit; 10. a core7 power consumption control unit; 11. a core8 power consumption control unit; 12. a Cluster3 power consumption control unit; 13. an APB interface; 14. and a register module.
Detailed Description
The technical solution of the present invention is further described in detail with reference to the accompanying drawings and specific embodiments.
The power consumption management circuit of the multi-core processor can realize the power consumption management of a plurality of groups of cores and clusters.
Referring to fig. 1, the power management circuit of the multicore processor according to the preferred embodiment of the present invention includes 12 power consumption control units: for managing power consumption of 8 cores and 4 clusters, respectively.
Each power consumption control unit is provided with an independent power consumption state machine, a power consumption state conversion state machine and a power supply control state machine, wherein the power consumption state machines are connected with the power consumption state conversion state machines, and the power consumption state conversion state machines are connected with the power supply control state machines.
And the power consumption state machine is used for managing the current power consumption state.
And the power consumption state conversion state machine is used for controlling the conversion process before the power consumption mode, initiating a power consumption state conversion request through a P-Channel interface and controlling the power supply to control the start of the state machine.
The power supply control state machine controls the power-on and power-off sequence of each power supply domain, controls the actions of the power switch, the isolation unit and the reset unit in the power-on and power-off process of the power supply and completes the operation of the power switch, the isolation unit and the reset unit in a correct sequence.
The system is communicated with the cores and the cluster of the processor through P-Channel interfaces, each core is provided with an independent P-Channel interface, and each cluster is provided with an independent P-Channel interface. The kernel provides the current state via the PACTIME signal and initiates the mode transition via the PREQ and PSTATE signals. The processor writes power-up and power-down configuration information to the register module 14 through the APB interface 13.
Each core and the Cluster correspond to a power consumption state machine to control the current power consumption state.
The 12 power consumption control units have the following structures:
the core0 power consumption control unit 1 comprises a core power consumption state machine 101, a power consumption state transition state machine 102 and a power supply control state machine 103;
the core1 power consumption control unit 2 comprises a core power consumption state machine 201, a power consumption state transition state machine 202 and a power supply control state machine 203;
the Cluster0 power consumption control unit 3 comprises a Cluster power consumption state machine 301, a power consumption state conversion state machine 302 and a power supply control state machine 303;
the core3 power consumption control unit 4 includes a core power consumption state machine 401, a power consumption state transition state machine 402, and a power control state machine 403;
the core4 power consumption control unit 5 comprises a core power consumption state machine 501, a power consumption state transition state machine 502 and a power supply control state machine 503;
the Cluster1 power consumption control unit 6 comprises a Cluster power consumption state machine 601, a power consumption state conversion state machine 602 and a power supply control state machine 603;
the core5 power consumption control unit 7 includes a core power consumption state machine 701, a power consumption state transition state machine 702, and a power control state machine 703;
the core6 power consumption control unit 8 includes a core power consumption state machine 801, a power consumption state transition state machine 802, and a power control state machine 803;
the Cluster2 power consumption control unit 9 comprises a Cluster power consumption state machine 901, a power consumption state transition state machine 902 and a power supply control state machine 903;
the core7 power consumption control unit 10 includes a core power consumption state machine 1001, a power consumption state transition state machine 1002, and a power control state machine 1003;
the core8 power consumption control unit 11 includes a core power consumption state machine 1101, a power consumption state transition state machine 1102, and a power control state machine 1103;
the Cluster3 power consumption control unit 12 comprises a Cluster power consumption state machine 1201, a power consumption state transition state machine 1202 and a power supply control state machine 1203;
the register module 14 is connected with a core power consumption state machine 101, a core power consumption state machine 201, a Cluster power consumption state machine 301, a core power consumption state machine 401, a core power consumption state machine 501, a Cluster power consumption state machine 601, a core power consumption state machine 701, a core power consumption state machine 801, a Cluster power consumption state machine 901, a core power consumption state machine 1001, a core power consumption state machine 1101 and a Cluster power consumption state machine 1201 respectively. The register module 14 is externally connected with an APB interface 13.
The working processes of the power consumption management circuits of 8 cores and 4 clusters are the same, and the working process of the power consumption management circuit is described by taking the core0 as an example:
the power-off process:
the power-off configuration information is written into the register module 14 through the APB interface 13, and the register module 14 controls the power consumption state machine 101 through an internal signal to initiate power consumption state transition. The power consumption state transition state machine 102 initiates a power consumption state transition request and controls the power control state machine 103 to start through the P-Channel interface. The power control state machine 103 controls the core0 power domain to power down. In the power-on and power-off process of the power supply, the actions of the power switch, the isolation unit and the reset unit are controlled according to the configuration information of the register module 14, the power-off operation is completed in a correct sequence, and the core0 enters a power-off mode.
Power-on process
The power-on configuration information is written into the register module 14 through the APB interface 13, and the register module controls the power consumption state machine 101 through the internal signal to initiate power consumption state transition. The power consumption state transition state machine 102 initiates a power consumption state transition request and controls the power control state machine 103 to start through the P-Channel interface. The power control state machine 103 controls the core0 power domain to power up. In the power-on process, the actions of the power switch, the isolation unit and the reset unit are controlled according to the configuration information of the register module 14, the power-on operation is completed in a correct sequence, and the core0 enters a normal working mode.
In order to solve the problem that under the application environment of a multi-core processor, static power consumption of the processor in an idle state is reduced, so that the reliability of the processor is improved, and the problem of heat dissipation caused by overhigh power consumption is solved, the invention provides a hierarchical power consumption control circuit structure of the multi-core processor, wherein a group of register modules 14 and 12 power consumption control units which can be accessed by an APB interface 13 are arranged in the circuit and are respectively used for managing the power consumption of 8 cores and 4 clusters. Each power consumption control unit is provided with an independent power consumption state machine, a power consumption state conversion state machine and a power supply control state machine, and a means for effectively reducing power consumption is provided for the multi-core processor in practical application.
Referring to fig. 2, the core power consumption state transition is schematically shown as follows:
the core power consumption states include: a power-on state, a power-off state, a sleep state, a stop state, and a debug resume state. The power-on state can be converted into any other state; the debug resume state can be entered from any state, but can only be exited to a power-on state. The sleep state can be entered only from the power-on state, and the sleep state can be exited only from the power-on state. The power-off state can be entered from the stop state only, the power-off state is exited, and the stop state or the power-on state can be entered. When the kernel is switched from the power-off state to the power-on state, the cluster must be in the power-on state.
Referring to FIG. 3, the cluster state transition is schematically shown as follows:
the Cluster power consumption states include a power-up state and a power-down state. After the kernel in the cluster is completely powered off, the power-off state can be entered from the power-on state.
Explanation of the name:
the state of each core:
power-On state (On): starting a kernel power domain;
power Off state (Off): the kernel power domain is closed;
sleep state (sleep): the clock of the core is cut off;
stop state (Stop): the kernel is reset effectively, and the kernel is in a stop state;
debug resume state (Debug Recovery): the debug resume mode may be used to assist in debugging external watchdog timer triggered reset events. It allows the contents of the core L1 data cache before reset to be viewed after reset. The L1 cache contents are retained and do not change upon transitioning back to the On mode.
Status of each cluster:
power-On state (Cluster _ On): the top layer power domain is started;
power-Off state (Cluster _ Off): the top power domain is turned off.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (8)

1. A multi-core processor power consumption management circuit, characterized by: the multi-core processor power consumption management circuit comprises a power consumption control unit, wherein the power consumption control unit comprises a power consumption state machine, a power consumption state conversion state machine and a power supply control state machine, the power consumption state machine is connected with the power consumption state conversion state machine, and the power consumption state conversion state machine is connected with the power supply control state machine.
2. The multicore processor power consumption management circuit of claim 1, wherein: the power consumption state machine is a kernel power consumption state machine or a Cluster power consumption state machine.
3. The multi-core processor power consumption management circuit of claim 2, wherein: and when the power consumption state machine is a kernel power consumption state machine, the power supply control state machine is connected with the kernel of the processor through a P-Channel interface.
4. The multicore processor power consumption management circuit of claim 2, wherein: and when the power consumption state machine is a Cluster power consumption state machine, the power supply control state machine is connected with the Cluster of the processor through a P-Channel interface.
5. The multi-core processor power consumption management circuit of any of claims 1 to 4, wherein: the power consumption control units are in a plurality of groups.
6. The multicore processor power consumption management circuit of claim 5, wherein: the multi-core processor power consumption management circuit further comprises a register module, and the register module is respectively connected with the multiple groups of power consumption control units.
7. The multi-core processor power consumption management circuit of claim 6, wherein: the multi-core processor power consumption management circuit further comprises an APB interface, and the APB interface is connected with the register module.
8. A method of implementing the multi-core processor power consumption management circuit of claim 1, wherein: the method comprises the following steps:
1) The power-off process:
writing the power-off configuration information into a register module through an APB interface, controlling a power consumption state machine through an internal signal by the register module to initiate power consumption state conversion, initiating a power consumption state conversion request and controlling the power supply control state machine to start through a P-Channel interface by the power consumption state conversion state machine, controlling the kernel or a Cluster power domain of a processor to perform power-off operation by the power supply control state machine, controlling the actions of a power switch, an isolation unit and a reset unit according to the configuration information of the register module in the power-on and power-off process of a power supply, completing the power-off operation according to the correct sequence, and enabling the kernel or the Cluster to enter a power-off mode;
2) And (3) electrifying:
writing the power-on configuration information into a register module through an APB interface, controlling a power consumption state machine through an internal signal by the register module, initiating power consumption state conversion, initiating a power consumption state conversion request and controlling the start of a power supply control state machine through a P-Channel interface by the power consumption state conversion state machine, and controlling a kernel or a Cluster power domain to carry out power-on operation by the power supply control state machine; in the power supply electrifying process, the actions of the power switch, the isolation unit and the reset unit are controlled according to the configuration information of the register module, the electrifying operation is completed according to the correct sequence, and the kernel or the Cluster enters a normal working mode.
CN202211001986.5A 2022-08-20 2022-08-20 Power consumption management circuit and method for multi-core processor Pending CN115392161A (en)

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Application Number Priority Date Filing Date Title
CN202211001986.5A CN115392161A (en) 2022-08-20 2022-08-20 Power consumption management circuit and method for multi-core processor

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