CN117878025B - Method for automatically clamping and controlling defective chips on wafer map - Google Patents
Method for automatically clamping and controlling defective chips on wafer map Download PDFInfo
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- CN117878025B CN117878025B CN202410268468.2A CN202410268468A CN117878025B CN 117878025 B CN117878025 B CN 117878025B CN 202410268468 A CN202410268468 A CN 202410268468A CN 117878025 B CN117878025 B CN 117878025B
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- 238000010586 diagram Methods 0.000 description 7
- 238000001514 detection method Methods 0.000 description 6
- 238000007689 inspection Methods 0.000 description 4
- 238000001228 spectrum Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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- 239000002184 metal Substances 0.000 description 1
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Abstract
The invention discloses a method for automatically clamping and controlling a defective chip on a wafer map, which comprises the steps of arranging a defect judging system and a map circulation system in wafer re-judging equipment; the defect judging system identifies the positions of defective chips in the wafer map to be tested, if the positions of the defective chips are in the defect categories, the defect categories are locked, the defect categories are marked as key defect categories, and an operator cannot modify the key defect categories into non-defect chip categories; transmitting the wafer graph to be tested containing the key defect types to a graph circulation system, and performing external expansion card control on the key defect types. The invention can effectively avoid erroneous judgment when the defective chip is manually re-judged, and can also ensure that the defective chip is fully re-judged in place.
Description
Technical Field
The invention relates to the technical field of semiconductor detection, in particular to a method for automatically clamping and controlling a defective chip on a wafer map.
Background
A Wafer (Wafer) is a circular piece of silicon on which a number of individual circuits are built, a single individual circuit being called a Die (Die). After the wafer is subjected to the bump process, 100% of the surface of the wafer needs to be inspected by using automatic surface defect inspection equipment, after the inspection is finished, repeated judgment is needed manually according to defect judgment standards, the good judgment is considered to be a qualified chip, the corresponding code is 00, the defective judgment is considered to be a failed chip, and the corresponding code is 01-99 (16 scale).
Principle of existing equipment inspection: the first step is gray scale contrast, pixels with large gray scale differences are marked by software, and the second step is to count whether the bad pixels exceed the set acceptable size and area, and the two are accepted by the device as defect reject. The limitation of machine judgment is that when the gray level difference between the defective pixel gray level and the golden image pixel is not large, or the defect size is smaller than the detection capability of the machine, the machine cannot detect the defect, and at this time, a rule is required to be specified to automatically ink. Due to the limitation of the device inspection principle, the problem of insufficient detection exists for some defects, or the detected defects are artificially re-judged to be qualified chips, so that the chips with problems can flow to a client side, and the quality problem is caused.
Therefore, it is desirable to provide a method for automatically clamping defective chips on a wafer map.
Disclosure of Invention
In order to solve the problems, the invention provides a method for automatically clamping and controlling the defective chips on the wafer map, which can effectively avoid erroneous judgment when the defective chips are manually re-judged, and can ensure that the defective chips are all re-judged in place; the maximum possible guarantee period of the accuracy of chip detection is greatly improved, and the cost is saved.
The invention discloses a method for automatically clamping and controlling a defective chip on a wafer map, which comprises the following steps:
s1, acquiring a map of a wafer to be detected, wherein the map records a surface image of the wafer to be detected, and the surface image comprises a defect chip; transmitting the map to wafer re-judging equipment;
s2, setting a defect judging system and a map circulation system in the wafer re-judging equipment;
When the defect judging system establishes a scanning program, a plurality of special attention areas are set, and each special attention area corresponds to a defect type; the special attention area comprises a position where a defective chip is easy to appear, and the defect type records the reason of the defective chip;
the defect judging system identifies the positions of defect chips in the wafer map to be detected, if the positions of the defect chips are in the defect categories, the defect categories are locked, the defect categories are marked as key defect categories, and an operator cannot modify the key defect categories into non-defect chip categories;
Transmitting the wafer graph to be tested containing the key defect types to a graph circulation system, and performing external expansion card control on the key defect types, wherein the specific external expansion card control rules are as follows:
Rule a, marking defect categories surrounded by the key defect categories on the first layer;
Or alternatively
A rule b, setting a special marking program in the map circulation system, wherein a plurality of special patterns are preset in the special marking program; if the critical defect categories form a special pattern, the chips surrounded by the chips in the first layer are marked.
In some embodiments, the rule a,
If the key defect category corresponds to an independent chip, marking the chips surrounded on the periphery of the chip by the first layer; or alternatively
If the key defect category corresponds to two adjacent chips, the two chips are regarded as a whole, and the chips surrounded on the periphery of the two chips in the first layer are marked; or alternatively
If qualified chips exist among the chips corresponding to the key defect categories, the chips surrounded on the periphery of each chip in the first layer are marked respectively.
In some embodiments, in rule b, the special graphic comprises: the critical defect types form continuous defects distributed in a strip shape, continuous defects distributed in an inclined direction, continuous defects distributed in a ring shape or continuous defects distributed in an interval qualified chip.
Compared with the prior art, the invention has the beneficial effects that:
The surrounding chips of the chip with key defects can have certain failure risks and need to be selected to ensure the quality of the produced chip; according to the invention, chips possibly at risk are clamped and controlled from the wafer map through the external expansion clamping control rule, and the chips around the chips with critical defects and failure are judged to be bad; ensuring that the chip produced is 100% good.
The invention realizes automatic clamping control of the defective chips on the wafer map, can effectively avoid erroneous judgment when the defective chips are manually re-judged, and can also ensure that the defective chips are fully re-judged in place; the maximum possible guarantee period of the accuracy of chip detection is greatly improved, and the cost is saved.
Drawings
FIG. 1 is a schematic diagram of the single defective chip before and after automatic clamping control;
FIG. 2 is a schematic diagram of the two adjacent defective chips before and after automatic clamping control;
FIG. 3 is a schematic diagram of the present invention before and after automatic clamping of a defective chip;
FIG. 4 is a schematic diagram of the continuous defective chips distributed in a stripe pattern before and after automatic clamping;
FIG. 5 is a schematic diagram of the continuous defective chips distributed obliquely before and after automatic clamping control in the present invention;
FIG. 6 is a schematic diagram of the continuous defect chip distributed in a ring shape before and after automatic clamping control;
FIG. 7 is a schematic diagram of the continuous defective chips distributed among the pass chips before and after automatic clamping.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments.
Example 1
The embodiment discloses a method for automatically clamping and controlling a defective chip on a wafer map, which comprises the following steps:
S1, acquiring a wafer map to be detected, wherein the map records a surface image of the wafer to be detected, and the surface image comprises a defect chip; transmitting the map to wafer re-judging equipment;
s2, setting a defect judging system and a map circulation system in the wafer re-judging equipment;
When a scanning program is established, the defect judging system sets a plurality of special attention areas, and each special attention area corresponds to a defect category; the special attention area includes the position of the defect chip, and the defect category records the reason of the defect chip.
Certain defects can easily occur in certain specific positions of the chip according to daily production experience, and the defects in certain specific positions on the chip can necessarily affect the quality of products, and the specific positions are defined as special attention areas.
The defect class describes the cause of defective chips that occur in different special areas of interest, such as a chip with a defect of "metal residue" and a chip with a defect of "bump defect".
The defect judging system identifies the positions of defective chips in the wafer map to be tested, locks the defect categories if the positions of the defective chips are in the defect categories, marks the defect categories as key defect categories, and operators cannot modify the key defect categories into non-defective chip categories.
In this embodiment, on the one hand, the defect judgment system is used to avoid artificial misjudgment for the defective chip at the source.
On the other hand, the automatic clamping control of the defective chip is realized through the map circulation system.
Transmitting the wafer graph to be tested containing the key defect types to a graph circulation system, and performing external expansion card control on the key defect types, wherein the specific external expansion card control rules are as follows:
Rule a, marking defect categories surrounded by the key defect categories on the first layer;
Or alternatively
A rule b, setting a special marking program in the map circulation system, and presetting a plurality of special patterns in the special marking program; if the critical defect categories form a special pattern, the chips surrounded by the chips in the first layer are marked.
When the rule a is implemented, if the key defect type corresponds to an independent chip, marking the chips surrounded on the periphery of the chip by the first layer; the original map and the map after automatic clamping control are shown in fig. 1, wherein 02 at the red bottom in fig. 1 is a single defective chip, and 02 at the yellow bottom is an outward-expansion defective chip after clamping control.
Or if the key defect category corresponds to two adjacent chips, the two chips are regarded as a whole, and the chips surrounded on the periphery of the two chips in the first layer are marked; the original map and the map after automatic clamping control are shown in fig. 2, wherein 02 at the red bottom in fig. 2 is a single defective chip, and 02 at the yellow bottom is an outward-expansion defective chip after clamping control.
Or if qualified chips exist among the chips corresponding to the key defect categories, respectively marking the chips surrounded by the first layer and the periphery of each chip. The original map and the map after automatic clamping control are shown in fig. 3, wherein 02 at the red bottom in fig. 3 is a single defective chip, and 02 at the yellow bottom is an outward-expansion defective chip after clamping control.
When the rule b is implemented, a plurality of special patterns are preset in the special marking program; if the critical defect categories form a special pattern, the chips surrounded by the chips in the first layer are marked. The special graphic may be a graphic including: the critical defect types form continuous defects distributed in a strip shape, continuous defects distributed in an inclined direction, continuous defects distributed in a ring shape or continuous defects distributed in an interval qualified chip.
The key defect types form continuous defects distributed in a strip shape, an original map and an automatically clamped map are shown in fig. 4, wherein 01 at the red bottom in fig. 4 is a single defect chip, and 01 at the yellow bottom is an outward-expanded defect chip after clamping.
The key defect types form continuous defects distributed obliquely, an original map and an automatically clamped map are shown in fig. 5, 01 at the red bottom in fig. 5 is a single defect chip, and 01 at the yellow bottom is an outward-expanded defect chip after clamping.
The key defect types form continuous defects distributed in a ring shape, an original map and an automatically clamped map are shown in fig. 6, wherein 01 at the red bottom in fig. 6 is a single defect chip, and 01 at the yellow bottom is an outward-expanded defect chip after clamping.
The key defect types form continuous defects distributed by spacing qualified chips, an original map and an automatically clamped map are shown in fig. 7, wherein 01 at the bottom of red in fig. 7 is a single defect chip, and 01 at the bottom of yellow is an outward-expanded defect chip after clamping.
In fig. 4-7, the left is the original spectrum and the right is the automatically clamped spectrum.
The invention realizes automatic clamping control of the defective chips on the wafer map, can effectively avoid erroneous judgment when the defective chips are manually re-judged, and can also ensure that the defective chips are fully re-judged in place; the maximum possible guarantee period of the accuracy of chip detection is greatly improved, and the cost is saved.
While only certain embodiments of the present invention have been described, it will be apparent to those skilled in the art that other modifications and improvements can be made without departing from the inventive concept of the present invention.
Claims (1)
1. A method for automatically clamping and controlling a defective chip on a wafer map, comprising the following steps:
s1, acquiring a map of a wafer to be detected, wherein the map records a surface image of the wafer to be detected, and the surface image comprises a defect chip; transmitting the map to wafer re-judging equipment;
s2, setting a defect judging system and a map circulation system in the wafer re-judging equipment;
When the defect judging system establishes a scanning program, a plurality of special attention areas are set, and each special attention area corresponds to a defect type; the special attention area comprises a position where a defective chip is easy to occur, and the defect category records the reason of the defective chip;
the defect judging system identifies the positions of defect chips in the wafer map to be detected, if the positions of the defect chips are in the defect categories, the defect categories are locked, the defect categories are marked as key defect categories, and an operator cannot modify the key defect categories into non-defect chip categories; the defect judging system is used for avoiding artificial misjudgment aiming at a defective chip at the source;
transmitting a wafer graph to be tested containing key defect types to a graph circulation system, performing external expansion card control on the key defect types, clamping and controlling chips possibly at risk from the wafer graph through an external expansion card control rule, and judging all surrounding chips with key defect failure as bad; ensuring that the produced chip is 100% good;
The specific external expansion card control rule is as follows:
Rule a, marking defect categories surrounded by the key defect categories on the first layer;
If the key defect category corresponds to an independent chip, marking the chips surrounded on the periphery of the chip by the first layer; or alternatively
If the key defect category corresponds to two adjacent chips, the two chips are regarded as a whole, and the chips surrounded on the periphery of the two chips in the first layer are marked; or alternatively
If qualified chips exist among the chips corresponding to the key defect categories, marking the chips surrounded on the periphery of each chip in the first layer respectively;
Or alternatively
A rule b, setting a special marking program in the map circulation system, wherein a plurality of special patterns are preset in the special marking program; if the key defect types form a certain special pattern, respectively marking the chips surrounded by the first layer on the periphery of each chip;
The special patterns include: the critical defect types form continuous defects distributed in a strip shape, continuous defects distributed in an inclined direction, continuous defects distributed in a ring shape or continuous defects distributed in an interval qualified chip.
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