JP2009071230A - System and method for analyzing defect distribution, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a defect distribution analyzing system capable of identifying cause of the occurrence of defect in a short time, and further reducing burden of workers. <P>SOLUTION: The defect distribution analyzing system 10 includes: a memory 16 into which a defect map showing distribution of defects which may be caused to a wafer by contacting to a specified portion of the process unit is stored by matching with identification information of the process unit, for each of a plurality of process units; an inspection data acquiring portion 12 which acquires the defect map, showing distribution of defects caused to the wafer, from an inspecting apparatus 21; and a control portion 11 which determines whether the defect distribution in the defect map acquired at the inspection data acquiring portion 12 matches with the defect distribution in either of the defect maps stored in the memory 16 or not, and then, when the defect distribution matches, displays the identification information, stored in the memory 16 while matching with the defect map with which the defect distribution matches, on a display portion 15. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a system for analyzing a distribution of defects generated on a wafer.

  The semiconductor process includes a plurality of processes such as oxide film formation, etching, cleaning, and sputtering, and a dedicated process processing apparatus (etching apparatus, cleaning apparatus, sputtering apparatus, etc.) is used in each process. In a process processing apparatus, a wafer transfer system or a pin chuck of a stage for fixing the wafer may come into contact with the wafer, so that a defect may occur on the front surface or the back surface of the wafer. When a defect occurs in a wafer that has undergone the process, it is necessary to analyze the distribution of the defect and identify the cause of the defect. For example, when a defect due to the contact of the transfer system occurs on the front surface or the back surface of the wafer, it is investigated in which process processing apparatus the transfer system has the defect. Specifically, the size, position, pattern, and the like of the defect are analyzed, and the transport system that caused the defect is specified from the relationship between the analysis result and the contact area with the wafer in each transport system.

There has been proposed a defect reference system capable of efficiently specifying the cause of a wafer defect (see Patent Document 1). In this defect reference system, information on a wafer and information on a process processing apparatus through which the wafer has passed are acquired from a MES (manufacturing execution system), and a defect inspection result (such as defect information indicating the feature of the defect) of the wafer is obtained by SSA ( It is acquired from inspection tools such as spatial feature analysis, and the acquired information is registered and managed in a database. Defect information is stored by category. A category is a classification item for qualitatively characterizing defects. For example, when there are some characteristic patterns in the defect map, a category is set for each characteristic pattern.
JP 2001-68518 A

  When identifying the cause of the defect, the operator usually analyzes the distribution of defects and characteristics (defect distribution analysis) from the inspection results, and compares the analysis results with the contact area of the wafer in each process device. Based on the relationship, the process apparatus causing the defect is determined. In this determination processing, necessary information is acquired manually from a vast amount of information, and the worker himself specifies the process apparatus using the acquired information. As described above, information is collected manually and the determination by the worker is performed. Therefore, it takes time to identify the cause of the occurrence, and the burden on the worker is large.

  In the defect reference system described in Patent Document 1, the cause of occurrence can be specified based on the category to which the defect map belongs. For example, when the defect map belongs to the donut-shaped pattern category, it can be determined that the defect is caused by the clamp ring. However, also in this case, it is necessary for the operator himself to determine which category the defect map belongs to.

  An object of the present invention is to provide a defect distribution analysis system and method capable of solving the above problems, specifying the cause of the defect in a short time, and reducing the burden on the operator. is there.

  In order to achieve the above object, the defect distribution analysis system of the present invention is configured such that the wafer is brought into contact with a specific portion of the process device for each of a display unit and a plurality of process devices that perform a series of processes on the wafer. A defect map indicating the distribution of defects that may occur in the wafer, and a defect map indicating the distribution of defects generated on the wafer from an external inspection apparatus, and a storage unit in which a defect map indicating the distribution of defects that may occur is associated with the identification information of the process apparatus Determining whether the defect distribution in the defect map acquired by the inspection data acquiring unit and the defect map acquired by the inspection data acquiring unit matches the defect distribution in any of the defect maps stored in the storage unit; A control unit that causes the display unit to display identification information stored in the storage unit in association with the defect map in which the defect distribution matches, Characterized in that it has.

  In the defect distribution analysis method of the present invention, the inspection data acquisition unit acquires a defect map indicating the distribution of defects generated on the wafer from an external inspection apparatus, and the control unit performs a series of processes on the wafer. For each of a plurality of process apparatuses to be executed, a memory in which a defect map indicating a distribution of defects that may occur in the wafer due to contact with a specific part of the process apparatus is stored in association with identification information of the process apparatus When the defect distribution matches, the defect distribution in the defect map acquired by the inspection data acquisition unit is determined to match the defect distribution in any of the defect maps stored in the storage unit. In addition, the identification information stored in the storage unit in association with the defect map having the same defect distribution is displayed on the display unit.

  In addition, the program of the present invention provides a process for acquiring a defect map indicating a distribution of defects generated on a wafer from an external inspection apparatus, and a plurality of process apparatuses that execute a series of processes on the wafer. A process of accessing a storage unit in which a defect map indicating a distribution of defects that may occur in the wafer due to contact with a specific part of the process apparatus is associated with identification information of the process apparatus, and the inspection data acquisition The defect distribution in the defect map acquired by the part matches the defect distribution in any of the defect maps stored in the storage unit, and the defect distribution matches when the defect distribution matches. And causing the computer to execute processing for displaying the identification information stored in the storage unit in association with the defect map on the display unit. To.

  According to the present invention, the process device that is the cause of the defect is automatically identified from the defect map acquired from the inspection device, and the identification information of the process device is displayed. In order to specify the device, manual information collection and determination by the worker are basically not required. Thus, by automating the identification of the process device that is the cause of the defect, the cause of the defect can be identified in a short time, and the burden on the operator can be reduced.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a defect distribution analysis system according to an embodiment of the present invention. Referring to FIG. 1, a defect distribution analysis system 10 is a computer system (for example, a server) that operates according to a program, and its main parts are a control unit 11, a process processing history information acquisition unit 12, and an inspection data acquisition unit 13. , An input unit 14, a display unit 15, and a storage unit 16.

  The process processing history information acquisition unit 12 is connected to the MES 20 and acquires process processing history information from the MES 20 in accordance with an instruction from the control unit 11. The acquired process processing history information is supplied from the process processing history information acquisition unit 12 to the control unit 11. The MES 20 is, for example, information on processing apparatuses (etching apparatus, cleaning apparatus, sputtering apparatus, CMP apparatus, etc.) of a plurality of processes such as oxide film formation, etching, cleaning, sputtering, and CMP (Chemical Mechanical Polishing) in a semiconductor process. This is an existing apparatus for managing wafer information. The process processing history information is information (including an apparatus code and chamber information) related to a process processing apparatus that has processed a wafer.

  The inspection data acquisition unit 13 is connected to the inspection device 21 and acquires inspection data from the inspection device 21 in accordance with an instruction from the control unit 11. The acquired inspection data is supplied from the inspection device 21 to the control unit 11. The inspection device 21 is an existing device that performs inspection such as SSA. The inspection data includes a defect map in which the position of the defect on the wafer is developed on a two-dimensional coordinate.

  The input unit 14 includes an input device such as a keyboard and a mouse. The display unit 15 is a display device such as a liquid crystal display or a plasma display.

  The storage unit 16 stores programs and data (including process device-specific defect map registration data 16a) necessary for operating the defect distribution analysis system 10.

  The defect map registration data 16a for each process device indicates, for each of a plurality of process devices that perform a series of processes on the wafer, a distribution of defects that may occur in the wafer due to contact with a specific part of the process device. This is data in which a defect map is registered in association with identification information (device code) of the process device.

  The defect map registered as the defect map registration data 16a for each process device may be created from actual inspection data, or may be created using a CAD (Computer Aided Design) system. In the former case, a defect is generated in the wafer by actually using the process apparatus, and a defect map is created from the inspection data of the wafer. In the latter case, information such as the size of the wafer and the positional relationship between the wafer and the contact area of the process equipment is input to the CAD system, and contact scratches generated on the wafer are created by arithmetic processing, and a defect map is created based on that. To do. In addition to the process device identification information (device code), the name and information of the process device may be stored in the storage unit 16 in association with the defect map.

  Hereinafter, the defect map registered in the defect map registration data 16a for each process device will be specifically described.

  FIG. 2A is a schematic diagram of a normal defect map. In this defect map, a large number of defects are randomly present on the wafer surface, and a defect distribution (pattern) peculiar to the process apparatus does not occur. FIG. 2B is a schematic diagram of a defect map of a scratch by a CMP apparatus, and FIG. 2C is a schematic diagram of a defect map when a defect occurs due to a contact portion in a transport system of a process apparatus. In these defect maps, a defect distribution (pattern) peculiar to the CMP apparatus and the transport system is generated. The defect map data shown in FIGS. 2B and 2C is stored in the storage unit 16 as defect map registration data 16a for each process device.

  The control unit 11 operates according to a program stored in the storage unit 16 and receives input from the input unit 14 to control the operation of each unit and performs processing necessary for defect distribution analysis. In the defect distribution analysis, the control unit 11 checks whether or not the defect map acquired from the inspection apparatus 21 relatively matches or resembles any defect map in the process apparatus-specific defect map registration data 16a. If there is a matching or similar defect map, the control unit 11 causes the display unit 15 to display a device code corresponding to the defect map. The control unit 11 may display information such as a device name on the display unit 15 together with the device code.

  In addition, the control unit 11 determines whether there is a matching or similar defect map based on the process processing history information (including the device code) acquired by the process processing history information acquisition unit 12 from the MES 20. Further, it is possible to perform a process of narrowing down the defect map to be determined in the defect map registration data 16a for each process device. Specifically, the control unit 11 acquires a defect map corresponding to the apparatus code acquired from the MES 20 from the defect map registration data 16a for each process apparatus, and the defect map matches the defect map acquired from the inspection apparatus 21. Alternatively, it is determined whether or not they are similar. As a result, the time required for the determination process can be shortened, and the data processing amount can be greatly reduced.

  Next, the defect distribution analysis process performed in the defect distribution analysis system of this embodiment will be described. FIG. 3 shows a procedure of the defect distribution analysis process.

  First, the inspection data acquisition unit 13 acquires inspection data from the inspection device 21 (step S10). Next, the process process history information acquisition unit 12 acquires process process history information from the MES 20 (step S11).

  Next, the control unit 11 narrows down the defect map to be determined from the defect map registration data 16a for each process device based on the device code included in the process processing history information acquired from the MES 20 (Step S12).

  Next, the control unit 11 determines whether or not the defect map acquired from the inspection apparatus 21 is relatively identical or similar to any of the defect maps to be determined (step S13). In this determination step, the defect distribution is examined for dimensions, position on the wafer surface, angle, and the like, and from these, it is determined whether or not the defect distributions are relatively matched or similar.

  If it is determined in step 13 that there is a matching or similar defect map, the control unit 11 acquires a device code corresponding to the defect map from the defect map registration data 16a for each process device, and displays the device code on the display unit 15. (Step S14).

  If it is determined in step 13 that there is no coincident or similar defect map, the defect distribution analysis process is terminated. At this time, the control unit 11 may cause the display unit 15 to display a message indicating that there is no matching or similar defect map.

  The above-described defect distribution analysis processing is performed after execution of each process in a series of semiconductor processes, for example.

  FIG. 4 shows a series of processes and inspection steps of the semiconductor process. In the example shown in FIG. 4, in a series of processes A to H, wafer inspections A to I are performed before and after each process. In this inspection process, when the defect distribution analysis process is performed when the inspection C is performed, information regarding the process history of the process apparatus in the process B between the inspection B and the inspection C is obtained from the MES 20 as the process process history information. Supplied to system 10. In the defect distribution analysis system 10, the defect map in the defect map registration data for each process device 16a is narrowed down based on the process processing history information supplied from the MES 20. Then, the narrowed-down defect map is compared with the defect map acquired from the inspection apparatus to determine whether there is a match. If no defect is generated on the wafer in the inspection C, the defect distribution analysis process in the inspection C is omitted.

  Next, the defect map matching determination conditions in step S13 will be specifically described.

  FIG. 5A is a schematic diagram illustrating an example of a defect map acquired from the inspection apparatus. In this defect map, two stripe-like defect patterns are generated. The spacing between these streak-like defect patterns is constant. Such a streak-like defect pattern is a pattern peculiar to the transfer system of the process apparatus.

  FIG. 5B is a schematic diagram illustrating an example of a defect map registered as defect map registration data 16a for each process device. This defect map is a defect map peculiar to the transport system of the process apparatus, and has two stripe-like defect patterns arranged at a constant interval.

  FIG. 5C is a schematic diagram illustrating a state in which the defect maps illustrated in FIGS. 5A and 5B are overlaid. The two stripe-like defect patterns in the defect map shown in FIG. 5A coincide with a part of the two stripe-like defect patterns in the defect map shown in FIG. 5B (the ellipse in FIG. 5C). Part surrounded by). In this way, even if the defect patterns do not completely match, if a part of them matches, the defect map acquired from the inspection apparatus 21 is considered to match the defect map to be determined. In addition, even when the defect patterns are relatively identical or similar, it is considered that the defect map acquired from the inspection apparatus 21 matches the defect map to be determined. It should be noted that this defect map match determination condition can be changed as appropriate.

  According to the defect distribution analysis system of the present embodiment described above, the process device that is the cause of the defect is automatically specified based on the defect map acquired from the inspection device, and the identification information (device code) of the process device is specified. Therefore, in order to identify the process device that has caused the defect, manual information collection and determination by the operator are basically unnecessary. Thus, by automating the identification of the process device that is the cause of the defect, the cause of the defect can be identified in a short time, and the burden on the operator can be reduced.

  In addition, since it is possible to quickly cope with the process apparatus that has caused the defect, the manufacturing yield is also improved.

(Other embodiments)
The defect distribution analysis system shown in FIG. 1 may be composed of a plurality of servers. In this case, the nuclear server may distribute various functions such as a defect distribution analysis processing function, a defect map registration management function, and an analysis result display function to a plurality of servers. The defect distribution analysis processing function is a function for performing defect distribution analysis processing in the defect distribution analysis system shown in FIG. The defect map registration management function is a function for registering and managing the defect map registration data 16a for each process device. The analysis result display function is a function for performing various analyzes based on inspection data from the inspection apparatus and displaying the results.

  FIG. 6 shows a configuration of a system in which processing functions related to defect distribution analysis, which is another embodiment of the present invention, are distributed to two servers. This system includes a defect distribution analysis server 30 and a host server 40 connected to the defect distribution analysis server 30 via a network.

  The defect distribution analysis server 30 has the same function as the defect distribution analysis system 10 shown in FIG. 1, and also has a function of communicating with the upper server 40 via a network. The defect distribution analysis server 30 is connected to the inspection device 21 and the MES 20.

  The host server 40 is connected to the inspection apparatus 21 and has a function of performing various data processing based on the inspection data from the inspection apparatus 21 and the determination result from the defect distribution analysis server 30 and displaying the result. The inspection device 21 and the MES 20 have the same functions as those shown in FIG. The inspection device 21 is connected to the MES 20 via an online controller (OC) 22.

  In the system shown in FIG. 6, first, the inspection apparatus 21 transmits inspection data to the defect distribution analysis server 30 and the upper server 40 and reports a process end to the OC 22. When the OC 22 receives the processing end report from the inspection device 21, the OC 22 transmits a process processing history information transmission instruction to the MES 20.

  When receiving the transmission instruction from the OC 22, the MES 20 transmits history information (process processing history information) of processes performed between the previous inspection and the current inspection to the defect distribution analysis server 30.

  The defect distribution analysis server 30 narrows down the defect map based on the process processing history information from the MES 20. Then, the defect distribution analysis server 30 determines whether there is a defect map obtained by narrowing down that matches the defect map included in the inspection data received from the inspection apparatus 21. If the defect maps match, information on the device code and device name (including information on the handler, board, chuck, etc.) corresponding to the defect map is transmitted to the upper server 40 as a determination result.

  The host server 40 displays the determination result received from the defect distribution analysis server 30 on the display unit. In displaying the determination result, the upper server 40 may display the inspection data received from the inspection device 21 and the processed data together. Further, the defect distribution analysis server 30 itself may display the determination result. The display of the determination result in this case may be a display by a WEB server.

  Also in the system configuration of this other embodiment, the same operational effects as the defect distribution analysis system shown in FIG. In addition, since the processing can be shared by a plurality of servers, the processing burden on the computer can be reduced.

  The system of each embodiment described above is an example of the present invention, and the configuration and operation thereof can be changed as appropriate without departing from the spirit of the invention.

  For example, the process processing history information acquisition unit 12 may be deleted in the defect distribution analysis system shown in FIG. However, if the process processing history information acquisition unit 12 is deleted, the amount of data when the defect map consistency confirmation processing is performed increases, so that processing takes time.

  Also, the process of confirming the consistency of the defect distribution in the defect map is based on data indicating the characteristics of the defect distribution, such as the size of the defect distribution, the position on the wafer surface, and the angle (angle based on the direction of the notch, etc.). It is desirable to do.

  Moreover, you may produce a defect map based on the result of SEM review or component analysis. As a result, the process apparatus that is the cause of the defect can be identified with higher accuracy.

  Any of the functions of the system described in each embodiment can be realized by a computer executing a program. The program indicates an execution procedure of each process (for example, the process shown in FIG. 3) performed in the system, and may be provided through a recording medium such as a CD-ROM or a DVD, and is represented by the Internet. It may be provided through a network.

It is a block diagram which shows the structure of the defect distribution analysis system which is one Embodiment of this invention. It is a schematic diagram of a normal defect map. It is a schematic diagram of a scratch defect map by a CMP apparatus. It is a schematic diagram of a defect map when a defect occurs due to a contact site in a transport system of a process apparatus. It is a flowchart which shows one procedure of the defect distribution analysis process performed in the defect distribution analysis system shown in FIG. It is a figure which shows a series of processes and an inspection process of a semiconductor process. It is a schematic diagram which shows an example of the defect map acquired from the inspection apparatus. It is a schematic diagram which shows an example of the defect map registered as defect map registration data classified by process apparatus. It is a schematic diagram which shows the state which accumulated the defect map shown to FIG. 5A and 5B. It is a figure for demonstrating other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Defect distribution analysis system 11 Control part 12 Process processing history information acquisition part 13 Inspection data acquisition part 14 Input part 15 Display part 16 Storage part 16a Defect map registration data according to process apparatus 20 MES
21 Inspection equipment

Claims (4)

A display unit;
For each of a plurality of process apparatuses that perform a series of processes on a wafer, a defect map indicating a distribution of defects that may occur in the wafer due to contact with a specific part of the process apparatus is identification information of the process apparatus. A storage unit stored in association with
An inspection data acquisition unit for acquiring a defect map indicating a distribution of defects generated in the wafer from an external inspection device;
It is determined whether or not the defect distribution in the defect map acquired by the inspection data acquisition unit matches the defect distribution in any of the defect maps stored in the storage unit. And a control unit that causes the display unit to display identification information stored in the storage unit in association with the defect map with the same. A process processing history information acquisition unit that acquires identification information of a process device that has executed a process on the wafer from an external manufacturing execution system that manages the plurality of process devices,
The control unit, based on the identification information acquired by the process processing history information acquisition unit, determines the defect map stored in association with the identification information before determining whether the defect distributions match. 2. The defect distribution analysis system according to claim 1, wherein the defect distribution analysis system according to claim 1, wherein the defect map is acquired from the storage unit and determines whether or not the acquired defect map matches the defect distribution of the defect map acquired by the inspection data acquisition unit. The inspection data acquisition unit acquires a defect map indicating the distribution of defects generated on the wafer from an external inspection device,
The control unit
For each of a plurality of process apparatuses that perform a series of processes on a wafer, a defect map indicating a distribution of defects that may occur in the wafer due to contact with a specific part of the process apparatus is identification information of the process apparatus. And access the storage unit stored in association with
Determining whether the defect distribution in the defect map acquired by the inspection data acquisition unit matches the defect distribution in any of the defect maps stored in the storage unit;
A defect distribution analysis method for displaying identification information stored in the storage unit in association with a defect map with a matching defect distribution on a display unit when the defect distributions match. A process of acquiring a defect map indicating the distribution of defects generated on the wafer from an external inspection device;
For each of a plurality of process apparatuses that perform a series of processes on a wafer, a defect map indicating a distribution of defects that may occur in the wafer due to contact with a specific part of the process apparatus is identification information of the process apparatus. Processing to access the storage unit stored in association with
A process of determining whether or not the defect distribution in the defect map acquired by the inspection data acquisition unit matches the defect distribution in any of the defect maps stored in the storage unit;
A program for causing a computer to execute processing for displaying identification information stored in the storage unit in association with a defect map with a matching defect distribution on a display unit when the defect distributions match.

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