CN117859202A - 用于接合结构的光学阻塞保护元件 - Google Patents
用于接合结构的光学阻塞保护元件 Download PDFInfo
- Publication number
- CN117859202A CN117859202A CN202280057739.9A CN202280057739A CN117859202A CN 117859202 A CN117859202 A CN 117859202A CN 202280057739 A CN202280057739 A CN 202280057739A CN 117859202 A CN117859202 A CN 117859202A
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- China
- Prior art keywords
- blocking
- layer
- bonding
- semiconductor element
- optical
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W42/00—Arrangements for protection of devices
- H10W42/40—Arrangements for protection of devices protecting against tampering, e.g. unauthorised inspection or reverse engineering
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/63—Vias, e.g. via plugs
- H10W70/635—Through-vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W80/00—Direct bonding of chips, wafers or substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W80/00—Direct bonding of chips, wafers or substrates
- H10W80/301—Bonding techniques, e.g. hybrid bonding
- H10W80/312—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W80/00—Direct bonding of chips, wafers or substrates
- H10W80/301—Bonding techniques, e.g. hybrid bonding
- H10W80/327—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W80/00—Direct bonding of chips, wafers or substrates
- H10W80/701—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
- H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
- H10W90/794—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Semiconductor Integrated Circuits (AREA)
- Die Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US202163203332P | 2021-07-16 | 2021-07-16 | |
| US63/203,332 | 2021-07-16 | ||
| PCT/US2022/037211 WO2023288021A1 (en) | 2021-07-16 | 2022-07-14 | Optically obstructive protective element for bonded structures |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117859202A true CN117859202A (zh) | 2024-04-09 |
Family
ID=84890595
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202280057739.9A Pending CN117859202A (zh) | 2021-07-16 | 2022-07-14 | 用于接合结构的光学阻塞保护元件 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US20230019869A1 (https=) |
| EP (1) | EP4371153A4 (https=) |
| JP (1) | JP2024530539A (https=) |
| KR (1) | KR20240036032A (https=) |
| CN (1) | CN117859202A (https=) |
| TW (1) | TW202324665A (https=) |
| WO (1) | WO2023288021A1 (https=) |
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| TWI822659B (zh) | 2016-10-27 | 2023-11-21 | 美商艾德亞半導體科技有限責任公司 | 用於低溫接合的結構和方法 |
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| TWI837879B (zh) | 2016-12-29 | 2024-04-01 | 美商艾德亞半導體接合科技有限公司 | 具有整合式被動構件的接合結構 |
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| US11385278B2 (en) | 2019-05-23 | 2022-07-12 | Invensas Bonding Technologies, Inc. | Security circuitry for bonded structures |
| WO2021022566A1 (zh) * | 2019-08-08 | 2021-02-11 | 深圳市汇顶科技股份有限公司 | 安全芯片、安全芯片的制备方法和电子设备 |
| KR102780357B1 (ko) * | 2020-01-07 | 2025-03-12 | 삼성전자주식회사 | 반도체 장치의 방어 회로 및 이를 포함하는 반도체 장치 |
-
2022
- 2022-07-14 KR KR1020247004776A patent/KR20240036032A/ko active Pending
- 2022-07-14 EP EP22842899.1A patent/EP4371153A4/en active Pending
- 2022-07-14 WO PCT/US2022/037211 patent/WO2023288021A1/en not_active Ceased
- 2022-07-14 CN CN202280057739.9A patent/CN117859202A/zh active Pending
- 2022-07-14 JP JP2024502047A patent/JP2024530539A/ja active Pending
- 2022-07-14 US US17/812,675 patent/US20230019869A1/en active Pending
- 2022-07-15 TW TW111126697A patent/TW202324665A/zh unknown
Also Published As
| Publication number | Publication date |
|---|---|
| JP2024530539A (ja) | 2024-08-22 |
| WO2023288021A1 (en) | 2023-01-19 |
| EP4371153A4 (en) | 2025-05-21 |
| EP4371153A1 (en) | 2024-05-22 |
| KR20240036032A (ko) | 2024-03-19 |
| US20230019869A1 (en) | 2023-01-19 |
| TW202324665A (zh) | 2023-06-16 |
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