CN117854433A

CN117854433A - Display panel and display device

Info

Publication number: CN117854433A
Application number: CN202311862838.7A
Authority: CN
Inventors: 褚胜男; 周洪波; 匡建; 冯敬骁
Original assignee: Xiamen Tianma Display Technology Co Ltd
Current assignee: Xiamen Tianma Display Technology Co Ltd
Priority date: 2023-12-29
Filing date: 2023-12-29
Publication date: 2024-04-09

Abstract

The present disclosure relates to a display panel and a display device in the field of display technology, the display panel comprising: the pixel driving circuit and the light emitting element, the output node of the pixel driving circuit is electrically connected with the first electrode of the light emitting element; the display panel comprises a display area and a front corridor area positioned at one side of the display area; at least part of the pixel driving circuits of the front porch area comprise a potential holding module connected to the output node, the potential holding module being for holding the potential of the output node in the front porch area at a reference potential, which is the potential input to the output node in the display area, during the black insertion phase of the front porch area. Therefore, the potential of the output node in the front corridor area can be kept at the reference potential, so that the potential of the output node in the front corridor area is kept consistent with the potential of the output node in the display area, and the problem that black marks appear in the display area corresponding to the front corridor area due to small reset current in the black inserting stage of the front corridor area is solved.

Description

Display panel and display device

Technical Field

The disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

With the development of display technology, in order to improve the display effect of low-frequency driving, low-temperature poly-oxide (LowTemperature Polycrystalline Oxid, LTPO) technology is gradually applied to electronic devices with display functions, so as to achieve higher and more flexible refresh rates and lower power consumption.

The LTPO technology needs to use a corresponding driving chip to perform driving when performing screen refreshing. Specifically, in the case of screen refresh, the driving chip is required to drive the pixel driving circuit corresponding to the display area so that the light emitting element corresponding to the display area selectively emits light, thereby realizing refresh display. In order to provide a driver chip with sufficient preparation time and rest time, the transmission of a corresponding reset signal to a pixel driving circuit in a power region is generally stopped when the power region in a display region is refreshed to realize a black insertion algorithm.

In the related art, two rows of pixels are generally refreshed at the same time when a screen is refreshed, that is, two corresponding display areas are refreshed at the same time, that is, one display area and a pore area are refreshed at the same time, and because the pore area has a duration of black insertion display, when the pore area is black inserted, a reset signal of the display area corresponding to the pore area is also affected, which can cause problems of low brightness and black marks of the display area corresponding to the pore area.

Disclosure of Invention

In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a display panel and a display device.

In a first aspect, the present disclosure provides a display panel, comprising:

a pixel driving circuit and a light emitting element, an output node of the pixel driving circuit being electrically connected to a first electrode of the light emitting element;

the display panel comprises a display area and a front corridor area positioned at one side of the display area; at least part of the pixel driving circuit of the front porch area comprises a potential holding module connected to the output node, the potential holding module being configured to hold a potential of the output node in the front porch area at a reference potential, which is a potential input to the output node in the display area, in a black insertion stage of the front porch area.

In a second aspect, the present disclosure further provides a display device including the display panel provided in the first aspect.

Compared with the prior art, the technical scheme provided by the disclosure has the following advantages:

in the display panel and the display device provided by the disclosure, the display panel comprises a pixel driving circuit and a light emitting element, and an output node of the pixel driving circuit is electrically connected with a first pole of the light emitting element; the display panel comprises a display area and a front corridor area positioned at one side of the display area; the at least part of pixel driving circuits of the front corridor area comprise a potential maintaining module, the potential maintaining module is arranged to maintain the potential of the output node in the front corridor area at the same reference potential as the potential of the output node in the display area of the display panel in the black inserting stage of the front corridor area, and the potential of the output node in the front corridor area can be maintained at the reference potential, so that the potential of the output node in the front corridor area is consistent with the potential of the output node in the display area, and further the problem that black marks appear in the display area corresponding to the front corridor area due to small reset current in the black inserting stage of the front corridor area is solved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.

In order to more clearly illustrate the embodiments of the present disclosure or the solutions in the prior art, the drawings that are required for the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.

Fig. 1 is a schematic structural diagram of a partial area of a display panel according to the related art;

fig. 2 is a schematic view of a region division structure of a display panel according to an embodiment of the disclosure;

fig. 3 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the disclosure;

fig. 4 is a schematic structural diagram of another pixel driving circuit according to an embodiment of the disclosure;

fig. 5 is a schematic structural diagram of a pixel driving circuit according to another embodiment of the disclosure;

fig. 6 is a schematic structural diagram of a pixel driving circuit according to another embodiment of the disclosure;

fig. 7 is a schematic view of a structure of another display panel according to an embodiment of the disclosure;

Fig. 8 is a schematic view illustrating a structure of a display panel according to still another embodiment of the present disclosure;

FIG. 9 is a timing diagram of a driving signal according to an embodiment of the disclosure;

fig. 10 is a schematic structural diagram of a display device according to an embodiment of the disclosure.

Detailed Description

In order that the above objects, features and advantages of the present disclosure may be more clearly understood, a further description of aspects of the present disclosure will be provided below. It should be noted that, without conflict, the embodiments of the present disclosure and features in the embodiments may be combined with each other.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced otherwise than as described herein; it will be apparent that the embodiments in the specification are only some, but not all, embodiments of the disclosure.

In general, LTPO technology requires driving using a corresponding driving chip when performing screen refresh, and in particular, requires driving a switching transistor in a pixel driving circuit corresponding to a display area by the driving chip when performing screen refresh, so that a light emitting element corresponding to the display area can selectively emit light, thereby realizing refresh display. In order to leave enough preparation time and rest time for the driving chip, the output of a corresponding reset signal to the switch tube in the power region is generally stopped when the power region in each display region is refreshed so as to realize the black insertion algorithm.

In the related art, at least two display areas are generally refreshed at the same time when a screen is refreshed, that is, at least one display area and a pore area are refreshed at the same time, and because the pore area has the black insertion requirement, when the pore area is black inserted, a reset signal of at least one display area corresponding to the pore area is also affected. Therefore, the related art scheme has a problem that when black insertion is performed in the pore region, the brightness of the display region corresponding to the pore region is low, and black marks appear.

To this end, the embodiments of the present disclosure provide a display panel and a display device, in which a pixel driving circuit and a light emitting element are provided in the display panel, an output node of the pixel driving circuit is electrically connected to a first electrode of the light emitting element, and a potential holding module for holding a potential of the output node in a front lane region at a reference potential in a black insertion stage of the front lane region is provided in at least a part of the pixel driving circuit in the front lane region of the display panel, so that the potential of the output node in the front lane region can be kept identical to the potential of the output node in the display region, thereby improving the problem that black marks appear in the display region corresponding to the front lane region due to a small reset current in the black insertion stage of the front lane region.

The display panel in the embodiments of the present disclosure may be applied to various display devices, which may be provided in any possible electronic apparatus. The electronic device may be, for example, a mobile phone, a computer, a tablet computer, a smart watch, a palm computer, or other devices or apparatuses with display functions, which are not limited in the embodiments of the disclosure.

The display panel and the display device provided by the embodiments of the present disclosure are exemplarily described below with reference to the accompanying drawings.

Illustratively, fig. 1 is a schematic structural view of a partial region of a display panel provided in an embodiment of the present disclosure, showing an optional structure within a front porch region; fig. 2 is a schematic view of a region division structure of a display panel according to an embodiment of the present disclosure, which illustrates a division manner of a front corridor area, a display area, and a rear corridor area in the display panel. Referring to fig. 1 and 2, the display panel 10 includes: a pixel driving circuit 20 and a light emitting element 30; wherein the output node N4 of the pixel driving circuit 20 is electrically connected to the first pole of the light emitting element 30. The display panel 10 includes a display area 102 and a front porch area 101 located at one side of the display area 102; optionally, the display panel 10 may further include a rear gallery area 103, the front gallery area 101 and the rear gallery area 103 being located on different sides of the display area 102, respectively. Taking the orientation shown in fig. 2 as an example, the front porch area 101 is located on the upper side of the display area 102 and the rear porch area 103 is located on the lower side of the display area. Wherein the front lane area 101 and the rear lane area 103 are used for black insertion, respectively, and the display area 102 is used for displaying a picture.

Referring to fig. 1 and 2, in the display panel 10, at least part of the pixel driving circuits 20 of the front porch area 101 include a potential holding module 210, and the potential holding module 210 is connected to the output node N4. The potential maintaining module 210 is configured to maintain, in the black inserting stage of the front porch area, the potential of the output node N4 in the front porch area at a reference potential, where the reference potential is the potential of the output node N4 input into the display area 102, so as to keep the potential of the first electrode of the light emitting element 30 consistent, and the corresponding reset current is kept consistent, reduce the voltage drop between the front porch area 101 and the display area 102, thereby reducing the influence of the front porch area 101 on the display area 102, and improve the black marking problem of the display area 102 in the black inserting stage of the front porch area 101.

In the disclosed embodiment, the display panel 10 may be any possible panel or screen having a display function. The display panel 10 may be an organic light emitting display (Organic Electroluminescence Display, OLED) panel, particularly an OLED panel based on LTPO technology, or may be other types of display panels, as the embodiments of the disclosure are not limited in this respect.

In the disclosed embodiment, the light emitting element 30 may be a light emitting diode. Illustratively, the first pole of the light emitting element 30 may be the anode of a light emitting diode.

In the embodiment of the disclosure, the pixel driving circuit 20 is configured to provide a driving signal to the light emitting element 30, so that the light emitting element 30 selectively emits light and controls the brightness of the light emitting element 30 when emitting light, so that the display panel 10 can display a picture to be displayed. The pixel driving circuit 20 may include a plurality of circuit elements therein, such as transistors (switching transistors) and capacitors, and a specific operation principle of the pixel driving circuit 20 will be exemplarily described hereinafter with reference to a specific circuit element structure and operation timing of the pixel driving circuit 20, which is not limited by the embodiments of the present disclosure.

For example, a plurality of light emitting elements 30 and a plurality of pixel driving circuits 20 may be included in the display panel 10, and each pixel driving circuit 20 is configured to drive at least one light emitting element 30. Specifically, if the light emitting elements 30 are arranged in an array, the pixel driving circuit 20 may also be arranged in an array and electrically connected to the light emitting elements 30 in a one-to-one correspondence, based on which the pixel driving circuit 20 may respectively drive the light emitting elements 30 correspondingly connected to selectively emit light according to the target brightness, so that the display panel 10 may display the corresponding picture to be displayed.

In the embodiment of the present disclosure, the front porch area 101 may be understood as at least a portion of a display area of the display panel 10 for black insertion, and the front porch area 101 includes a plurality of light emitting elements 30 therein. In general, when black insertion is performed, that is, in the black insertion stage, none of the plurality of light emitting elements 30 in the front porch area 101 emits light, which corresponds to at least one frame of black screen being inserted into the front porch area 101.

Illustratively, in connection with fig. 2, in the display panel 10, the target display area 104 in the display area 102 may be understood as one display area that is refreshed in synchronization with the front porch area 101, that is, the target display area 104 and the front porch area 101 may be refreshed simultaneously. Alternatively, the control signal for driving the light emitting elements in the target display region 104 corresponds to or is the same as the control signal for driving the light emitting elements in the front porch region 101.

In the embodiment of the present disclosure, the output node N4 of the pixel driving circuit 20 may be understood as a connection point between the pixel driving circuit 20 and the light emitting element 30. Specifically, a corresponding control signal is output through the output node N4 to achieve selectively controlled light emission of the light emitting element 30 connected to the output node N4.

In the embodiment of the present disclosure, the potential holding module 210 may hold the potential of the output node N4 in the front porch area 101 at the reference potential by outputting a dynamically held or statically held potential signal to the output node N4.

In the embodiment of the disclosure, the reference potential may be set according to actual needs. Specifically, the reference potential is a potential inputted to the output node N4 in the display area 102 of the display panel 10.

For example, the pixel driving circuit 20 may be arranged in any possible manner, for example, the pixel driving circuit 20 may be a circuit in the form of a circuit structure such as "7T1C", "7T2C", "8T1C", where "T" represents a transistor, "C" represents a capacitor, "8T" may represent 8 transistors in total in the pixel driving circuit 20, and "1C" may represent 2 capacitors in total in the pixel driving circuit 20.

It should be noted that the display panel may include a plurality of pixel driving circuits 20 and a plurality of light emitting elements 30, and the structure of the partial area of the display panel 10 shown in fig. 1 is only an example, and does not represent that the display panel provided by the embodiments of the present disclosure includes only 4 pixel driving circuits 20 and 4 light emitting elements 30. In general, a plurality, for example, thousands of pixel driving circuits 20 and light emitting elements 30 may be provided in the display panel 10, as long as the display panel 10 can be ensured to display a picture correctly, which is not limited by the embodiments of the present disclosure.

It should be noted that, in view of the technical problems in the related art, the applicant has studied to find that, when the front porch area 101 is black-inserted, the reset signal of the target display area 104 is affected, for example, at the LTPO high refresh rate, in the pixel driving circuit 20 of the front porch area 101, the refresh pulse of the bias transistor has a plurality, and the first electrode (e.g., anode) of the light emitting element 30 is reset only at the first pulse, and the following pulse does not reset the anode, so that the reset current of the anode is small; for example, the reset current is only I, and the reset current requirement of the normal display area is 2I; this results in a small voltage drop in the front porch area 101, and a reset signal that is different from the reset signal of the display area, so that the reset of the target display area 104 that is refreshed in synchronization with the front porch area is lower, that is, the light emission luminance of the light emitting element 30 in the target display area 104 is reduced, and thus the luminance of the target display area 104 is lower or black mark appears.

In the embodiment of the disclosure, by setting the potential of the output node N4 in the front porch area to the reference potential in the black insertion stage of the front porch area, the potential of the output node N4 in the front porch area 101 may be made the same as the potential of the output node N4 in the display area 102, that is, the reset signal of the output node N4 in the front porch area 101 (i.e., the reset signal of the first pole of the light emitting element 30) may be made the same as the reset signal of the output node N4 in the display area 102 (i.e., the reset signal of the first pole of the light emitting element 30); thus, the reset signal of the output node in the target display area 104 in the display area 102 is matched or identical to the reset signal of the output node in the front lane area, so that the potential of the output node in the target display area 104 is also identical to the reset signal of the output node in the display area.

In this way, it is possible to ensure that the potentials of the output nodes in the display area 102 and the front lane area 101 of the display panel 10 are the same, while ensuring that the reset currents of the output nodes in the display area 102 and the front lane area 101 of the display panel 10 are also the same; further, the light-emitting brightness of each region in the display region can be made the same, so that the problem that black marks appear in the display region corresponding to the front corridor region due to small reset current in the black insertion stage of the front corridor region can be solved.

In some implementations, fig. 3 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the disclosure. On the basis of fig. 1, referring to fig. 3, in the pixel driving circuit 20, the potential holding block 210 includes a first transistor T1 and a second transistor T2; the first transistor T1 and the second transistor T2 may be P-channel type switching transistors, or N-communication type switching transistors; and the two channels may be the same or different, and are not limited herein.

With continued reference to fig. 3, the display panel 10 also includes a reference power signal line REF. The reference power supply signal line REF may be configured to supply a reference potential to one pole of the first transistor T1 and one pole of the second transistor T2.

The first transistor T1 and the second transistor T2 are connected in parallel between the reference power signal line REF and the output node N4, and in the black insertion stage of the front porch area 101, the first transistor T1 and the second transistor T2 are alternately turned on to alternately transmit the potential on the reference power signal line REF to the output node N4.

In the embodiment of the present disclosure, in the case where the first transistor T1 and/or the second transistor T2 are controlled to be turned on, the reference power supply signal line REF may transmit the reference potential to the output node N4 through the turned-on first transistor T1 and/or second transistor T2, thereby achieving the first-pole reset of the light emitting element 30.

In the embodiment of the present disclosure, in the black insertion stage of the front porch area 101, the first transistor T1 or the second transistor T2 may be controlled to be turned on by any possible manner, for example, a corresponding pulse control signal, such as a low level pulse signal or a high level pulse signal, may be output to the first transistor T1 or the second transistor T2 to control the on or off thereof, which is not limited by the embodiment of the present disclosure.

Illustratively, with continued reference to fig. 3, the first pole P11 of the first transistor T1 and the first pole P21 of the second transistor T2 are respectively connected to the reference power supply signal line REF, and the second pole P12 of the first transistor T1 and the second pole P22 of the second transistor T2 are both connected to the output node N4. In other embodiments, the second pole P12 of the first transistor T1 and the second pole P22 of the second transistor T2 may also be connected with other possible components or lines, which the disclosed embodiments are not limited to.

In the embodiment of the disclosure, the first transistor T1 and the second transistor T2 are both connected between the reference power signal line REF and the output node N4, and since the first transistor T1 and the second transistor T2 are respectively connected to the reference power signal line REF, the reference power signal line REF can alternately output a reference potential to the output node N4 through the first transistor T1 and the second transistor T2 when the first transistor T1 and the second transistor T2 are alternately turned on; in combination with the above, the output node N4 is connected to the first electrode of the light emitting element 30, for example, the anode of the organic light emitting diode, whereby the first electrode of the light emitting element 30 can be alternately reset by the first transistor T1 and the second transistor T2 by using the reference potential outputted from the reference power supply signal line REF, thereby enabling the instantaneous reference potential to be held at the first electrode of the light emitting element 30. Specifically, in the black insertion stage of the front porch area 101, the first transistor T1 and the second transistor T2 are alternately turned on, which is equivalent to prolonging the holding time of the reference potential output by the reference power signal line REF at the first pole of the light emitting element 30, so that the potential of the output node N4 can be held at the reference potential to complement the reset current of the output node N4, thereby complementing the reset current of the first pole of the light emitting element 30 and weakening the influence on the display effect of the display area 102.

In the embodiment of the disclosure, the first transistor T1 and the second transistor T2 are alternately turned on, so that the reset signal of the output node N4 in the front porch area 101 is ensured to be the same as the reset signal of the output node N4 in the display area 102, and further the problem that the display area 102 corresponding to the front porch area 101 has black marks due to small reset current in the black insertion stage of the front porch area 101 is solved.

In some embodiments, with continued reference to fig. 3, the display panel 10 further includes a first scan line SV and a second scan line SW. The first scan line SV is connected to the control terminal P13 of the first transistor T1, and the second scan line SW is connected to the control terminal P23 of the second transistor T2. The first scan line SV and the second scan line SW alternately output an enable signal to alternately turn on the corresponding first transistor T1 and second transistor T2.

The first scan line SV is configured to output an enable signal for controlling the first transistor T1 to be turned on to the control terminal P13 of the first transistor T1. The second scan line SW is configured to output an enable signal controlling the second transistor T2 to be turned on to the control terminal P23 of the second transistor T2.

The types of the enable signals (e.g., high and low level settings) output by the first scan line SV and the second scan line SW may be the same or different based on the settings of the first transistor T1 and the second transistor T2. In addition, the first scan line SV may output the enable signal for the same period as the second scan line SW. The embodiments of the present disclosure are not limited in this regard.

In the embodiments of the present disclosure, the enable signal may be understood as a signal for turning on the first transistor T1 and/or the second transistor T2. The enable signal may be a pulse signal, for example, and may be active low or active high, as the example, without limitation.

Illustratively, with continued reference to fig. 3, the control terminal P13 (which may also be referred to as a third electrode P13) of the first transistor T1 is connected to the first scan line SV, and the control terminal P23 (which may also be referred to as a third electrode P23) of the second transistor T2 is connected to the second scan line SW.

When the first scan line SV outputs the enable signal, the first transistor T1 may be turned on, and the reference power signal line REF may output the reference potential to the output node N4 through the first transistor T1. When the second scan line SW outputs the enable signal, the second transistor T2 may be turned on, and the reference power signal line REF may output the reference potential to the output node N4 through the second transistor T2.

Based on this, by controlling the first scan line SV and the second scan line SW to alternately output the enable signal, the first transistor T1 and the second transistor T2 can be accurately and flexibly controlled to alternately turn on, so that the potential of the output node N4 is maintained at the reference potential by the instantaneous reference potential, and further the flexibility and accuracy of resetting the first pole of the light emitting element 30 can be improved.

In some implementations, fig. 4 is a schematic structural diagram of another pixel driving circuit according to an embodiment of the disclosure. On the basis of fig. 1, referring to fig. 4, the pixel driving circuit 20 further includes a bias transistor T3 and a driving transistor T4; the display panel 10 further includes a third scan line SP and a bias signal line DVH.

The bias transistor T3 is electrically connected between the bias signal line DVH and at least one of the first and second poles of the driving transistor T4, and the control terminal P31 of the bias transistor T3 is connected to the third scan signal line SP to be selectively turned on under the control of the third scan signal provided by the third scan line SP, and to provide a bias voltage signal to one pole of the driving transistor T4.

The third scan line SP is configured to output a bias control signal for controlling the bias transistor T3 to be turned on to the control terminal P31 of the bias transistor T3.

The bias transistor T3 is configured to be selectively turned on under control of a bias control signal supplied from the third scan line SP, and transmits a bias voltage signal to the first or second pole of the driving transistor T4. In the disclosed embodiment, the bias voltage signal may be provided by a bias signal line DVH, which may be connected to one pole of the bias transistor T3, the other pole of the bias transistor T3 being connected to the first pole or the second pole of the driving transistor T4, and the bias voltage signal being transmitted to the first pole or the second pole of the driving transistor T4 through the bias transistor T3 in case the bias transistor T3 is controlled to be turned on.

In the embodiment of the disclosure, the bias control signal may be one of the scan signals. Each scan signal may include an enable level and a disable level. For example, an enable level may turn on a transistor and a disable level may turn off a transistor. When the transistor is an N-type semiconductor transistor (NMOS), the enable level is high and the disable level is low. When the transistor is a P-type semiconductor transistor (PMOS), the enable level is low and the disable level is high. In the embodiment of the disclosure, the bias control signal includes an enable level and a disable level, the enable level may turn on the bias transistor T3, and the disable level may turn off the bias transistor T3.

Illustratively, with continued reference to fig. 4, the first pole P31 of the bias transistor T3 may be connected to the third scan line SP, the second pole P32 of the bias transistor T3 may be connected to the bias signal line DVH, the third pole P33 of the bias transistor T3 may be connected to the second pole P42 of the drive transistor T4, the first pole P41 of the drive transistor T4 may be connected to the second pole P12 of the first transistor T1 and the second pole P22 of the second transistor T2, the third pole P43 of the drive transistor T4 may be connected to other lines or components for resetting the third pole P43 (i.e., the gate) of the drive transistor T4, which is not limited in the disclosed embodiments.

For example, the second pole P42 of the driving transistor T4 may be also electrically connected to the power supply line PVDD. Specifically, the second pole P42 of the driving transistor T4 may be directly electrically connected to the power line PVDD, or the second pole P42 of the driving transistor T4 may be indirectly electrically connected to the power line PVDD via a thin film transistor, a capacitor, or the like, which is not limited in the embodiment of the present disclosure.

In some embodiments, when the third scan line SP controls the bias transistor T3 to be turned on, the bias transistor T3 may transmit the bias voltage signal transmitted on the bias voltage power supply signal line to the second pole P42 of the driving transistor T4, so as to reset the second pole P42 of the driving transistor T4, improve the first frame brightness during the picture display, avoid the first frame brightness from being too low, and ensure that the picture display effect consistency is better. Before resetting the third electrode P43 of the driving transistor T4, the bias voltage supplied from the bias voltage power supply signal line can be written into the first electrode of the driving transistor T4 by controlling the bias transistor T3 to be turned on, and the first electrode of the driving transistor T4 is refreshed in potential, so that the device characteristics of the driving transistor T4 are set to a certain initial state, and the influence of the data signal written in the previous frame on the device characteristics of the driving transistor T4 is eliminated. After writing the data voltage into the driving transistor T4, the voltage of the second pole P42 of the driving transistor T4 will generate electric leakage, especially under low frequency driving, the electric leakage is more obvious, resulting in a larger shift of the electric potential of the second pole P42 of the driving transistor T4, at this time, by controlling the bias transistor T3 to be turned on, the bias voltage is written into the second pole P42 of the driving transistor T4 by using the bias transistor T3, the bias state of the driving transistor T4 can be kept consistent with the bias state when the data voltage is just written, so as to improve the stability of the working state of the driving transistor, and improve the low frequency flicker, thereby improving the picture display effect of the display panel 10.

It should be noted that the third scan line SP may further include a plurality of sub-bias signal lines extending in different directions and electrically connected in a cross manner, and may be specifically configured according to actual needs. In general, by arranging a plurality of sub-bias signal lines respectively extending along different directions and electrically connected in a cross manner, the overall size of the third scan line SP is increased, the overall resistance of the third scan line SP is reduced, so that the signal transmission stability of the third scan line SP is improved, the influence of the coupling interference of other signal lines on the third scan line SP is reduced, and the improvement of the picture display quality of the display panel 10 is facilitated.

It should be noted that the bias transistor T3 is connected between the third scan line and at least one of the first and second poles of the driving transistor T4, and fig. 4 only shows one possible connection, that is, the bias transistor T3 may be disposed not in the connection shown in fig. 4 but in the other pole of the driving transistor T4. The principle and effect of the method are similar to those of the scheme, and the embodiment of the disclosure is not repeated here.

In some implementations, fig. 5 is a schematic diagram of a structure of a pixel driving circuit according to another embodiment of the disclosure. Referring to fig. 5, the pixel driving circuit 20 further includes a power supply writing transistor T5, a data writing transistor T6, a first reset transistor T7, a threshold compensation transistor T8, and a light emission control transistor T9; the pixel driving circuit 20 further includes a first capacitor C1; the display panel 10 further includes a first reference power supply signal line REF1.

The threshold compensation transistor T8 is electrically connected between the gate and the first pole of the driving transistor T4, the first pole of the power writing transistor T5 and the first pole of the data writing transistor T6 are both electrically connected to the second pole of the driving transistor T4, the second pole of the power writing transistor T5 is electrically connected to the second pole plate of the first capacitor C1, the gate of the driving transistor T4 and the first pole of the first reset transistor T7 are both electrically connected to the first pole plate of the first capacitor C1, the second pole of the first reset transistor T7 is electrically connected to the first reference power signal line REF1, and the light emission control transistor T9 is connected between the driving transistors and the light emitting element driven by the pixel driving circuit 20.

The data writing transistor T6, the first reset transistor T7, and the light emission control transistor T9 may be P-channel switching transistors, and the power writing transistor T5 and the threshold compensation transistor T8 may be N-channel switching transistors. The power supply writing transistor T5 and the threshold compensation transistor T8 may be P-channel switching transistors, if necessary, and are not limited to this.

Specifically, the first reset transistor T7 and the threshold compensation transistor T8 may be indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) transistors. The data write transistor T6, the power write transistor T5, and the light emission control transistor T9 may be Low Temperature Polysilicon (LTPS) transistors.

In the embodiment of the present disclosure, the first capacitor C1 may be a capacitor for storing a voltage, in particular, a voltage written through the data writing transistor T6 may be stored, and the voltage stored by the first capacitor C1 may be used to characterize the light emitting luminance of the light emitting element 30.

In the disclosed embodiment, the first reference power supply signal line REF1 may be configured to supply a reference potential to one pole of the first reset transistor T7.

In some embodiments, the control terminal (i.e., gate) of the DATA write transistor T6 is also used to connect to the corresponding scan line sc_p, and the second terminal of the DATA write transistor T6 is also used to connect to the corresponding DATA write signal line DATA. The data writing transistor T6 may be turned on by a control signal output from the scan line sc_p to implement writing of data. Also, when the DATA writing transistor T6 is turned on, the DATA writing signal line DATA may output the DATA writing signal VDATA through the DATA writing transistor T6.

The second pole of the power writing transistor T5 and the second pole of the first capacitor C1 may be connected to the power line PVDD, respectively. In the case where the power supply writing transistor T5, the driving transistor T4, and the emission control transistor T9 are turned on, the power supply line PVDD can transmit electric power to the light emitting element 30, thereby realizing light emission of the light emitting element 30

The control terminal (i.e., gate) of the first reset transistor T7 is also used for connecting to the corresponding scan line sc_n1, and the first reset transistor T7 may be turned on or off under the control of the voltage input to the scan line sc_n1. The control terminal (i.e., gate) of the threshold compensation transistor T8 is also used to connect to the corresponding scan line sc_n2, and the threshold compensation transistor T8 may be turned on or off under the control of the voltage input to the scan line sc_n2.

In addition, the control terminal (i.e., gate) of the power supply writing transistor T5 and the control terminal (i.e., gate) of the emission control transistor T9 are also used to connect the emission control scan line EMIT. The power supply writing transistor T5 and the emission control transistor T9 are turned on under the control of the emission control scan signal VEMIT input from the scan line EMIT.

For example, the specific connection relationship of the power writing transistor T5, the data writing transistor T6, the first reset transistor T7, the threshold compensating transistor T8 and the light emission control transistor T9 may be referred to in fig. 5, and will not be described herein.

As can be seen from fig. 5, the pixel driving circuit 20 includes a plurality of connection nodes, for example, the output node N4 is the node N4 in fig. 5, and further includes a first node N1, a second node N2, and a third node N3 in fig. 5. It can be appreciated that the first node N1, the second node N2, the third node N3, and the output node N4 may be virtually existing connection nodes or actually existing connection nodes.

In the embodiment of the present disclosure, the first node N1 may be a connection point of the gate of the driving transistor T4, the first pole of the data writing transistor T6, and the first pole of the first reset transistor T7. The second node N2 may be a connection point of the first pole of the power writing transistor T5 and the second pole of the driving transistor T4. The third node N3 may be a connection point of the driving transistor T4, the threshold compensation transistor T8, and the emission control transistor T9. The embodiments of the present disclosure are not limited in this regard.

Specifically, with the first reset transistor T7 turned on, the first reference power supply signal line REF1 may output power to the first node N1 and the first capacitor C1 through the first reset transistor T7.

In some embodiments, with continued reference to fig. 5, a second capacitor may also be included in the pixel drive circuit 20. The second capacitor is connected between the second pole and the third pole of the data writing transistor T6. In other embodiments, the pixel driving circuit 20 may have other structures known to those skilled in the art, and is not limited herein.

In an embodiment of the disclosure, at least part of the pixel driving circuits of the front corridor area comprise a potential maintaining module to improve the influence of the black inserting stage of the front corridor area on the display area; the pixel driving circuit of the display area can adopt a circuit structure without an upper potential holding module.

Illustratively, fig. 6 is a schematic structural diagram of still another pixel driving circuit according to an embodiment of the disclosure, which shows a pixel driving circuit structure of a display area. Referring to fig. 6, the pixel driving circuit of the display area further includes a second reset transistor T10; the display panel 10 further includes a second reference power supply signal line REF2; a first pole of the second reset transistor T10 is electrically connected to the light emission control transistor T9 and the light emitting element 30, and a second pole of the second reset transistor T10 is connected to the second reference power supply signal line REF2.

The second reset transistor T10 may be a P-channel switch, and the second reset transistor T10 is configured to be turned on under a corresponding control signal to output power to the output node N4.

The second reference power supply signal line REF2 may be configured to supply a reference potential to one pole of the second reset transistor T10.

Specifically, in the case where the second reset transistor T10 is turned on, the second reference power supply signal line REF2 may output power to the output node N4 in the pixel driving circuit of the display area through the second reset transistor T10 to achieve reset of the output node N4, ensuring that the light emitting element of the display area can emit light normally.

Illustratively, with continued reference to fig. 6, a first pole of the second reset transistor T10 is connected to a light emission control transistor in the pixel driving circuit of the display area, a second pole of the second reset transistor T10 is connected to the second reference power supply signal line REF2, and a third pole of the second reset transistor T10 is connected to the corresponding control scan line SPX.

In the embodiment of the present disclosure, the control scan line SPX is configured to output a pulse control signal for controlling the second reset transistor T10 to be turned on or off to the second reset transistor T10.

After the control scan line SPX outputs a pulse control signal to the second reset transistor T10 to control the second reset transistor T10 to be turned on, the light emitting element of the display area can be reset normally. In the related art, the black insertion stage of the front porch area also controls the anode reset of the light emitting element by using the control scanning line SPX, and the reset current outputted from the pixel driving circuit of the front porch area to the light emitting element of the front porch area is generally only half of the light emitting element of the display area, which results in a problem that the brightness of the light emitting element of the target display area corresponding to the front porch area is lowered.

In the embodiment of the disclosure, the second reset transistor T10 is controlled to be turned on by the control scan line SPX, and the first transistor T1 and the second transistor T2 are controlled to be turned on alternately by the first scan line SV and the second scan line SW, so that the reference power supply signal line outputs a voltage to the output node (i.e., the anode of the light emitting element) of the front porch area alternately through the first transistor T1 and the second transistor T2, so as to ensure that the potential of the output node in the front porch area can be kept at the reference potential in the black insertion stage of the front porch area.

In some embodiments, the potential holding module 210 may also be connected to the second reference power supply signal line REF2. Specifically, one pole of the first transistor T1 and one pole of the second transistor T2 in the potential holding block 210 are connected to the second reference power supply signal line REF2, respectively.

It should be noted that, when the first transistor T1 or the second transistor T2 is turned on, the second reference power signal line REF2 may output power to the output node N4 in the pixel driving circuit of the front lane region through the first transistor T1 or the second transistor T2 to reset the output node N4.

Also, since the first transistor T1 and the second transistor T2 are both identical to the second reference power supply signal line REF2, it is possible to ensure that the electric potential output to the output node N4 corresponding to the front porch region is identical when the first transistor T1 and the second transistor T2 are alternately turned on, so that it is ensured that the light emitting elements in the front porch region and the target display region corresponding to the front porch region can normally emit light.

In some embodiments, the front porch region includes a plurality of pixel driving circuits arranged in an array along the first direction and the second direction. Wherein the first direction and the second direction intersect.

Fig. 7 is a schematic view illustrating a structure of another display panel according to an embodiment of the disclosure, and fig. 8 is a schematic view illustrating a structure of yet another display panel according to an embodiment of the disclosure. Referring to fig. 7 or 8, the first direction may be a lateral direction in the drawing, i.e., a left-right direction; the second direction may be a longitudinal direction in the figure, i.e., an up-down direction; the first direction may be perpendicular to the second direction; in other embodiments, the first direction may also form an angle with the second direction, which is not limited by the embodiment of the disclosure, as long as the first direction and the second direction are not parallel.

In the embodiment of the present disclosure, the plurality of pixel driving circuits may be specifically configured as follows:

in the first way, a potential holding module 210 is disposed along the first direction and/or the second direction at intervals of a predetermined number of pixel driving circuits.

In the embodiment of the disclosure, the preset number may be set by a related technician according to actual needs, and the preset number may be any integer greater than or equal to 0.

For example, if the preset number is 1, it represents that a potential holding module 210 may be configured for every other pixel driving circuit along the first direction and/or the second direction, as shown in fig. 7.

In the second way, the pixel driving circuits 20 located in the same row along the first direction and/or in the same column along the second direction are each provided with the potential holding module 210.

That is, when the pixel driving circuits are arranged in the second manner, the pixel driving circuits in the same row in the front lane are each provided with the potential holding module 210 as shown in fig. 8; either the pixel driving circuits located in the same column are each provided with the potential holding module 210, or each pixel driving circuit is provided with the potential holding module 210.

It will be appreciated that, since the front porch area generally includes a plurality of pixel driving circuits and a plurality of light emitting elements, during the black insertion stage of the front porch area, none of the light emitting elements in the front porch area emit light, and if the schemes in the related art are based, each pixel driving circuit in the front porch area does not reset the anode of the corresponding light emitting element, which results in a smaller anode reset current and a lower voltage drop.

Then, the anode reset current of each pixel driving circuit in the display area corresponding to the front lane area (i.e., the target display area) is small, and thus the brightness of each light emitting element in the target display area is low, and even black marks appear in the target display area.

As shown in fig. 7 above, fig. 7 is illustrated taking 9 pixel driving circuits 20 in the front lane as an example, and the pixel driving circuits 20 in the front lane are arranged in such a manner that one potential holding module 210 is arranged at 1 pixel driving circuit 20 intervals in the first direction and the second direction. Fig. 7 is only an example and does not represent that the display panel 10 provided in the embodiment of the present disclosure can be provided only in such a way. The embodiments of the present disclosure are not limited in this regard.

It should be noted that, if the potential holding modules 210 are disposed at intervals along the first direction and/or the second direction for each pixel driving circuit, it is ensured that the pixel driving circuit with the potential holding modules disposed in the front lane region can correctly reset the anode of the light emitting element, so that at least part of the pixel driving circuits in the target display region can provide a reset current that is normal to other display regions in the display region, and the light emitting brightness of at least part of the light emitting elements in the target display region is the same as the light emitting brightness of the light emitting elements in other display regions in the display region. Thus, the problem that black marks appear in the display area corresponding to the front corridor area due to small reset current in the black inserting stage of the front corridor area can be improved to a certain extent, and meanwhile, the effects of reducing cost and simplifying circuit design can be achieved.

If the potential holding module 210 is configured for the pixel driving circuits 20, it is ensured that all the pixel driving circuits in the front porch area can correctly reset the anodes of the light elements, so that all the pixel driving circuits in the target display area can provide a reset current normal to other display areas in the display area, and the light-emitting brightness of all the light-emitting elements in the target display area is the same as the light-emitting brightness of the light-emitting elements in other display areas in the display area. Thus, it is possible to solve the problem that the black mark appears in the display area corresponding to the front porch area due to the small reset current in the black insertion stage of the front porch area.

That is, the related art may flexibly select any one of the above schemes to set each pixel driving circuit in the front porch area according to actual needs, which is not limited by the embodiment of the present disclosure.

In some embodiments, as shown in fig. 5, the second pole of the light emitting element 30, e.g. the cathode of the light emitting diode, may also be connected to a common power supply line PVEE for providing a common power supply signal to the light emitting element 30.

In some implementations, to better illustrate the timing of signals in a display panel provided by the disclosed embodiments, the disclosed embodiments also provide a driving signal timing diagram as shown in fig. 9.

Referring specifically to fig. 9, SPX represents the driving signals of the other display areas among the above-described display areas except for the target display area. In fig. 9 (a), the timing of the driving signal in the related art is shown, and it can be seen that, in one driving period, the other display areas in the display areas continue to generate the reset current for resetting after writing DATA. In the black insertion stage of the front porch area, after writing DATA, the front porch area does not generate a reset current, so that the reset current of the target display area corresponding to the front porch area is smaller than that of other display areas, and the brightness of the light emitting element in the target display area is lower than that of the light emitting element in the other display areas.

In the embodiment of the present disclosure, however, referring to the part (b) of the timing shown in fig. 9, since the potential of the output node of the front porch area can be maintained at the reference potential by the potential maintaining module 210 after writing DATA, that is, the reset current of the front porch area can be complemented, and thus the reset current of the target display area corresponding to the front porch area can be made the same as the reset current of the other display areas. In this way, it is possible to improve the problem that the black mark appears in the display area corresponding to the front porch area due to the small reset current in the black insertion stage of the front porch area.

Further, for the operation of the pixel driving circuit 20, described in detail with reference to fig. 6 and 9, the scan signal vsc_n1 of the scan line sc_n1 controls the on or off of the first reset transistor T7 of the pixel driving circuit 20, and resets the gate potential of the driving transistor T4 when the first reset transistor T7 is turned on, i.e., transmits the reset signal of the first reference power signal line REF1 to the first reset transistor T7 and resets the connection node (first node N1) of the driving transistor T4, the first reset transistor T7, the threshold compensation transistor T8 and the storage capacitor Cst. The scanning signal VDATA of the scanning signal line DATA controls on and off of the DATA writing transistor T6 of the pixel driving circuit 20, and writes the DATA signal on the DATA signal line DL to the gate of the driving transistor T4 at the time of the on of the DATA writing transistor T6. The scan signal vsc_n2 of the scan line sc_n2 controls the on and off of the threshold compensation transistor T8, and compensates the threshold voltage of the driving transistor T4 when the threshold compensation transistor T8 is turned on. Meanwhile, the bias control signal line SP controls on and off of the first reset transistor T7, and resets the anode of the light emitting element 30 connected to the pixel driving circuit 20 when the first reset transistor T7 is turned on, that is, transmits the first reset signal of the first reset signal line VREF1 to the anode of the light emitting element 30. The light emission control scan signal VEMIT of the light emission control scan signal line EMIT controls on and off of the power supply writing transistor T5 and the light emission control transistor T9, and the first power supply signal transmitted by the power supply line PVDD when the control power supply writing transistor T5 and the light emission control transistor T9 are turned on is transmitted to the light emitting element 30, thereby realizing display and light emission of the light emitting element 30. The bias control signal VSP of the bias control signal line SP controls the on or off of the bias transistor T3, and performs bias adjustment on the driving transistor T4 when the bias transistor T3 is turned on, that is, the bias signal of the bias signal line DVH is transmitted to the bias transistor T3, and performs bias adjustment on the connection nodes (the second node N2) of the driving transistor T4, the power supply writing transistor T5, and the data writing transistor T6, so as to ensure the operation stability of the driving transistor T4. In the case where the power supply writing transistor T5, the driving transistor T4, and the light emission control transistor T9 are turned on, the power supply line PVDD may transmit electric power to the light emitting element 30, thereby realizing light emission of the light emitting element 30.

In addition, even in the state of LTPO high refresh rate, the display panel 10 provided in the embodiment of the present disclosure can maintain the potential of the output node in the front porch region at the reference potential by the potential maintaining module 210 of the pixel driving circuit 20 provided in the front porch region when the front porch region enters the black insertion stage.

In practical applications, when the display panel is required to have different refresh frequencies, the duration of the light-emitting holding period in the whole driving period can be appropriately adjusted. When the display panel requires the high frequency driving mode, the duration of the light emission maintaining period can be reduced as much as possible. For example, except for one non-enable level phase of the VEMIT adjacent to the data writing phase, the rest of the period in the light-emitting hold phase may not be set any more and the next data writing phase may be re-entered.

Therefore, the high-precision frequency conversion of the LTPO can be realized, and the problem that black marks appear in the display area corresponding to the front corridor area due to small reset current in the black inserting stage of the front corridor area can be solved.

On the basis of the implementation manners, the embodiment of the disclosure also provides a display device.

Fig. 10 is a schematic structural diagram of a display device according to an embodiment of the disclosure. As shown in fig. 10, the display device X may include any of the display panels 10 provided in the foregoing embodiments, and has corresponding beneficial effects, and is not repeated here for avoiding repeated descriptions.

Exemplary display devices include, but are not limited to, cell phones, tablet computers, vehicle-mounted computers, smart wearable devices with display functions, and other structural components with display functions, which are not described herein nor limited.

It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing is merely a specific embodiment of the disclosure to enable one skilled in the art to understand or practice the disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, comprising:

2. The display panel according to claim 1, wherein the potential holding module includes a first transistor and a second transistor;

the display panel further includes a reference power signal line;

the first transistor and the second transistor are connected in parallel between the reference power supply signal line and the output node, and in the black inserting stage of the front corridor area, the first transistor and the second transistor are alternately conducted to alternately transmit the potential on the reference power supply signal line to the output node.

3. The display panel of claim 2, further comprising a first scan line and a second scan line;

the first scanning line is connected with the control end of the first transistor, and the second scanning line is connected with the control end of the second transistor;

the first scan line and the second scan line alternately output an enable signal.

4. The display panel according to claim 1, wherein the pixel driving circuit further comprises a bias transistor and a driving transistor;

the display panel further includes a third scan line and a bias signal line;

the bias transistor is electrically connected between the bias signal line and at least one of the first and second poles of the drive transistor to be selectively turned on under control of a third scan signal supplied from the third scan line to supply a bias voltage signal to one pole of the drive transistor.

5. The display panel according to claim 4, wherein the pixel driving circuit further comprises a power supply writing transistor, a data writing transistor, a first reset transistor, a threshold compensation transistor, and a light emission control transistor; the pixel driving circuit further comprises a first capacitor;

The display panel further includes a first reference power signal line;

the threshold compensation transistor is electrically connected between the gate and the first pole of the driving transistor, the first pole of the power writing transistor and the first pole of the data writing transistor are electrically connected with the second pole of the driving transistor, the second pole of the power writing transistor is electrically connected with the second pole plate of the first capacitor, the gate of the driving transistor and the first pole of the first resetting transistor are electrically connected with the first pole plate of the first capacitor, the second pole of the first resetting transistor is electrically connected with the first reference power signal line, and the light emitting control transistor is connected between the driving transistor and the light emitting element driven by the pixel driving circuit.

6. The display panel according to claim 5, wherein the pixel driving circuit of the display region further comprises a second reset transistor;

the display panel further includes a second reference power signal line;

the first pole of the second reset transistor is electrically connected with the light-emitting control transistor and the light-emitting element, and the second pole of the second reset transistor is connected with the second reference power supply signal line.

7. The display panel of claim 1, further comprising a second reference power signal line; the potential holding module is connected with the second reference power supply signal line.

8. The display panel of claim 1, wherein the front porch region includes a plurality of pixel driving circuits arranged in an array along a first direction and a second direction, the first direction and the second direction intersecting;

and configuring one potential maintaining module by pixel driving circuits with a preset number along the first direction and/or the second direction, wherein the preset number is an integer greater than or equal to 0.

9. The display panel according to claim 8, wherein the pixel driving circuits located in the same row along the first direction and/or in the same column along the second direction are each provided with the potential holding module.

10. A display device comprising the display panel of any one of claims 1-9.