CN116631321A

CN116631321A - Display panel and driving method thereof

Info

Publication number: CN116631321A
Application number: CN202310631559.3A
Authority: CN
Inventors: 陈楠楠; 鉏文权; 黄学琳
Original assignee: Hefei Visionox Technology Co Ltd
Current assignee: Hefei Visionox Technology Co Ltd
Priority date: 2023-05-30
Filing date: 2023-05-30
Publication date: 2023-08-22

Abstract

The embodiment of the invention discloses a display panel and a driving method thereof. The display panel comprises a plurality of pixel circuits, a plurality of first scanning lines, a plurality of data lines and a plurality of light-emitting control lines, wherein the data lines are used for transmitting data voltages to the pixel circuits row by row in a data writing stage of each row of pixel circuits in a frame period; the pixel circuit is used for responding to the first scanning signal in the corresponding data writing stage and writing the data voltage into the pixel circuit; the light-emitting control signal includes at least one pulse in one frame period; in one frame period, the level transition time of at least one pulse of the light-emitting control signal of the pixel circuit of the m-th row is outside the data writing stage of the pixel circuit of the n-th row, and in one frame period, the data writing stage of the pixel circuit of the n-th row is after the data writing stage of the pixel circuit of the m-th row, and m and n are different positive integers. The technical scheme provided by the embodiment solves the problem that the display panel has flicker when displaying pictures.

Description

Display panel and driving method thereof

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a display panel and a driving method thereof.

Background

With the development of display technology, the requirements of people on the display panel are increasing. The existing display panel has the problem of flickering when displaying pictures, and the display effect of the display panel is affected.

Disclosure of Invention

The embodiment of the invention provides a display panel and a driving method thereof, which are used for solving the problem that the display effect of the display panel is affected due to flicker when the display panel displays pictures.

In order to realize the technical problems, the invention adopts the following technical scheme:

an embodiment of the present invention provides a display panel including:

a plurality of pixel circuits arranged in an array;

a plurality of first scanning lines for transmitting first scanning signals to the pixel circuits of the corresponding rows;

a plurality of data lines for transmitting data voltages to the pixel circuits row by row in a data writing stage of each row of the pixel circuits in one frame period; the pixel circuit is used for responding to the first scanning signal in the corresponding data writing stage and writing the data voltage into the pixel circuit;

a plurality of light emission control lines for transmitting light emission control signals to the pixel circuits of the corresponding rows; in one frame period, the light-emitting control signal comprises at least one pulse, in one frame period, the level transition time of the at least one pulse of the light-emitting control signal of the pixel circuit of the m-th row is outside the data writing stage of the pixel circuit of the n-th row, in one frame period, the data writing stage of the pixel circuit of the n-th row is after the data writing stage of the pixel circuit of the m-th row, and m and n are different positive integers.

Optionally, the light emission control signal includes a first pulse and at least one second pulse after the first pulse within one frame period; the data writing stage of the pixel circuit is positioned in the duration of the extinction level of the first pulse of the light-emitting control signal corresponding to the pixel circuit;

wherein, in a frame period, the level transition time of the second pulse of the light-emitting control signal of the pixel circuit of the m-th row is out of the data writing stage of the pixel circuit of the n-th row.

Optionally, in a frame period, a time when the second pulse of the light-emitting control signal of the mth row of pixel circuits jumps to the off level is outside the data writing stage of the nth row of pixel circuits, and/or a time when the second pulse of the light-emitting control signal of the mth row of pixel circuits jumps to the on level is outside the data writing stage of the nth row of pixel circuits;

optionally, in a frame period, the level transition time of the second pulse of the light-emitting control signal corresponding to at least one row of pixel circuits is outside the data writing phase corresponding to the other rows of pixel circuits;

optionally, in a frame period, the level transition time of the second pulse of the light-emitting control signal corresponding to each row of pixel circuits is outside the data writing phases corresponding to the other rows of pixel circuits.

Optionally, in a frame period, a time when the second pulse of the light-emitting control signal of the pixel circuit of the m-th row jumps to the extinction level is before the data writing stage of the pixel circuit of the n-th row; the timing at which the second pulse of the light emission control signal of the m-th row pixel circuit jumps to the off level is after the data writing stage of the n-1 th row pixel circuit, where n is an integer greater than 2.

Optionally, in a frame period, a time when the second pulse of the light emission control signal of the pixel circuit of the m-th row jumps to the lighting level is before the data writing stage of the pixel circuit of the n+k-th row; the second pulse of the light-emitting control signal of the m-th row pixel circuit jumps to the lighting level at a time point after the data writing stage of the n+k-1-th row pixel circuit, wherein k is an integer greater than or equal to 1

Optionally, in a frame period, a timing at which the second pulse of the light emission control signal of the mth row pixel circuit jumps to the lighting level is after the data writing stage of the nth row pixel circuit; the timing at which the second pulse of the light emission control signal of the m-th row pixel circuit jumps to the lighting level is after the data writing stage of the n+1th row pixel circuit.

Optionally, the display panel further includes:

A plurality of second scanning lines for transmitting second scanning signals to the corresponding pixel circuits in an initialization stage of the pixel circuits of the corresponding row; the second scanning signal is used for controlling the pixel circuit to write the initialization voltage;

in one frame period, the level jump time of the second pulse of the light-emitting control signal of the pixel circuit of the m-th row is outside the initialization phase of the pixel circuit of the n-th row, and the initialization phase of the pixel circuit of the n-th row is after the initialization phase of the pixel circuit of the m-th row;

optionally, the initialization phase of the n+1th row pixel circuit coincides with the data writing phase of the n row pixel circuit;

optionally, the second scan line electrically connected to the n+1th row pixel circuit is electrically connected to the first scan line electrically connected to the n th row pixel circuit, or is the same scan signal line.

Optionally, the pixel circuit includes a driving transistor, a light emitting element, and a data writing module;

the data writing module is connected between the data line and the grid electrode of the driving transistor, the control end of the data writing module is connected with the first scanning line, and the data writing module is used for responding to the first scanning signal to transmit data voltage to the grid electrode of the driving transistor in the data writing stage;

Optionally, the effective level of the first scanning signal is a conduction level for controlling the conduction of the data writing module;

optionally, the data writing module includes a data writing transistor and a threshold compensating transistor, and a gate of the data writing transistor is electrically connected with the first scan line; the data writing transistor is connected between the data line and the first pole of the driving transistor, and the threshold compensating transistor is connected between the grid electrode of the driving transistor and the second pole;

optionally, a gate of the threshold compensation transistor is electrically connected to the first scan line;

optionally, the plurality of data lines and the plurality of light-emitting control lines are arranged in a crossing insulation manner;

optionally, the plurality of data lines extend along a first direction and are arranged along a second direction; the plurality of light-emitting control lines extend along the second direction and are arranged along the first direction; the first direction and the second direction intersect;

the plurality of first scanning lines extend along the second direction and are arranged along the first direction.

Optionally, the display panel further includes:

an initialization line for transmitting an initialization voltage to the pixel circuit;

the pixel circuit further includes:

the initialization module is connected with the grid electrode of the driving transistor and/or the first electrode of the light-emitting element, and the control end of the initialization module is connected with the second scanning line; the initialization module is used for transmitting an initialization voltage to the grid electrode of the driving transistor and/or the first electrode of the light-emitting element in an initialization stage;

Optionally, the active level of the second scan signal on the second scan line is a turn-on level controlling the initialization module to turn on.

Optionally, the pixel circuit further includes: the first light-emitting control module is connected between the first power line and the first pole of the driving transistor, and the second light-emitting control module is connected between the second pole of the driving transistor and the first pole of the light-emitting element, and the second pole of the light-emitting element is connected with the second power line;

the control end of the first light-emitting control module and the control end of the second light-emitting control module are connected with a light-emitting control line, and the first light-emitting control module and the second light-emitting control module are used for responding to a light-emitting control signal to control the light-emitting element to emit light in a light-emitting stage;

optionally, the extinction level is a turn-off level for controlling the first light emitting control module and/or the second light emitting control module to turn off; the lighting level is a conduction level for controlling the conduction of the first light-emitting control module and/or the second light-emitting control module.

According to another aspect of the present invention, there is provided a driving method of a display panel, including:

transmitting data voltages on the data lines to the pixel circuits row by row in a data writing stage of each row of the pixel circuits in a frame period; the pixel circuit responds to a first scanning signal on a corresponding first scanning line in a corresponding data writing stage, and data voltages on the data lines are written into the pixel circuit;

The pixel circuit emits light in response to a lighting level of a light emission control signal on a light emission control line in a light emission period; wherein, in a frame period, the light-emitting control signal on the light-emitting control line comprises at least one pulse; in one frame period, the level transition time of at least one pulse of the light-emitting control signal of the pixel circuit of the m-th row is outside the data writing phase of the pixel circuit of the n-th row, and in one frame period, the data writing phase of the pixel circuit of the n-th row is after the data writing phase of the pixel circuit of the m-th row, and m and n are different positive integers.

Optionally, the light emission control signal on the light emission control line includes a first pulse and at least one second pulse after the first pulse within one frame period; the data writing stage of the pixel circuit is positioned in the duration of the extinction level of the first pulse of the light-emitting control signal corresponding to the pixel circuit; wherein, in a frame period, the level transition time of the second pulse of the light-emitting control signal of the pixel circuit of the m-th row is out of the data writing stage of the pixel circuit of the n-th row.

According to still another aspect of the present invention, there is provided a display device including the display panel set forth in any of the first aspects.

In the display panel provided by the embodiment of the invention, in a frame period, in a data writing stage of each row of pixel circuits, data voltage is transmitted to the pixel circuits row by row, wherein the level jump time of at least one pulse of the luminous control signal of the mth row of pixel circuits is outside the data writing stage of the nth row of pixel circuits, so that the level jump of at least one pulse of the luminous control signal of the mth row of pixel circuits cannot be coupled to the data voltage transmitted by the data line when the data voltage is written into the nth row of pixel circuits, the data voltage of the storage capacitor filled into the nth row of pixel circuits by the data line is the correct data voltage in the frame period, the accuracy of the luminous brightness of the luminous element is ensured, the flickering problem of the display panel is better solved, and the display effect of the display panel is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following description will briefly explain the drawings needed in the description of the embodiments of the present invention, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the contents of the embodiments of the present invention and these drawings without inventive effort for those skilled in the art.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a driving timing of a display panel according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

fig. 4 is a flowchart of a driving method of a display panel according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.

Based on the above technical problems, the present embodiment proposes the following solutions:

fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention. Fig. 2 is a schematic diagram of a driving timing of a display panel according to an embodiment of the invention. Fig. 3 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention. Referring to fig. 1 to 3, a display panel 100 according to an embodiment of the present invention includes a plurality of pixel circuits 10, a plurality of first scan lines s2, a plurality of data lines d, and a plurality of light emission control lines em arranged in an array.

The first scan line S2 is used to transmit the first scan signal S2 to the pixel circuit 10 of the corresponding row; the data line d is used to transfer the data voltage Vdata to the pixel circuit 10 row by row in a data writing stage of each row of the pixel circuit 10 in one frame period (corresponding to one frame period of a picture refresh period, which may be one frame period of a plurality of frame periods or each frame period of a plurality of frame periods). The pixel circuit 10 is configured to write the data voltage Vdata to the pixel circuit 10 in response to the first scan signal S2 in a corresponding data writing phase. The light emission control lines EM are used to transmit light emission control signals EM to the pixel circuits 10 of the corresponding row; the emission control signal EM includes at least one pulse during one frame period; in one frame period, the level transition time of at least one pulse of the light emission control signal of the pixel circuit 10 of the m-th row is out of the data writing stage of the pixel circuit 10 of the n-th row (which may correspond to a period in which the first scan signal S2-n on the first scan line S2 to which the pixel circuit 10 of the n-th row is electrically connected is at an active level). In one frame period, the data writing stage of the nth row pixel circuits 10 follows the data writing stage of the mth row pixel circuits 10, and m and n are different positive integers.

Optionally, the emission control signal EM includes a first pulse and at least one second pulse after the first pulse within one frame period; the data writing stage of the pixel circuit 10 is located in the duration of the off level (or black-inserted level) of the first pulse of the emission control signal EM corresponding to the pixel circuit 10; the level transition time of the second pulse of the light emission control signal of the pixel circuit 10 of the m-th row is outside the data writing stage of the pixel circuit 10 of the n-th row (which may correspond to a period in which the first scan signal S2-n on the first scan line S2 to which the pixel circuit 10 of the n-th row is electrically connected is at an active level).

The first scan line S2 may be electrically connected to the pixel circuits 10 of the corresponding row. The data line d may be electrically connected to the pixel circuits of the corresponding column. The light emission control lines em may be electrically connected to the pixel circuits of the corresponding rows. The plurality of light emission control lines em may be disposed to cross the plurality of data lines d in an insulating manner. The plurality of first scan lines s2 may be disposed to cross the plurality of data lines d with insulation. The light emission control line em may be the same as the extending direction of the first scan line s 2. Optionally, the plurality of data lines d extend along the first direction Y and are arranged along the second direction X; the plurality of light-emitting control lines em extend along the second direction X and are arranged along the first direction Y; the first direction X and the second direction Y intersect; alternatively, the first direction X and the second direction Y are perpendicular. The plurality of first scan lines s2 may extend along the second direction X and be arranged along the first direction Y. With continued reference to fig. 1, the first scan line s2 and the light emission control line em extend in the first direction X, and the data line d extends in the second direction Y.

Specifically, the pixel circuit 10 may include a light emitting element D1, a driving transistor M7, and at least one switching transistor, and a storage capacitor C1. In the initialization stage, the pixel circuit 10 initializes a first electrode (e.g., anode) of the light emitting element D1 and/or a gate of the driving transistor M7 by an initialization voltage transmitted through an initialization line. In the data writing stage, the pixel circuit transfers the data voltage Vdata on the data line d to the gate of the driving transistor according to the first scan signal S2 transferred on the first scan line S2 to charge the storage capacitor C1. In the light emitting stage, the light emitting control signal EM is turned on to transmit the first power signal VDD transmitted by the first power line to the first electrode (e.g., the source) of the driving transistor M7, so that the driving transistor M7 generates a driving current according to the gate-source voltage difference, and drives the light emitting device D1 to emit light. The second power line is connected to the second pole of the light emitting element D1, and is configured to transmit the second power signal VSS to the second pole of the light emitting element D1. One of the first power supply signal VDD and the second power supply signal VSS is a high level signal, and the other is a low level signal. The first power signal VDD may be a high level signal and the second power signal VSS may be a low level signal. The storage capacitor C1 may be connected between the first power line and the gate of the driving transistor M7.

In the data writing stage of each row of the pixel circuits 10, the data voltages are written to the pixel circuits 10 row by row in one frame period, so that the pixel circuits 10 of the display panel 100 are charged row by row from top to bottom in one frame period. In a frame period, the data writing phases corresponding to the pixel circuits of different rows are not overlapped, namely, data voltages are transmitted to the pixel circuits of each row in a line-by-line time sharing mode. The data writing stage may correspond to a period in which the first scan signal S2 is at an active level.

Alternatively, the light emission control signal EM includes a first pulse1 and one or more second pulses pulse2 after the first pulse1 within one frame period. Each pulse may include a time to transition from the on level to the off level, a off level hold period, and a time to transition from the off level to the on level. The light emission control signal EM may include a plurality of extinction levels within one frame period.

In the related art, during the data writing stage of the nth pixel circuit 10, if the second pulse2 of the light emission control signal EM of the nth pixel circuit 10 is level-shifted, the data voltage on the data line electrically connected to the nth pixel circuit 10 is disturbed due to the capacitive coupling between the data line electrically connected to the nth pixel circuit 10 and the light emission control line electrically connected to the nth pixel circuit 10, which may cause the flicker problem of the display panel 100 due to the error of the data voltage written to the nth pixel circuit 10.

In this embodiment, the level transition time of at least one pulse (e.g., the first pulse and/or the second pulse) of the emission control signal EMm on the emission control line em to which the pixel circuit 10 of the m-th row preceding the data writing stage is outside the data writing stage (which may correspond to the period in which the first scan signal S2-n on the first scan line S2 to which the pixel circuit 10 of the n-th row is electrically connected is at the active level) of the pixel circuit 10 of the n-th row following the data writing stage. The level transition timing of at least one pulse (e.g., the first pulse and/or the second pulse) corresponding to the light emission control signal of the pixel circuit of the m-th row does not overlap with the data writing stage of the pixel circuit of the n-th row (corresponding to the period in which the first scanning signal of the pixel circuit of the n-th row is at an active level). When the data voltage is written in the pixel circuits of the nth row (corresponding to a period when the first scanning signal of the pixel circuits of the nth row is at an active level), the level of at least one pulse (for example, the first pulse and/or the second pulse) of the light emission control signal of the pixel circuits of the mth row does not jump. The arrangement is such that the level transition timing of at least one pulse (e.g., the first pulse and/or the second pulse) of the light emission control signal EMm of the pixel circuit 10 of the m-th row preceding the data writing stage is shifted in time from the data writing stage of the pixel circuit of the n-th row (corresponding to the period in which the first scanning signal S2-n on the first scanning line S to which the pixel circuit of the n-th row is electrically connected is at the active level). The arrangement is such that when the data voltage is written into the nth row of pixel circuits 10, the level jump of at least one pulse (e.g. the first pulse and/or the second pulse) of the light emission control signal EM of the nth row of pixel circuits 10 can be avoided, and the data voltage transmitted on the data line d is coupled, so that the data voltage of the storage capacitor of the nth row of pixel circuits 10 charged by the data line d is the correct data voltage within one frame period, the flicker problem of the display panel 100 is better solved, and the display effect of the display panel 100 is improved.

In the display panel 100 provided in this embodiment, in a frame period, in a data writing stage of each row of pixel circuits 10, data voltages are transmitted to the pixel circuits 10 row by row, wherein a level transition time of at least one pulse of the light-emitting control signal EMm of the mth row of pixel circuits 10 is outside the data writing stage of the nth row of pixel circuits 10, so that when the data voltages are written into the nth row of pixel circuits 10, the level transition of at least one pulse of the light-emitting control signal EMm of the mth row of pixel circuits 10 cannot be coupled to the data voltages transmitted by the data line D, so that in a frame period, the data voltages of the storage capacitors in the nth row of pixel circuits 10 are all correct data voltages, the accuracy of the light-emitting brightness of the light-emitting element D1 is ensured, the flicker problem of the display panel 100 is better solved, and the display effect of the display panel 100 is improved.

Optionally, based on the above-described embodiment, referring to fig. 1 to 3, in one frame period, the timing at which the first pulse of the light-emitting control signal EMm of the mth row of pixel circuits 10 transitions to the off level is outside the data writing stage of the nth row of pixel circuits 10 and/or the timing at which the first pulse of the light-emitting control signal EMm of the mth row of pixel circuits 10 transitions to the on level is outside the data writing stage of the nth row of pixel circuits 10.

Optionally, based on the above-described embodiments, referring to fig. 1 to 3, in a frame period, the time when the second pulse of the light-emitting control signal EMm of the mth row of pixel circuits 10 transitions to the off level (e.g., time T1 in fig. 2) is outside the data writing stage of the nth row of pixel circuits 10 (e.g., time T1 in fig. 2), and/or the time when the second pulse of the light-emitting control signal EMm of the mth row of pixel circuits 10 transitions to the on level (e.g., time T2 in fig. 2) is outside the data writing stage of the nth row of pixel circuits 10.

In an alternative embodiment, the timing at which the first pulse and/or the second pulse of the light emission control signal EMm of the mth row of pixel circuits 10 transitions to the off level is outside the data writing phase of the nth row of pixel circuits 10 during one frame period. The timing at which the first pulse and/or the second pulse of the emission control signal EMm corresponding to the mth row pixel circuit 10 transitions to the off level is not within the data writing stage of the nth row pixel circuit 10, but the first pulse and/or the second pulse of the emission control signal EMm corresponding to the mth row pixel circuit 10 does not transition to the off level during the data writing stage of the nth row pixel circuit 10.

Specifically, the timing when the first pulse and/or the second pulse of the light-emitting control signal EMm of the m-th row of pixel circuits 10 in front of the data writing stage is turned off level is staggered from the timing when the data writing stage of the n-th row of pixel circuits 10 in rear of the data writing stage is performed, so that the first pulse and/or the second pulse of the light-emitting control signal EMm of the m-th row of pixel circuits 10 in front of the data writing stage is preferably prevented from being turned off level, and the data writing of the n-th row of pixel circuits 10 in rear of the data writing stage is preferably prevented. By the arrangement, in the data writing stage of the nth row pixel circuits 10, the data lines are charged with the correct data voltages of the storage capacitors of the nth row pixel circuits 10, so that the flicker problem of the display panel 100 is solved well, and the display effect of the display panel 100 is further improved.

In another alternative embodiment, the timing at which the first pulse and/or the second pulse of the emission control signal EMn of the mth row pixel circuit 10 transitions to the on level is outside the data writing stage of the nth row pixel circuit 10 during one frame period. The timing at which the first pulse and/or the second pulse of the light emission control signal EMm corresponding to the mth row pixel circuit 10 transitions to the light-on level is not within the data writing stage of the nth row pixel circuit 10, and the first pulse and/or the second pulse of the light emission control signal EMm corresponding to the mth row pixel circuit 10 does not transition to the light-on level during the data writing stage of the nth row pixel circuit 10.

Specifically, the timing when the first pulse and/or the second pulse of the light emission control signal EMm of the m-th row of pixel circuits 10 preceding the data writing stage is changed to the lighting level is offset from the timing when the data writing stage of the n-th row of pixel circuits 10 following the data writing stage is performed, so that the first pulse and/or the second pulse of the light emission control signal EMm of the m-th row of pixel circuits 10 preceding the data writing stage is preferably prevented from changing to the lighting level, and the data writing of the n-th row of pixel circuits 10 following the data writing stage is preferably prevented. By the arrangement, in the data writing stage of the nth row pixel circuits 10, the data lines are charged with the correct data voltage Vdata of the storage capacitance of the nth row pixel circuits 10, so that the flicker problem of the display panel 100 is solved well, and the display effect of the display panel 100 is further improved.

In yet another alternative embodiment, the timing at which the first pulse and/or the second pulse of the light emission control signal EMm of the mth row of pixel circuits 10 transitions to the off level is outside the data writing phase of the nth row of pixel circuits 10 during one frame period; and the timing at which the first pulse and/or the second pulse of the light emission control signal EMm of the mth row of pixel circuits 10 transitions to the on level is outside the data writing phase of the nth row of pixel circuits 10.

With continued reference to fig. 2 based on the above-described embodiment, optionally, the timing at which the second pulse of the light-emission control signal EMm of the mth row of pixel circuits 10 transitions to the off level precedes the data writing phase of the nth row of pixel circuits 10; the timing at which the second pulse2 corresponding to the emission control signal EMm of the mth row of pixel circuits 10 transitions to the off level is before the start timing of the data writing stage of the nth row of pixel circuits 10 (the start timing that can correspond to the active level of the first scanning signal S2-n on the first scanning line S2 to which the nth row of pixel circuits 10 are electrically connected). The timing at which the second pulse2 of the emission control signal EMm of the mth row of pixel circuits 10 transitions to the off level is after the data writing stage (e.g., the period T2 in fig. 2) of the nth-1 row of pixel circuits 10, and the timing at which the second pulse2 of the emission control signal EMm of the mth row of pixel circuits 10 transitions to the off level is after the end timing of the data writing stage of the nth-1 row of pixel circuits 10 (the end timing that may correspond to the end timing of the active level of the first scan signal S2-n-1 on the first scan line S2 to which the nth row of pixel circuits 10 is electrically connected). Illustratively, m=1.

For example, the emission control signal EM may include one first pulse and 15 second pulses within one frame period. The data writing stage may be set during the duration of the off level of the first pulse of the light emission control signal EM corresponding to each row of the pixel circuits 10, and the data writing may be performed on the row of the pixel circuits 10. The data writing stage is not provided for the duration of the off level of the second pulse of the emission control signal EM corresponding to each row of the pixel circuits 10, and the data writing may not be performed for the row of the pixel circuits 10. With continued reference to fig. 2, the first second pulse of the mth row of pixel circuits 10, i.e., the second pulse of the emission control signal EMm of the mth row of pixel circuits 10.

Optionally, in a frame period, a time when the second pulse of the light emission control signal of the mth row of pixel circuits jumps to the lighting level is before a data writing stage of the n+k row of pixel circuits (corresponding to a period in which the first scanning signal on the first scanning line electrically connected to the n+k row of pixel circuits is at an active level); the timing at which the second pulse of the light emission control signal of the mth row pixel circuit jumps to the light-on level is after the data writing stage of the n+k-1 th row pixel circuit (corresponding to a period in which the first scanning signal on the first scanning line to which the n+k-1 th row pixel circuit is electrically connected is an active level), where k is an integer greater than or equal to 1. Fig. 2 illustrates an exemplary case where k=2. In one frame period, the timing at which the second pulse of the light emission control signal of the mth row pixel circuit jumps to the lighting level is before the data writing stage (corresponding to the T4 period in fig. 2) of the n+2th row pixel circuit; the timing at which the second pulse of the light emission control signal of the m-th row pixel circuit transitions to the light-on level is after the data writing stage (corresponding to the T3 period in fig. 2) of the n+1th row pixel circuit.

With continued reference to fig. 2 on the basis of the above-described embodiment, optionally, the timing at which the second pulse of the light emission control signal EMm of the mth row pixel circuit 10 transitions to the on level is after the data writing stage of the nth row pixel circuit 10 within one frame period; the timing at which the second pulse of the light emission control signal EMm of the m-th row pixel circuit 10 transitions to the on level is after the data writing stage (e.g., T3 period in fig. 2) of the n+1th row pixel circuit 10.

As an example, with continued reference to fig. 2 and 3, taking the switching transistor of the pixel circuit 10 as a P-type transistor as an example, the on level of the emission control signal EMn is a low level signal and the off level of the emission control signal EMn is a high level signal. The first pulse and the second pulse of the emission control signal EMn correspond to the off level of the emission control signal EMn. That is, when the pulse of the emission control signal EMn (including the first pulse and the second pulse) arrives, the light emitting element D1 of the row of pixel circuits 10 does not emit light, and the row of pixel circuits 10 enters the data writing stage according to the arrival of the first scan signal S2-n.

By way of example, with continued reference to fig. 2 and 3, the number of pulses of the emission control signal EMn may be set to 16 in one frame period. In one frame period, the first row of pixel circuits 10 corresponds to the first scan signal S2-1, the second scan signal S1-1, and the light emission control signal EM1. The second row of pixel circuits 10 corresponds to the second scan signal S2-2, the second scan signal S1-2, and the emission control signal EM2. By analogy, the m-th row of pixel circuits 10 corresponds to the first scan signal S2-m, the second scan signal S1-m, and the light emission control signal EMm. The corresponding second scanning signal S2-m+1, the second scanning signal S1-m+1, the light emission control signal EM m+1 of the pixel circuit 10 of the m+1 row, the corresponding first scanning signal S2-n-1, the second scanning signal S1-n-1, the light emission control signal EMn-1 of the pixel circuit 10 of the n-1 row. The corresponding first scan signal S2-n, second scan signal S1-n, and emission control signal EMn of the n-th row of pixel circuits 10. The n+1th row of pixel circuits 10 corresponds to the first scan signal S2-n+1, the second scan signal S1-n+1, and the emission control signal emn+1. The n+2 row of pixel circuits 10 corresponds to the first scan signal S2-n+2, the second scan signal S1-n+2, and the emission control signal emn+2.

Optionally, in a frame period, the level transition time of at least one pulse (for example, the first pulse and/or the second pulse, or all pulses) of the light emission control signals corresponding to at least one row of pixel circuits is outside the data writing phase corresponding to the remaining rows of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits). Illustratively, in one frame period, the level transition time of at least one pulse (e.g., the first pulse and/or the second pulse) of the light emission control signal corresponding to the mth row of pixel circuits is outside the data writing phase corresponding to the remaining row of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits).

Optionally, in a frame period, the level transition time of the second pulse of the light emission control signal corresponding to at least one row of pixel circuits is outside the data writing phase corresponding to the other rows of pixel circuits (or all rows of pixel circuits, including the pixel circuit of the present row). Illustratively, in one frame period, the level transition timing of the second pulse of the light emission control signal corresponding to the mth row of pixel circuits is outside the data writing phase corresponding to the remaining rows of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits).

Optionally, in a frame period, the level transition time of at least one pulse (for example, the first pulse and/or the second pulse, or all pulses) of the light emission control signal corresponding to each row of pixel circuits is outside the data writing phase corresponding to the remaining rows of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits).

Optionally, in a frame period, the level transition time of the second pulse of the light emission control signal corresponding to each row of pixel circuits is outside the data writing phase corresponding to the other rows of pixel circuits (or all rows of pixel circuits, including the pixel circuit of the present row).

Optionally, in a frame period, a time when at least one pulse (for example, the first pulse and/or the second pulse, or all pulses) of the light emission control signal corresponding to at least one row of pixel circuits jumps to the off level is outside of a data writing phase corresponding to the remaining row of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits), and/or a time when at least one pulse (for example, the first pulse and/or the second pulse, or all pulses) of the light emission control signal corresponding to at least one row of pixel circuits jumps to the on level is outside of a data writing phase corresponding to the remaining row of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits).

Optionally, in one frame period, the time when the second pulse of the light-emitting control signal corresponding to the at least one row of pixel circuits jumps to the off level is outside the data writing phase corresponding to the other row of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits), and/or in one frame period, the time when the second pulse of the light-emitting control signal corresponding to the at least one row of pixel circuits jumps to the on level is outside the data writing phase corresponding to the other row of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits).

Optionally, in a frame period, at least one pulse (for example, the first pulse and/or the second pulse, or all pulses) of the light emission control signal corresponding to each row of pixel circuits transitions to the off level at a time point outside the data writing phase corresponding to the remaining rows of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits), and/or in a frame period, at least one pulse (for example, the first pulse and/or the second pulse, or all pulses) of the light emission control signal corresponding to each row of pixel circuits transitions to the light-up level at a time point outside the data writing phase corresponding to the remaining rows of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits).

Optionally, in one frame period, the time when the second pulse of the light-emitting control signal corresponding to each row of pixel circuits jumps to the off level is outside the data writing phase corresponding to the other rows of pixel circuits (or all rows of pixel circuits including the present row of pixel circuits), and/or in one frame period, the time when the second pulse of the light-emitting control signal corresponding to each row of pixel circuits jumps to the on level is outside the data writing phase corresponding to the other rows of pixel circuits (or all rows of pixel circuits including the present row of pixel circuits).

Optionally, on the basis of the foregoing embodiment, with continued reference to fig. 1 to 3, the display panel 100 provided in this embodiment may further include: a plurality of second scan lines S1, the second scan lines S1 being used for transmitting second scan signals S1-n to the corresponding pixel circuits 10 in an initialization stage of the corresponding pixel circuits; the second scan signals S1-n are used to control the pixel circuit 10 to write the initialization voltage. The initialization phase of the nth row pixel circuits 10 is after the initialization phase of the mth row pixel circuits 10 within one frame period.

Alternatively, in one frame period, the level transition timing of at least one pulse of the light emission control signal EMm of the mth row pixel circuit 10 is outside the initialization stage of the nth row pixel circuit 10 (corresponding to a period in which the second scan signal S1-n on the second scan line S1 to which the nth row pixel circuit 10 is electrically connected is at an active level).

Alternatively, in one frame period, the level transition timing of the first pulse of the light emission control signal EMm of the mth row pixel circuit 10 is outside the initialization stage of the nth row pixel circuit 10 (corresponding to the period in which the second scan signal S1-n on the second scan line S1 to which the nth row pixel circuit 10 is electrically connected is at an active level).

Alternatively, in one frame period, the level transition timing of the second pulse of the light emission control signal EMm of the mth row pixel circuit 10 is outside the initialization stage of the nth row pixel circuit 10 (corresponding to the period in which the second scan signal S1-n on the second scan line S1 to which the nth row pixel circuit 10 is electrically connected is at an active level).

Specifically, in the initialization stage of the pixel circuit 10, the initialization module of the pixel circuit 10 responds to the second scan signal S1-n, so that the initialization module is turned on, and the initialization voltage transmitted on the initialization line is transmitted to the first electrode of the light emitting element D1 and/or the gate of the driving transistor through the initialization module. The initialization line may be disposed to cross the light emission control signal line with insulation. Since the first electrode of the light emitting element D1 and/or the gate of the driving transistor are written with the initialization voltage in the initialization phase, the initialization voltage written with the first electrode of the light emitting element D1 and/or the gate of the driving transistor in the initialization phase of the nth row pixel circuit 10 can be made more accurate by setting the level transition timing of the first pulse and/or the second pulse of the light emission control signal EMm of the mth row pixel circuit 10 to be outside the initialization phase of the nth row pixel circuit 10, thereby further improving the display effect of the display panel 100.

Alternatively, the initialization phase of the n+1th row pixel circuit 10 coincides with the data writing phase of the n+1th row pixel circuit 10, and may correspond to a period in which the second scan signal S2-n+1 of the n+1th row pixel circuit 10 is at an active level coincides with a period in which the first scan signal S2-n of the n+1th row pixel circuit 10 is at an active level. Optionally, the first scan line s2 of the n-th row of pixel circuits 10 is electrically connected to the second scan line s1 of the n+1-th row of pixel circuits 10, or is the same scan signal line, so as to reduce the occupied area of the scan driving circuit.

Optionally, in a frame period, the level transition time of at least one pulse (for example, the first pulse and/or the second pulse, or all pulses) of the light emission control signals corresponding to at least one row of pixel circuits is outside the initialization phase corresponding to the remaining rows of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits). Illustratively, in one frame period, the level transition time of at least one pulse (e.g., the first pulse and/or the second pulse, or all pulses) of the light emission control signal corresponding to the mth row of pixel circuits is outside the initialization phase corresponding to the remaining row of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits).

Optionally, in a frame period, the level transition time of the second pulse of the light emission control signal corresponding to at least one row of pixel circuits is outside the initialization phase corresponding to the other rows of pixel circuits (or all rows of pixel circuits, including the pixel circuit of the present row). Illustratively, in one frame period, the level transition time of the second pulse of the light emission control signal corresponding to the mth row of pixel circuits is outside the initialization phase corresponding to the rest of the row of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits).

Optionally, in a frame period, the level transition time of at least one pulse (for example, the first pulse and/or the second pulse, or all pulses) of the light emission control signal corresponding to each row of pixel circuits is outside the initialization phase corresponding to the remaining rows of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits).

Optionally, in a frame period, the level transition time of the second pulse of the light emission control signal corresponding to each row of pixel circuits is outside the initialization phase corresponding to the other rows of pixel circuits (or all rows of pixel circuits, including the pixel circuit of the present row).

Optionally, in one frame period, the time when at least one pulse (for example, the first pulse and/or the second pulse, or all pulses) of the light emission control signal corresponding to at least one row of pixel circuits transitions to the off level is outside of the initialization phase corresponding to the remaining row of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits), and/or the time when at least one pulse (for example, the first pulse and/or the second pulse, or all pulses) of the light emission control signal corresponding to at least one row of pixel circuits transitions to the on level is outside of the initialization phase corresponding to the remaining row of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits).

Optionally, in one frame period, the time when the second pulse of the light-emitting control signal corresponding to the at least one row of pixel circuits jumps to the off level is outside the initialization phase corresponding to the other row of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits), and/or in one frame period, the time when the second pulse of the light-emitting control signal corresponding to the at least one row of pixel circuits jumps to the on level is outside the initialization phase corresponding to the other row of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits).

Optionally, in a frame period, at least one pulse (for example, the first pulse and/or the second pulse, or all pulses) of the light emission control signal corresponding to each row of pixel circuits transitions to the off level at a time outside an initialization phase corresponding to the remaining row of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits), and/or at least one pulse (for example, the first pulse and/or the second pulse, or all pulses) of the light emission control signal corresponding to each row of pixel circuits transitions to the on level at a time outside an initialization phase corresponding to the remaining row of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits).

Optionally, in one frame period, the time when the second pulse of the light-emitting control signal corresponding to each row of pixel circuits jumps to the off level is outside the initialization phase corresponding to the other rows of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits), and/or in one frame period, the time when the second pulse of the light-emitting control signal corresponding to each row of pixel circuits jumps to the on level is outside the initialization phase corresponding to the other rows of pixel circuits (or all rows of pixel circuits, including the present row of pixel circuits).

For example, referring to fig. 1 to 3, the off level of the emission control signal EMn corresponds to the front end of the pulse of the emission control signal EMn, and the off level of the emission control signal EMn is a high level; the active level of the first scan signal S2-n is low; the active level of the second scan signal S1-n is low.

Alternatively, with continued reference to fig. 3 on the basis of the above-described embodiment, the pixel circuit 10 provided in this embodiment includes a driving transistor M7, a light emitting element D1, and a data writing module 1; the data writing module 1 is connected between the data line d and the gate of the driving transistor M7, the control terminal of the data writing module 1 is connected to the first scan line S2, and the data writing module 1 is configured to transmit the data voltage Vdata to the gate of the driving transistor M7 in response to the first scan signal S2 during the data writing stage.

Optionally, the active level of the first scan signal S2 is a turn-on level for controlling the data writing module to turn on. In the data writing stage, the data writing module 1 is turned on in response to the active level of the first scan signal S2, and transmits the data voltage to the gate of the driving transistor M7. The gate of the driving transistor M7 of the pixel circuit 10 is written with the data voltage before the light emitting stage, so that the voltage of the gate of the driving transistor M7 of the pixel circuit 10 is stored in the storage capacitor. This arrangement allows the pixel circuit 10 to maintain the gate voltage of the driving transistor M7 during the light-emitting period, thereby improving the display effect of the display panel 100. Alternatively, the data writing module 1 may include a data writing transistor M2 and a threshold compensating transistor M1. The data writing transistor M2 is connected between the data line and the first pole of the driving transistor M7. The threshold compensation transistor M1 is connected between the gate and the second pole of the driving transistor M7. The gate of the data writing transistor M2 is electrically connected to the first scan line. Optionally, the gate of the threshold compensation transistor M1 is electrically connected to the first scan line. The gate of the data writing transistor M2 and the gate of the threshold compensating transistor M1 may be connected to the same scan line or different scan lines.

Optionally, with continued reference to fig. 3, the display panel 100 provided in this embodiment may further include: an initialization line for transmitting an initialization voltage Vinit to the pixel circuit 10. The pixel circuit 10 may further include: the initialization module 3, the initialization module 3 is connected with the grid electrode of the driving transistor M7 and/or the first electrode of the light-emitting element D1, and the control end of the initialization module 3 is connected with the second scanning line s1; the initialization module 3 is configured to transmit an initialization voltage to the gate of the driving transistor M7 and/or the first electrode of the light emitting element D1 in an initialization phase.

Specifically, the arrangement is such that the pixel circuit 10 transmits the second scan signal S1 to the control terminal of the initialization module 3 through the second scan line S1, and the initialization module 3 is turned on in response to the active level of the second scan signal S1 to transmit the initialization voltage transmitted on the initialization line to the gate of the driving transistor M7 and/or the first electrode (may be, for example, the anode) of the light emitting element D1, and initialize the gate of the driving transistor M7 and/or the first electrode of the light emitting element D1 in the initialization stage. The initial state of each row of pixel circuits 10 is set so as to be as uniform as possible, and the potential of the first electrode of the light emitting element D1 of each pixel circuit 10 is set so as to be as uniform as possible after the initialization phase is completed. The potential of the gate electrode of the driving transistor M7 of each row of pixel circuits 10 is as uniform as possible, so that when each row of pixel circuits 10 enters the light-emitting stage after writing the data voltage, the light-emitting brightness of each pixel circuit 10 is as uniform as possible with the light-emitting brightness to be displayed, and the display effect of the display panel 100 is further improved.

Optionally, the initialization module 3 may include a first initialization transistor M5 and/or a second initialization transistor M4. The first initialization transistor M5 is connected between the initialization line and the gate of the driving transistor M7, and the first initialization transistor M5 is used for initializing the gate of the driving transistor M7 in the initialization stage. The second initialization transistor M4 is connected between the initialization line and the first pole of the light emitting element. The second initializing transistor M4 is used for initializing the first electrode of the light emitting element D1 in the initializing stage. Optionally, the active level of the second scan signal S1 is a turn-on level for controlling the initialization module 3 to turn on. The gate of the first initialization transistor M5 is electrically connected to the second scan line. Optionally, the gate of the second initialization transistor M4 is electrically connected to the second scan line. The gate of the first initialization transistor M5 and the gate of the second initialization transistor M4 may be connected to the same scan line or different scan lines.

Optionally, with continued reference to fig. 3, the pixel circuit 10 provided in this embodiment may further include: at least one light-emitting control module. At least one light emission control module comprises a first light emission control module 21 and/or a second light emission control module 22, the first light emission control module 21 is connected between a first power line and a first pole of the driving transistor M7, the second light emission control module 22 is connected between a second pole (e.g. drain) of the driving transistor M7 and a first pole (e.g. anode) of the light emitting element D1, and a second pole (e.g. cathode) of the light emitting element D1 is connected with the second power line; the control end of the first light-emitting control module 21 and the control end of the second light-emitting control module 22 are connected with a light-emitting control line EM, and the first light-emitting control module 21 and the second light-emitting control module 22 are used for responding to the light-emitting control signal EM to control the light-emitting element D1 to emit light in a light-emitting stage. The first light emitting control module 21 may include a first light emitting control transistor M3. The second light emitting control module 22 may include a second light emitting control transistor M6.

Specifically, since the gate potential of the driving transistor M7 is maintained by the electric energy stored in the storage capacitor in the light emitting stage, the driving current generated by the driving transistor M7 in the light emitting stage is stabilized. The control terminal of the first light emitting control module 21 and/or the second light emitting control module 22 is turned on in response to the lighting level of the light emitting control signal EM, so as to transmit the first power signal VDD transmitted by the first power line to the first electrode (for example, may be a source) of the driving transistor M7, and thus the driving transistor M7 generates a driving current according to the gate-source voltage difference thereof, and drives the light emitting element D1 to emit light.

Optionally, the extinction level is a turn-off level for controlling the first light emitting control module and/or the second light emitting control module to turn off; the lighting level is a conduction level for controlling the conduction of the first light-emitting control module and/or the second light-emitting control module. One of the off level and the on level may be a high level, and the other may be a low level.

Optionally, in a frame period, the initialization phase of the same pixel circuit may precede the data writing phase; the light-emitting phase of the same pixel circuit may be subsequent to the data-writing phase.

Optionally, the data driving circuit is electrically connected to the pixel circuit via a data line. Optionally, the scan driving circuit is electrically connected to the pixel circuit via the first scan line and/or the second scan line. Optionally, the light-emitting driving circuit is electrically connected to the pixel circuit via a light-emitting control line. Optionally, the timing controller is electrically connected with the data driving circuit, the scan driving circuit, and the light-emitting driving circuit. Alternatively, the timing controller and the data driving circuit may be integrated in the driving chip. The level transition timing of at least one pulse (e.g., the first pulse and/or the second pulse) of the emission control signal EM may be staggered from the data writing phase by adjusting the emission control signal EM (e.g., forward or backward, etc.), so as not to overlap. The display panel comprises a display area AA. The pixel circuit may be located in the display area AA.

Fig. 4 is a flowchart of a driving method of a display panel according to an embodiment of the present invention. The driving method of the display panel can be used to drive the display panel in the above-described embodiments. Referring to fig. 4, the driving method of the display panel provided in this embodiment includes:

s101, transmitting data voltages on data lines to pixel circuits row by row in a data writing stage of each row of pixel circuits in a frame period; the pixel circuit writes a data voltage to the pixel circuit in response to a first scan signal on a corresponding first scan line in a corresponding data writing phase.

S102, the pixel circuit emits light in response to the lighting level of a light-emitting control signal on a light-emitting control line in a light-emitting stage, wherein the light-emitting control signal on the light-emitting control line comprises at least one pulse in one frame period; in one frame period, the level transition time of at least one pulse of the light-emitting control signal of the pixel circuit of the m-th row is outside the data writing phase of the pixel circuit of the n-th row, and in one frame period, the data writing phase of the pixel circuit of the n-th row is after the data writing phase of the pixel circuit of the m-th row, and m and n are different positive integers.

Optionally, the light emission control signal on the light emission control line includes a first pulse and at least one second pulse after the first pulse within one frame period; the data writing stage of the pixel circuit is positioned in the duration of the extinction level of the first pulse of the light-emitting control signal corresponding to the pixel circuit; the level transition time of the second pulse of the light-emitting control signal of the pixel circuit of the m row is out of the duration of the active level of the first scanning signal of the pixel circuit of the n row.

According to the driving method of the display panel, in a frame period, data voltages are transmitted to the pixel circuits row by row in a data writing stage of each row of pixel circuits, wherein the level jump time of the second pulse of the light-emitting control signal of the mth row of pixel circuits is out of the data writing stage of the nth row of pixel circuits, so that the level jump of the second pulse of the light-emitting control signal of the mth row of pixel circuits cannot be coupled to the data voltages transmitted by the data lines when the data voltages are written into the nth row of pixel circuits, the data voltages of the storage capacitors filled in the nth row of pixel circuits in the frame period are all correct data voltages, the accuracy of the light-emitting brightness of the light-emitting elements is guaranteed, the flicker problem of the display panel is well solved, and the display effect of the display panel is improved.

The driving method of the display panel can be used for driving the display panel in the above embodiments, and has the advantages in the above embodiments, and will not be described herein.

Optionally, the data writing phase of the same row of pixel circuits precedes the light emitting phase in one frame period.

Optionally, before the data writing stage of the same row of pixel circuits in one frame period, the method further includes: in the initialization phase, the pixel circuit writes an initialization voltage on the initialization line to the pixel circuit in response to a second scan signal on the second scan line.

Fig. 5 is a schematic structural diagram of a display device according to an embodiment of the present invention. On the basis of the foregoing embodiments, referring to fig. 5, the display device 200 provided in this embodiment includes the display panel 100 provided in any of the foregoing embodiments, and has the beneficial effects of the display panel 100 provided in any of the foregoing embodiments, which are not described herein again. The display device 200 provided by the embodiment of the invention can comprise a mobile phone, a tablet personal computer, a wearable device and other terminals.

Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims

1. A display panel, comprising:

a plurality of pixel circuits arranged in an array;

A plurality of first scanning lines for transmitting first scanning signals to the pixel circuits of the corresponding row;

a plurality of light emission control lines for transmitting light emission control signals to the pixel circuits of the corresponding row; in one frame period, the light-emitting control signal comprises at least one pulse, in one frame period, the level transition time of the at least one pulse of the light-emitting control signal of the pixel circuit of the m-th row is outside the data writing stage of the pixel circuit of the n-th row, in one frame period, the data writing stage of the pixel circuit of the n-th row is after the data writing stage of the pixel circuit of the m-th row, and m and n are different positive integers.

2. The display panel according to claim 1, wherein the light emission control signal includes a first pulse and at least one second pulse after the first pulse within one frame period; the data writing stage of the pixel circuit is positioned in the duration of the extinction level of the first pulse of the light-emitting control signal corresponding to the pixel circuit;

3. The display panel of claim 2, wherein the display panel comprises,

in one frame period, the time when the second pulse of the light-emitting control signal of the mth row pixel circuit jumps to the off level is outside the data writing stage of the nth row pixel circuit, and/or the time when the second pulse of the light-emitting control signal of the mth row pixel circuit jumps to the on level is outside the data writing stage of the nth row pixel circuit;

preferably, in a frame period, level transition time of the second pulse of the light-emitting control signal corresponding to at least one row of pixel circuits is out of the data writing phases corresponding to the other rows of pixel circuits;

preferably, in a frame period, the level transition time of the second pulse of the light-emitting control signal corresponding to each row of pixel circuits is outside the data writing phases corresponding to the pixel circuits of the other rows.

4. The display panel of claim 2, wherein the display panel comprises,

in a frame period, the moment when the second pulse of the light-emitting control signal of the pixel circuit of the m row jumps to the extinction level is before the data writing stage of the pixel circuit of the n row; the second pulse of the light-emitting control signal of the m-th row pixel circuit jumps to the extinction level at a moment after the data writing stage of the n-1 th row pixel circuit, wherein n is an integer larger than 2;

And/or the number of the groups of groups,

in one frame period, the second pulse of the lighting control signal of the pixel circuit of the m row jumps to the lighting level before the data writing stage of the pixel circuit of the n+k row; the second pulse of the light-emitting control signal of the m-th row pixel circuit jumps to the lighting level at a time point after the data writing stage of the n+k-1-th row pixel circuit, wherein k is an integer greater than or equal to 1;

preferably, the timing at which the second pulse of the light emission control signal of the mth row pixel circuit jumps to the lighting level is after the data writing stage of the nth row pixel circuit within one frame period; the timing at which the second pulse of the light emission control signal of the m-th row pixel circuit jumps to the lighting level is after the data writing stage of the n+1th row pixel circuit.

5. The display panel of claim 2, further comprising:

a plurality of second scanning lines for transmitting second scanning signals to the corresponding pixel circuits in an initialization stage of the pixel circuits of the corresponding row; the second scanning signal is used for controlling the pixel circuit to write an initialization voltage;

Preferably, the initialization phase of the n+1th row pixel circuit coincides with the data writing phase of the n row pixel circuit;

preferably, the second scan line electrically connected to the n+1th row pixel circuit is electrically connected to the first scan line electrically connected to the n-th row pixel circuit, or is the same scan signal line.

6. The display panel according to claim 3 or 4, wherein the pixel circuit includes a driving transistor, a light emitting element, and a data writing module;

preferably, the effective level of the first scanning signal is a conduction level for controlling the conduction of the data writing module;

preferably, the data writing module comprises a data writing transistor and a threshold compensating transistor, and the grid electrode of the data writing transistor is electrically connected with the first scanning line; the data writing transistor is connected between the data line and a first pole of the driving transistor, and the threshold compensating transistor is connected between a gate of the driving transistor and a second pole;

Preferably, a gate of the threshold compensation transistor is electrically connected to the first scan line;

preferably, the plurality of data lines and the plurality of light-emitting control lines are arranged in a crossing insulation manner;

preferably, the plurality of data lines extend along a first direction and are arranged along a second direction; the plurality of light-emitting control lines extend along the second direction and are arranged along the first direction; the first direction and the second direction intersect;

the plurality of first scan lines extend along the second direction and are arranged along the first direction.

7. The display panel of claim 6, further comprising:

the pixel circuit further includes:

preferably, the effective level of the second scan signal on the second scan line is a conduction level for controlling the initialization module to be conducted.

8. The display panel of claim 6, wherein the pixel circuit further comprises: the first light-emitting control module is connected between a first power line and a first pole of the driving transistor, the second light-emitting control module is connected between a second pole of the driving transistor and a first pole of the light-emitting element, and the second pole of the light-emitting element is connected with a second power line;

the control end of the first light-emitting control module and the control end of the second light-emitting control module are connected with a light-emitting control line, and the first light-emitting control module and the second light-emitting control module are used for responding to the light-emitting control signal to control the light-emitting element to emit light in a light-emitting stage;

preferably, the extinction level is a turn-off level for controlling the first light emitting control module and/or the second light emitting control module to turn off; the lighting level is a conduction level for controlling the first light-emitting control module and/or the second light-emitting control module to be conducted.

9. A driving method of a display panel, comprising:

transmitting data voltages on data lines to pixel circuits row by row in a data writing stage of each row of pixel circuits in a frame period; the pixel circuit responds to a first scanning signal on a corresponding first scanning line in the corresponding data writing stage, and data voltages on the data lines are written into the pixel circuit;

10. The method for driving a display panel according to claim 9, wherein,

the light-emitting control signal on the light-emitting control line includes a first pulse and at least one second pulse after the first pulse within one frame period; the data writing stage of the pixel circuit is positioned in the duration of the extinction level of the first pulse of the light-emitting control signal corresponding to the pixel circuit; wherein, in a frame period, the level transition time of the second pulse of the light-emitting control signal of the pixel circuit of the m-th row is out of the data writing stage of the pixel circuit of the n-th row.