CN116312376A

CN116312376A - Pixel circuit, driving method thereof and display panel

Info

Publication number: CN116312376A
Application number: CN202310201723.7A
Authority: CN
Inventors: 桑成祥; 张春雷
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd; Hefei Visionox Technology Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd; Hefei Visionox Technology Co Ltd
Priority date: 2023-02-28
Filing date: 2023-02-28
Publication date: 2023-06-23

Abstract

The embodiment of the application provides a pixel circuit, a driving method thereof and a display panel, and relates to the technical field of display panels, wherein the pixel circuit comprises: the driving module is used for driving the light-emitting element to emit light, and the first end of the driving module is connected with a power supply signal; the storage module is used for storing the target voltage signal; the first end of the first switch module is electrically connected with the storage module, and the second end of the first switch module is electrically connected with the second end of the driving module; the storage module stores the target voltage signal in a bias phase or in a target voltage signal writing phase located before the bias phase; in the bias phase before the data writing phase, the first switch module is conducted, and the target voltage signal in the storage module is transmitted to the second end of the driving module through the first switch module. According to the embodiment of the application, the flicker phenomenon generated during low-frequency display of the display panel can be improved, and the picture display effect is improved.

Description

Pixel circuit, driving method thereof and display panel

Technical Field

The application belongs to the technical field of display panels, and particularly relates to a pixel circuit, a driving method thereof and a display panel.

Background

At present, with the continuous development of Active-matrix organic light-emitting diode (Active matrix organic light emitting diode) display technology, the functions of an AMOLED display panel are continuously updated, and the AMOLED display panel can pertinently adopt different display modes in different working scenes. Typically, in the locked state, the AMOLED display panel enters an inactive display (Always On Display, AOD) mode that reduces the current consumed during standby to increase the battery life.

After the AMOLED display panel enters an AOD display mode, the power consumption of a screen body or an integrated circuit of the display panel can be effectively reduced through an adaptive refresh rate technology, but in the process of reducing the refresh rate, the gate voltage of a driving thin film field effect transistor (Driving Thin Film Transistor, DTFT) in an internal pixel circuit is always in a constant voltage state, so that the threshold voltage of the driving thin film field effect transistor is in a bias state for a long time, thereby influencing the driving current flowing into an Organic Light-Emitting Diode (OLED), further influencing the display state of the display panel, and causing the display panel to have a low-frequency flicker phenomenon.

Disclosure of Invention

The embodiment of the application provides a pixel circuit, a driving method thereof and a display panel, which can be beneficial to improving the flicker phenomenon of the display panel during low-frequency display and improving the picture display effect.

In a first aspect, embodiments of the present application provide a pixel circuit, including:

the driving module is used for driving the light-emitting element to emit light, and the first end of the driving module is connected with a power supply signal;

the storage module is used for storing the target voltage signal;

the first end of the first switch module is electrically connected with the storage module, and the second end of the first switch module is electrically connected with the second end of the driving module;

the storage module stores a target voltage signal in a bias phase or in a target voltage signal writing phase located before the bias phase;

in the bias phase before the data writing phase, the first switch module is conducted, and the target voltage signal in the storage module is transmitted to the second end of the driving module through the first switch module.

In a possible implementation manner of the first aspect, the pixel circuit further includes a second switch module; the control end of the second switch module is electrically connected with the first scanning signal line, the first end of the second switch module is electrically connected with the storage module, and the second end of the second switch module is electrically connected with the first reference voltage signal end; in the bias stage or in the target voltage signal writing stage before the bias stage, the second switch module is conducted under the control of the first scanning signal line, and the target voltage signal provided by the first reference voltage signal end is transmitted to the storage module.

In a possible implementation manner of the first aspect, a first end of the memory module is electrically connected to the control end of the driving module, and a second end of the memory module is connected to the first power supply voltage signal end; the first end of the second switch module is electrically connected with the first end of the storage module and the control end of the driving module; in an initialization stage after the bias stage, the second switch module is turned on under the control of the first scanning signal line, and transmits a first reference voltage signal provided by the first reference voltage signal end to the control end of the driving module so as to initialize the control end of the driving module.

In a possible implementation manner of the first aspect, the voltage value of the target voltage signal is different from the voltage value of the first reference voltage signal.

In a possible implementation manner of the first aspect, the voltage value of the target voltage signal is greater than the voltage value of the first reference voltage signal.

In a possible implementation manner of the first aspect, the control terminal of the driving module is electrically connected to the first terminal of the first switch module, and the pixel circuit further includes a data writing module; the control end of the data writing module is electrically connected with the second scanning signal line, the first end of the data writing module is electrically connected with the data signal end, and the second end of the data writing module is electrically connected with the first end of the driving module; the control end of the first switch module is electrically connected with the third scanning signal line; in the data writing stage after the bias stage, the data writing module is conducted under the control of the second scanning signal line, and the first switch module is conducted under the control of the third scanning signal line so as to transmit the data signal of the data signal end to the first end of the driving module.

In a possible implementation manner of the first aspect, the control terminal of the first switch module is electrically connected to the third scan signal line, and the waveforms of the scan signals output by the first scan signal line and the third scan signal line connected to the same pixel circuit are the same and are different by a preset interval.

In one possible implementation manner of the first aspect, the waveforms and phases of the scanning signals output by the first scanning signal line connected to the pixel circuit of the i-1 th row and the scanning signal output by the third scanning signal line connected to the pixel circuit of the i-1 th row are the same;

in one possible implementation manner of the first aspect, the first scan signal line connected to the pixel circuit of the i-1 th row and the third scan signal line connected to the pixel circuit of the i-1 th row are all electrically connected to the output terminal of the same shift register, and i is a positive integer.

In a possible implementation manner of the first aspect, one frame display period includes a refresh frame and a hold frame, wherein the control end of the driving module is refreshed when the frame is refreshed, and the control end of the driving module is not refreshed when the frame is held; the refresh frame and the hold frame include a bias phase.

In a possible implementation manner of the first aspect, one screen display period includes 1 refresh frame and N hold frames, where N is a positive integer, and the refresh frame and the N hold frames each include a bias phase.

In a possible implementation manner of the first aspect, the first switch module and the second switch module each include an oxide thin film transistor.

In a possible implementation manner of the first aspect, the first switch module and the second switch module each include an N-type transistor.

Based on the same inventive concept, in a second aspect, an embodiment of the present application provides a driving method of a pixel circuit, which is applied to the pixel circuit provided in any one of the foregoing embodiments in the first aspect of the present application, where the driving method of the pixel circuit includes: storing, by the memory module, the target voltage signal during the bias phase or during a target signal writing phase preceding the bias phase; and in a bias stage before the data writing stage, controlling the first switch module to be conducted so that a target voltage signal in the storage module is transmitted to the second end of the driving module through the first switch module.

In a possible implementation manner of the second aspect, the pixel circuit further includes a second switch module; the driving method of the pixel circuit further includes: in the bias stage or in the target voltage signal writing stage before the bias stage, the second switch module is conducted by controlling the conduction level of the first scanning signal line output second switch module, and the target voltage signal provided by the first reference voltage signal end is transmitted to the storage module.

Based on the same inventive concept, in a third aspect, the present embodiment provides a display panel, which includes the pixel circuit provided in any one of the foregoing embodiments of the first aspect of the present application.

Based on the same inventive concept, in a fourth aspect, the present embodiment provides a display device including a display panel as provided in the embodiments of the third aspect of the present application.

According to the pixel circuit, the driving module, the storage module and the first switch module are arranged in the pixel circuit, the first end of the first switch module is electrically connected with the storage module, the second end of the first switch module is electrically connected with the second end of the driving module, the target voltage signal is stored through the storage module in the bias stage or the target voltage signal writing stage before the bias stage, the target voltage signal stored by the storage module is transmitted to the second end of the driving module through the first switch module in the bias stage before the data writing module, an additional bias voltage writing transistor is not needed to be added, the bias state of the driving module can be adjusted through the target voltage signal, the threshold voltage of the driving module is adjusted, the flicker phenomenon occurring during low-frequency display of the display panel is improved, and the picture display effect is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described, and it is possible for a person skilled in the art to obtain other drawings according to these drawings without inventive effort.

Fig. 1 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

fig. 2 is another schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

fig. 3 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

fig. 4 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

fig. 5 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

fig. 6 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

FIG. 7 is a timing diagram of the pixel circuit shown in FIG. 6;

fig. 8 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

FIG. 9 is a timing diagram of the pixel circuit shown in FIG. 8;

FIG. 10 is another timing diagram of the pixel circuit shown in FIG. 8;

fig. 11 is a schematic flow chart of a driving method of a pixel circuit according to an embodiment of the present application;

Fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

Features and exemplary embodiments of various aspects of the present application are described in detail below to make the objects, technical solutions and advantages of the present application more apparent, and to further describe the present application in conjunction with the accompanying drawings and the detailed embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative of the application and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by showing examples of the present application.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

It should be noted that, the transistor in the embodiment of the present application may be an N-type transistor or a P-type transistor. For an N-type transistor, the on level is high and the off level is low. That is, the gate of the N-type transistor is on between the first and second poles when the gate is high, and is off between the first and second poles when the gate is low. For a P-type transistor, the on level is low and the off level is high. That is, when the control of the P-type transistor is at a very low level, the first pole and the second pole are turned on, and when the control of the P-type transistor is at a high level, the first pole and the second pole are turned off. In a specific implementation, the gate of each transistor is used as a control electrode, and the first electrode of each transistor may be used as a source electrode, the second electrode may be used as a drain electrode, or the first electrode may be used as a drain electrode, and the second electrode may be used as a source electrode, which is not distinguished herein.

In the embodiments herein, the term "electrically connected" may refer to two components being directly electrically connected, or may refer to two components being electrically connected via one or more other components.

In the embodiment of the present application, the first node, the second node, and the third node are defined only for convenience in describing the circuit structure, and the first node, the second node, and the third node are not one actual circuit unit.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Accordingly, this application is intended to cover such modifications and variations of this application as fall within the scope of the appended claims (the claims) and their equivalents. The embodiments provided in the examples of the present application may be combined with each other without contradiction.

Before describing the technical solution provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

the inventor researches that, when the AMOLED display panel displays at low frequency, the display panel displays fewer frames per second, and accordingly, in order to prolong the light emitting time of the organic light emitting diode in each frame, the gate voltage of the driving transistor in the pixel circuit needs to be in a constant voltage state for a long time, and the leakage time of the gate of the driving transistor is prolonged, so that the threshold voltage of the driving transistor is also in a bias state for a long time.

In this way, the threshold voltage of the driving transistor is biased for a long time, so that the driving current of the driving transistor for driving the organic light emitting diode to emit light is unstable, thereby influencing the display state of the display panel, and causing the display panel to generate a flicker phenomenon during low-frequency display.

In view of the above-mentioned research of the inventor, in order to solve the problems of the prior art, embodiments of the present application provide a pixel circuit, a driving method thereof, and a display panel. The pixel circuit provided in the embodiment of the present application will be described first.

Fig. 1 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present application. As shown in fig. 1, the pixel circuit 10 may specifically include a driving module 101, a storage module 102, and a first switching module 103. A first end of the first switch module 103 may be electrically connected with the memory module 102, and a second end of the first switch module 103 may be electrically connected with a second end of the driving module 101. The second end of the driving module 101 may be understood as the output end of the driving current of the driving module 101. Illustratively, the driving module 101 may be a transistor, and the second terminal of the driving module 101 may be specifically a drain (or a source) of the transistor.

The driving module 101 may be used to drive the light emitting element to emit light. The target voltage signal is stored by the above-described storage module 102 in the bias phase or the target voltage signal writing phase preceding the bias phase. In the bias phase before the data writing phase of the pixel circuit 10, the first switch module 103 is turned on, and the target voltage signal in the storage module 102 is transmitted to the second end of the driving module 101 through the first switch module 103, so that the bias state of the driving module 101 is adjusted by writing the target voltage signal. For example, the target voltage signal is written into the second end of the driving module 101 through the turned-on first switch module, so that the voltage difference between the electric potential of the second end of the driving module 101 and the electric potential of the control end of the driving module 101 is reduced and even tends to be consistent, thereby improving the drifting phenomenon of the threshold voltage Vth caused by the fact that the control end of the driving module 101 is in a constant voltage state for a long time, further improving the flickering phenomenon occurring during low-frequency display of the display panel, and further improving the picture display effect.

According to the pixel circuit, the driving module 101, the storage module 102 and the first switch module 103 are arranged, the first end of the first switch module 103 is electrically connected with the storage module 102, the second end of the first switch module 103 is electrically connected with the second end of the driving module 101, and the target voltage signal is stored through the storage module 102 in the bias phase or the target voltage signal writing phase before the bias phase. In the bias stage before data writing, the target voltage signal stored by the storage module 102 is transmitted to the second end of the driving module 101 through the first switch module 103, and the bias state of the driving module 101 can be adjusted through the target voltage signal without adding an additional bias voltage writing transistor, so that the threshold voltage of the driving module 101 is adjusted, the flicker phenomenon occurring during low-frequency display of the display panel is improved, and the picture display effect is improved.

In some more specific embodiments, in order to more reasonably adjust the bias state of the driving module 101 to substantially improve the low-frequency flicker phenomenon of the display panel, the control terminal of the driving module 101 may be electrically connected to the first terminal of the first switch module 103. The voltage value of the target voltage signal is smaller than the sum of the voltage value of the power signal and the threshold voltage of the driving module 101, so as to ensure effective conduction of the driving module 101. In this way, when the voltage bias circuit is in the bias phase, the target voltage signal in the storage module 102 is transmitted to the second end of the driving module 101 through the turned-on first switch module 103, and the control end of the driving module 101 is communicated with the second end of the driving module 101 through the turned-on first switch module 103, so that the electric potentials of the control end and the second end of the driving module 101 tend to be consistent, the threshold voltage drift phenomenon caused by long-term constant voltage of the control end of the driving module 101 is effectively inhibited, the flicker phenomenon of the display panel during low-frequency display is effectively improved, and the picture display effect is greatly improved.

Referring to fig. 2, fig. 2 is another circuit schematic of the pixel circuit according to the embodiment of the present application. As shown in fig. 2, in some embodiments, the bias signal voltage may be stored to the storage capacitor 102 in advance or simultaneously with the writing of the target voltage signal to enable the writing of the target voltage signal to the second terminal of the driving module 101 during the bias phase. Optionally, the pixel circuit 10 may further include a second switch module 104, where a control end of the second switch module 104 is electrically connected to the first scan signal line S1, a first end of the second switch module 104 is electrically connected to the memory module 102, and a second end of the second switch module 104 is electrically connected to the first reference voltage signal terminal vref 1. In the bias phase or in the target voltage signal writing phase before the bias phase, the second switch module 104 is turned on under the control of the first scan signal line S1 to transmit the target voltage signal provided by the first reference voltage signal terminal vref1 to the memory module 102.

In some embodiments, when the target voltage signal provided by the first reference voltage signal terminal vref1 is transmitted to the memory module 102 in the target voltage signal writing stage before the biasing stage, the first switch module 103 may be turned off, the second switch module 104 is turned on in response to the turn-on level provided by the first scan signal line S1, and the target voltage signal provided by the first reference voltage signal terminal vref1 is transmitted to the memory module 102 through the turned-on second switch module 104. In this way, the storage module 102 stores the target voltage signal, so that the target voltage signal can be written to the second terminal of the driving module 101 via the turned-on first switch module 103 in the subsequent bias stage.

In other embodiments, when the target voltage signal provided by the first reference voltage signal terminal vref1 is transmitted to the memory module 102 during the bias phase of the pixel circuit of the present application, the first switch module 103 is controlled to be turned on by the corresponding control signal, and the second switch module 104 is turned on in response to the turn-on level provided by the first scan signal line S1. At this time, the target voltage signal provided by the first reference voltage signal terminal vref1 is transmitted to the memory module 102 through the turned-on second switch module 104, and is stored in the memory module 102.

In this way, in the bias phase or in the target voltage signal writing phase before the bias phase, the second switch module 104 turned on stores the target voltage signal provided by the first reference voltage signal terminal vref1 into the storage module 102, so as to write the stored target voltage signal into the second terminal of the driving module 101 in the bias phase, thereby effectively improving the low flicker phenomenon of the display panel.

Referring to fig. 3, fig. 3 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present application. As shown in fig. 3, the data writing process of the pixel circuit data writing stage is adversely affected in consideration of the possible residual charges at the control terminal of the driving module 101.

Accordingly, in order to sufficiently secure the picture display effect of the display panel, in some embodiments, optionally, the first terminal of the memory module 102 may be further electrically connected to the control terminal of the driving module 101, and the second terminal of the memory module 102 may be connected to the first power voltage signal terminal ELVDD. The first end of the second switch module 104 may be electrically connected to the first end of the memory module 102 and the control end of the driving module 101, and the second end of the second switch module 104 is electrically connected to the first reference voltage signal end vref 1. It should be noted that the power signal connected to the first terminal of the driving module 101 may be provided by the first power voltage signal terminal ELVDD, but in other embodiments, the power signal may be provided by other power voltage signal terminals, which is not limited in this application.

In the initialization stage after the bias stage, the second switch module 104 is turned on in response to the turn-on level provided by the first scan signal line S1, and the first reference voltage signal provided by the first reference voltage signal terminal vref1 may be transmitted to the control terminal of the driving module 101 through the turned-on second switch module 104, so as to initialize the control terminal of the driving module 101. When the driving module 101 is a driving transistor, the control terminal of the driving module 101 may be specifically a gate of the driving transistor.

In some embodiments, the voltage value of the target voltage signal may be different from the voltage value of the first reference voltage signal in consideration of the actual display panel's display condition and the timing requirements of different stages in each frame. Further, in some embodiments, the inventors of the present application have found that the target voltage signal is actually used to adjust the bias state of the driving module 101 during the bias phase, and the first reference voltage signal is substantially used to initialize the control terminal of the driving module 101 during the initialization phase after the bias phase, so as to solve the problem of discharging the residual charge at the control terminal of the driving module 101 and ensure the sufficient conduction of the driving module 101. Based on this, in order to achieve a reasonable utilization of the voltage signal, the voltage value of the target voltage signal may be greater than the voltage value of the first reference voltage signal.

Referring to fig. 4, fig. 4 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present application. In some embodiments, based on the above scheme, the control terminal of the driving module 101 is electrically connected to the first terminal of the first switch module 103, the pixel circuit 10 may further include a data writing module 105, the control terminal of the data writing module 105 is electrically connected to the second scan signal line S2, the first terminal of the data writing module 105 is electrically connected to the data signal terminal data, and the second terminal of the data writing module 105 is electrically connected to the first terminal of the driving module 101.

In the data writing stage following the bias stage, the data writing module 105 is turned on in response to the turn-on level supplied from the second scan signal line S2. In this way, the data signal of the data signal terminal can be transmitted to the first terminal of the driving module 101 through the turned-on data writing module 105.

Referring to fig. 5, fig. 5 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present application. In some more specific embodiments, optionally, the control terminal of the first switch module 103 may be electrically connected to the third scan signal line S3.

Specifically, in the data writing stage after the bias stage, the data writing module 105 is turned on under the control of the second scan signal line, and the first switch module 103 is turned on in response to the turn-on level provided by the third scan signal line S3, and the control terminal of the driving module 101 is connected to the second terminal of the driving module 101. The data signal of the data signal terminal data is written into the first terminal of the driving module 101, and the first terminal of the driving module 101 and the control terminal are electrically connected due to the potential difference. In this way, the data signal of the data signal terminal data is written into the control terminal of the driving module 101 through the turned-on data writing module 105, the turned-on driving module 101 and the turned-on first switching module 103, and the compensation of the threshold voltage of the driving module 101 is realized while the data signal is written.

In some embodiments, in order to achieve reasonable arrangement of the scan signal lines connected to the pixel circuits, the control terminal of the first switch module 103 is electrically connected to the third scan signal line S3. The waveforms of the scanning signals output from the first scanning signal line S1 and the third scanning signal line S3 connected to the same pixel circuit 10 may be identical and may be out of phase by a predetermined interval. For example, the waveform phases of the scanning signals output from the first scanning signal line S1 and the third scanning signal line S3 may be different by a phase corresponding to a half period.

In some more specific embodiments, in order to reasonably realize multiplexing of the scan signals, the waveforms and phases of the scan signals output by the first scan signal line S1 connected to the pixel circuit of the i-1 th row and the third scan signal line S3 connected to the pixel circuit of the i-1 th row are the same.

In some more specific embodiments, considering that the pixel circuits in the display panel are turned on row by row, based on this, in combination with the specific operation timing setting of the pixel circuits, in order to further promote the reasonable utilization of the pixel circuit scanning signal lines in the display panel, the first scanning signal line S1 connected to the i-1 th row of pixel circuits and the third scanning signal line S3 connected to the i-1 th row of pixel circuits may all be electrically connected to the output end of the same shift register, where i is a positive integer.

That is, in the present application, the scan signals output from the first scan signal line of the i-th row and the third scan signal line of the i-1-th row in the display panel may be provided for the same shift register. Therefore, reasonable multiplexing of each shift register in the display panel is realized, and the wiring complexity of the pixel circuits in the display panel is effectively simplified.

In some embodiments, in combination with practical application scenario consideration of the display panel, one frame display period may include a refresh frame and a hold frame, where the control end of the driving module 101 is refreshed when the frame is refreshed, and the control end of the driving module 101 is not refreshed when the frame is held. In order to fully ensure the picture display effect, the refresh frame and the hold frame can comprise offset stages.

In some more specific embodiments, one screen display period of the display panel may specifically include 1 refresh frame and N hold frames, where N is a positive integer. In the picture display period, the refreshing frame and the N holding frames can comprise the offset stage, so that the display effect of the display panel under each frame can be effectively improved, and the flicker phenomenon of the display panel is avoided.

In some embodiments, on the basis of the above scheme, considering that the off-state leakage current of the oxide transistor is small, in order to achieve sufficient blocking of the first switch module 103 and the second switch module 104, optionally, both the first switch module 103 and the second switch module 104 may include oxide thin film transistors.

When the first switch module 103 and the second switch module 104 are both oxide transistors, the transistors can be fully turned off under the control of the corresponding scanning signal line cut-off level, so that the leakage current path of the control end of the driving module 101 can be reduced, and the potential variation amplitude of the corresponding node of the control end of the driving module 101 can be effectively reduced, so that the driving current generated by the subsequent driving module 101 is more accurate.

Further, in some more specific embodiments, the first switch module 103 and the second switch module 104 may each include an N-type transistor. When the first switch module 103 and the second switch module 104 are both N-type transistors, the on level of the first scanning signal line S1 is high, and the off level is low. The second scanning signal line S2 has a high on level and a low off level.

In order to facilitate understanding of the pixel circuits provided herein, the following description is provided in connection with some specific application embodiments.

Referring to fig. 6, fig. 6 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present application. As shown in fig. 6, in the pixel circuit 10 provided in this embodiment, optionally, the driving module 101 may be a P-type driving transistor T1, the storage module 102 may be a storage elevator Cst, the first switch module 103 may be an N-type transistor T3, the second switch module 104 may be an N-type transistor T4, and the data writing module 105 may be a P-type transistor T2. The first terminal of the transistor T3 may be electrically connected to the memory module Cst, and the second terminal of the transistor T3 may be electrically connected to the second terminal of the driving transistor T1. The control terminal of the transistor T4 is electrically connected to the first scan signal line S1, the first terminal of the transistor T4 is electrically connected to the first terminal of the memory module Cst, the first terminal of the transistor T4 is further electrically connected to the control terminal of the driving transistor T1, and the second terminal of the transistor T4 is electrically connected to the first reference voltage signal terminal vref 1. The first terminal of the storage module Cst may be further electrically connected to the control terminal of the driving transistor T1, and the second terminal of the storage module Cst may be connected to the first power voltage signal terminal ELVDD. The control terminal of the transistor T2 is electrically connected to the second scan signal line S2, the first terminal of the transistor T2 is electrically connected to the data signal terminal data, and the second terminal of the transistor T2 is electrically connected to the first terminal of the driving transistor T1. The control terminal of the transistor T3 may be electrically connected to the third scan signal line S3. The power signal connected to the first terminal of the driving transistor T1 may be provided by the first power voltage signal terminal ELVDD, or may be provided by another power voltage signal terminal, which is not specifically limited in this application.

Fig. 7 is a timing diagram of the pixel circuit shown in fig. 6. The pixel circuit shown in fig. 6 will be described with reference to the timing sequence shown in fig. 7, and the operation of the pixel circuit in fig. 6 may specifically include: a target voltage signal writing stage t0, a bias stage t1, an initialization stage t2, and a data writing stage t3.

In the target voltage signal writing stage t0, the first scanning signal line S1 provides an on level, the second scanning signal line S2 provides an off level, and the third scanning signal line S3 provides an off level. The transistor T4 is turned on under the control of the first scan signal line S1, the transistor T2 is turned off under the control of the second scan signal line S2, and the transistor T3 is turned off under the control of the third scan signal line S3. The target voltage signal provided by the first reference voltage signal terminal vref1 is transmitted to the storage capacitor Cst through the turned-on transistor T4, and the storage capacitor Cst stores the target voltage signal.

In the bias stage t1, the first scan signal line S1 provides a cut-off level, the second scan signal line S2 provides a cut-off level, and the third scan signal line S3 provides a turn-on level. The transistor T4 is turned off under the control of the first scan signal line S1, the transistor T2 is turned off under the control of the second scan signal line S2, and the transistor T3 is turned on under the control of the third scan signal line S3. The target voltage signal stored in the storage capacitor Cst is transmitted to the second terminal of the driving transistor T1 through the turned-on transistor T3, so as to implement adjustment of the bias state of the driving transistor T1. The second terminal of the driving transistor T1 may be understood as an output terminal of the driving current of the driving transistor T1.

In the initialization stage t2, the first scan signal line S1 provides an on level, the second scan signal line S2 provides an off level, and the third scan signal line S3 provides an off level. The transistor T4 is turned on under the control of the first scan signal line S1, the transistor T2 is turned off under the control of the second scan signal line S2, and the transistor T3 is turned off under the control of the third scan signal line S3. The first reference voltage signal provided by the first reference voltage signal terminal vref1 is transmitted to the control terminal of the driving transistor T1 through the turned-on transistor T4, thereby initializing the control terminal of the driving transistor T1. The control terminal of the driving transistor T1 may specifically be a gate of the driving transistor. The voltage value of the target voltage signal is smaller than the sum of the voltage value of the power supply signal and the threshold voltage of the driving transistor T1.

In the data writing stage t3, the first scan signal line S1 provides a cut-off level, the second scan signal line S2 provides a turn-on level, and the third scan signal line S3 provides a turn-on level. The transistor T4 is turned off under the control of the first scan signal line S1, the transistor T2 is turned on under the control of the second scan signal line S2, and the transistor T3 is turned on under the control of the third scan signal line S3. The data signal of the data signal terminal data is written into the first terminal of the driving transistor T1 through the transistor T2, and the control terminal of the driving transistor T1 is communicated with the second terminal of the driving transistor T1 through the turned-on transistor T3. The first terminal and the control terminal of the driving transistor T1 are turned on due to the potential difference. Thus, the data signal of the data signal terminal data is finally written into the control terminal of the driving transistor T1 through the turned-on transistor T2, the turned-on driving transistor T1, and the turned-on transistor T3.

According to the pixel circuit provided by the embodiment of the application, the bias voltage writing stage and the bias stage are additionally arranged by changing the time sequence of the pixel circuit, the target voltage signal is stored by the storage module, and in the bias stage, the target voltage signal stored by the storage module is transmitted to the second end of the driving module through the first switch module, so that the bias state of the driving module can be adjusted through the target voltage signal without adding an additional bias voltage writing transistor. The pixel circuit can fully and effectively improve the flicker phenomenon of the display panel during low-frequency display on the basis of not increasing the element cost, and improves the picture display effect.

It should be noted that the pixel circuit 10 may include other transistors in addition to the transistors listed above, and these transistors together constitute a plurality of types of pixel circuits. That is, the embodiments of the present application can be applied to various types of pixel circuits such as 7T1C, 7T2C, or 9T 1C.

For ease of understanding, the following description will be given with reference to a 7T1C pixel circuit as an example.

Fig. 8 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure. As shown in fig. 8, alternatively, in the pixel circuit 10 provided in this embodiment, in addition to the structure shown in fig. 6 described above, the pixel circuit 10 further includes a transistor T5 (P-type), a transistor T6 (P-type), a transistor T7 (P-type), and an organic light emitting diode OLED. The first end of the transistor T5 is electrically connected to the first power voltage signal end ELVDD, the control end of the transistor T5 is electrically connected to the light emission control signal end EM, the second end of the transistor T5 is electrically connected to the first end of the driving transistor T1, the first end of the transistor T6 is electrically connected to the second end of the driving transistor T1, the control end of the transistor T6 is electrically connected to the light emission control signal end EM, the second end of the transistor T6 is electrically connected to the anode of the OLED, the cathode of the OLED is electrically connected to the ground voltage signal end ELVSS, the first end of the transistor T7 is electrically connected to the anode of the OLED, the control end of the transistor T7 is electrically connected to the fourth scan signal line S4, and the second end of the transistor T7 is electrically connected to the second reference voltage signal end vref 2. The power signal connected to the first terminal of the driving transistor T1 may be provided by the first power voltage signal terminal ELVDD.

Fig. 9 is a timing diagram of the pixel circuit shown in fig. 8. Describing the 7T1C pixel circuit shown in fig. 8 with reference to the timing sequence shown in fig. 9, the operation of the pixel circuit in fig. 8 may be divided into a light-emitting phase and a non-light-emitting phase, in which the light-emitting control signal terminal EM outputs a cut-off level, and the transistors T5 and T6 are cut-off under the control of the light-emitting control signal terminal EM, so that the OLED does not emit light. In the light emitting stage, the first scan signal line S1, the second scan signal line S2, the third scan signal line S3 and the fourth scan signal line S4 all provide cut-off levels, the light emitting control signal end EM outputs on levels, and the transistor T5 and the transistor T6 are turned on under the control of the light emitting control signal end EM to drive the OLED to emit light.

The non-light-emitting stage may specifically include: a target voltage signal writing stage t0, a bias stage t1, an initialization stage t2, and a data writing stage t3.

In the target voltage signal writing stage t0, the first scan signal line S1 provides an on level, the second scan signal line S2 provides an off level, the third scan signal line S3 provides an off level, and the fourth scan signal line S4 provides an off level. The transistor T4 is turned on under the control of the first scan signal line S1, the transistor T2 is turned off under the control of the second scan signal line S2, the transistor T3 is turned off under the control of the third scan signal line S3, and the transistor T7 is turned off under the control of the fourth scan signal line S4. The target voltage signal provided by the first reference voltage signal terminal vref1 is transmitted to the storage capacitor Cst through the turned-on transistor T4, and the storage capacitor Cst stores the target voltage signal.

In the bias stage t1, the first scan signal line S1 provides a cut-off level, the second scan signal line S2 provides a cut-off level, the third scan signal line S3 provides a turn-on level, and the fourth scan signal line S4 provides a cut-off level. The transistor T4 is turned off under the control of the first scan signal line S1, the transistor T2 is turned off under the control of the second scan signal line S2, the transistor T3 is turned on under the control of the third scan signal line S3, and the transistor T7 is turned off under the control of the fourth scan signal line S4. The target voltage signal stored in the storage capacitor Cst is transmitted to the second terminal of the driving transistor T1 through the turned-on transistor T3, so as to implement adjustment of the bias state of the driving transistor T1. The second terminal of the driving transistor T1 may be understood as an output terminal of the driving current of the driving transistor T1, and the voltage value of the target voltage signal is smaller than the sum of the power supply signal and the threshold voltage of the driving transistor.

In the initialization stage t2, the first scan signal line S1 provides an on level, the second scan signal line S2 provides an off level, the third scan signal line S3 provides an off level, and the fourth scan signal line S4 provides an off level. The transistor T4 is turned on under the control of the first scan signal line S1, the transistor T2 is turned off under the control of the second scan signal line S2, the transistor T3 is turned off under the control of the third scan signal line S3, and the transistor T7 is turned off under the control of the fourth scan signal line S4. The first reference voltage signal provided by the first reference voltage signal terminal vref1 is transmitted to the control terminal of the driving transistor T1 through the turned-on transistor T4, thereby initializing the control terminal of the driving transistor T1. The control terminal of the driving transistor T1 may specifically be a gate of the driving transistor.

In the data writing stage t3, the first scan signal line S1 provides a cut-off level, the second scan signal line S2 provides a turn-on level, the third scan signal line S3 provides a turn-on level, and the fourth scan signal line S4 provides a turn-on level. The transistor T4 is turned off under the control of the first scan signal line S1, the transistor T2 is turned on under the control of the second scan signal line S2, the transistor T3 is turned on under the control of the third scan signal line S3, and the transistor T7 is turned on under the control of the fourth scan signal line S4. The data signal of the data signal terminal data is written into the first terminal of the driving transistor T1 through the transistor T2, and the control terminal of the driving transistor T1 is communicated with the second terminal of the driving transistor T1 through the turned-on transistor T3. The first terminal and the control terminal of the driving transistor T1 are turned on due to the potential difference. Thus, the data signal of the data signal terminal data is finally written into the control terminal of the driving transistor T1 through the turned-on transistor T2, the turned-on driving transistor T1 and the turned-on transistor T3; the second reference voltage signal provided by the second reference voltage signal terminal vref2 is written into the OLED anode through the turned-on transistor T2, so that the initialization of the OLED anode is realized.

In some more specific embodiments, please refer to fig. 10, fig. 10 is another timing diagram of the pixel circuit shown in fig. 8. The operation timings of the pixel circuits of the i-1 th and i-th rows are shown in fig. 10.

As can be seen from fig. 10, the waveforms and phases of the scanning signals output from the first scanning signal line S1 connected to the i-1 th row pixel circuit and the third scanning signal line S3 connected to the i-1 th row pixel circuit are identical. Based on this, in this embodiment, the first scan signal line S1 connected to the pixel circuit of the i-1 th row and the third scan signal line S3 connected to the pixel circuit of the i-1 th row in fig. 10 may be all electrically connected to the output terminal of the same shift register.

In summary, in the pixel circuit provided by the embodiment of the application, the bias voltage writing stage and the bias stage are additionally arranged by changing the time sequence of the pixel circuit, and based on different signal outputs of the additionally arranged stages, the target voltage signal is stored by the storage module, and in the bias stage, the target voltage signal stored by the storage module is transmitted to the second end of the driving module through the first switch module, and the bias state of the driving module can be adjusted through the target voltage signal without adding an additional bias voltage writing transistor. The pixel circuit can fully and effectively improve the flicker phenomenon of the display panel during low-frequency display on the basis of not increasing the element cost, and improves the picture display effect.

Based on the same inventive concept, correspondingly, the present application also provides a driving method of the pixel circuit, which is applied to the pixel circuit 11 provided in any of the above embodiments of the present application. Referring to fig. 11, fig. 11 is a flow chart of a driving method of a pixel circuit according to an embodiment of the present disclosure.

As shown in fig. 11, the driving method of the pixel circuit includes:

s1110, storing the target voltage signal through a storage module in a bias phase or in a target voltage signal writing phase before the bias phase;

and S1120, in a biasing stage before the data writing stage, controlling the first switch module to be conducted so as to enable the target voltage signal in the storage module to be transmitted to the second end of the driving module through the first switch module.

The target voltage signal is stored by the memory module, for example, during a bias phase or during a target voltage signal writing phase that precedes the bias phase. In the offset stage before the data writing stage, the on control of the first switch module can be realized by controlling the output of the shift register corresponding to the scanning signal end connected with the control end of the first switch module. In this way, under the condition that the first switch module is conducted, the target voltage signal in the storage module can be transmitted to the second end of the driving module through the conducted first switch module, so that the second end of the driving module is reset.

According to the driving method of the pixel circuit, the first switch module is controlled to be conducted through the bias stage, so that the target voltage signal stored in the storage module in the pixel circuit can be transmitted to the second end of the driving module through the conducted first switch module. Therefore, the bias state of the driving module is adjusted through the target voltage signal, so that the threshold voltage of the driving module is adjusted, the flicker phenomenon occurring during low-frequency display of the display panel is effectively improved, and the picture display effect is improved.

In some possible implementations, in order to reasonably implement driving of the pixel circuit in the foregoing embodiment, the foregoing pixel circuit may optionally further include a second switching module; the driving method of the pixel circuit may further include:

in the bias stage or in the target voltage signal writing stage before the bias stage, the second switch module is conducted by controlling the conduction level of the first scanning signal line output second switch module, and the target voltage signal provided by the first reference voltage signal end is transmitted to the storage module.

Specifically, in the bias stage or in the target voltage signal writing stage located before the bias stage, the first scan signal line may be enabled to output the on level of the second switch module by controlling the output of the shift register connected to the first scan signal line. In this way, the second switch module is turned on in response to the turn-on level of the first scan signal line, and the target voltage signal provided by the first reference voltage signal terminal is transmitted to the memory module through the turned-on second switch module, so that the target voltage signal stored in the memory module is transmitted to the second terminal of the driving module in the bias stage.

Based on the pixel circuits provided in any of the above embodiments, correspondingly, the present application further provides a display panel, including the pixel circuit 10 provided in the present application. Referring to fig. 12, fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. As shown in fig. 12, the display panel 100 provided in the embodiment of the present application may include the pixel circuit 10 described in any of the embodiments above. The display panel shown in fig. 12 may be an Organic Light-Emitting Diode (OLED) display panel.

Those skilled in the art will appreciate that in other implementations of the present application, the display panel may also be a Micro light emitting diode (Micro LED) display panel, a quantum dot display panel, or the like.

The display panel provided in the embodiment of the present application has the beneficial effects of the pixel circuit 10 provided in the embodiment of the present application, and the specific description of the pixel circuit 10 in the above embodiments may be referred to specifically, and the description of the embodiment is omitted herein.

Based on the display panel provided by the embodiment, correspondingly, the application also provides a display device comprising the display panel provided by the application. Referring to fig. 13, fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. Fig. 13 provides a display device 1000 including a display panel 100 according to any of the embodiments described above. The embodiment of fig. 13 is described with respect to the display device 1000 by taking a mobile phone as an example, and it is to be understood that the display device provided in the embodiment of the present application may be a wearable product, a computer, a television, a vehicle-mounted display device, or other display devices having a display function, which is not particularly limited in this application. The display device provided in the embodiment of the present application has the beneficial effects of the display panel 100 provided in the embodiment of the present application, and the specific description of the display panel 100 in the above embodiments may be referred to specifically, and the description of the embodiment is omitted herein.

It should be understood that the specific structures of the circuits and the display panel structures provided in the drawings of the embodiments of the present application are only examples and are not intended to limit the present application. In addition, the above embodiments provided herein may be combined with each other without contradiction.

It should be understood that, in the present specification, each embodiment is described in an incremental manner, and the same or similar parts between the embodiments are all referred to each other, and each embodiment is mainly described in a different point from other embodiments. These embodiments are not all details described in detail in accordance with the embodiments described hereinabove, nor are they intended to limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. This application is to be limited only by the claims and the full scope and equivalents thereof.

Those skilled in the art will appreciate that the above-described embodiments are exemplary and not limiting. The different technical features presented in the different embodiments may be combined to advantage. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in view of the drawings, the description, and the claims. In the claims, the term "comprising" does not exclude other structures; the amounts refer to "a" and do not exclude a plurality; the terms "first," "second," and the like, are used for designating a name and not for indicating any particular order. Any reference signs in the claims shall not be construed as limiting the scope. The presence of certain features in different dependent claims does not imply that these features cannot be combined to advantage.

Claims

1. A pixel circuit, comprising:

the storage module is used for storing the target voltage signal;

in the bias stage before the data writing stage, the first switch module is turned on, and the target voltage signal in the storage module is transmitted to the second end of the driving module through the first switch module.

2. The pixel circuit of claim 1, further comprising a second switching module;

the control end of the second switch module is electrically connected with the first scanning signal line, the first end of the second switch module is electrically connected with the storage module, and the second end of the second switch module is electrically connected with the first reference voltage signal end;

In the bias stage or in a target voltage signal writing stage positioned before the bias stage, the second switch module is conducted under the control of the first scanning signal line, and the target voltage signal provided by the first reference voltage signal terminal is transmitted to the storage module.

3. The pixel circuit according to claim 2, wherein a first end of the memory module is electrically connected to the control end of the driving module, and a second end of the memory module is connected to the first power supply voltage signal end;

the first end of the second switch module is electrically connected with the first end of the storage module and the control end of the driving module;

in an initialization stage after the bias stage, the second switch module is turned on under the control of the first scanning signal line, and transmits a first reference voltage signal provided by the first reference voltage signal end to the control end of the driving module so as to initialize the control end of the driving module;

preferably, the voltage value of the target voltage signal is different from the voltage value of the first reference voltage signal;

preferably, the voltage value of the target voltage signal is greater than the voltage value of the first reference voltage signal.

4. The pixel circuit of claim 1, wherein the control terminal of the drive module is electrically connected to the first terminal of the first switch module, the pixel circuit further comprising a data write module;

the control end of the data writing module is electrically connected with the second scanning signal line, the first end of the data writing module is electrically connected with the data signal end, and the second end of the data writing module is electrically connected with the first end of the driving module;

the control end of the first switch module is electrically connected with a third scanning signal line;

in the data writing stage located after the bias stage, the data writing module is turned on under the control of the second scanning signal line, and the first switch module is turned on under the control of the third scanning signal line to write the data signal of the data signal end into the control end of the driving module.

5. The pixel circuit according to claim 2, wherein a control end of the first switch module is electrically connected to a third scan signal line, and the waveforms of the scan signals output from the first scan signal line and the third scan signal line connected to the same pixel circuit are the same and differ in phase by a predetermined interval;

Preferably, the waveforms and phases of the scanning signals output by the first scanning signal line connected with the pixel circuit of the i-1 row and the third scanning signal line connected with the pixel circuit of the i-1 row are the same;

preferably, the first scanning signal line connected to the pixel circuit of the i-1 th row and the third scanning signal line connected to the pixel circuit of the i-1 th row are all electrically connected to the output end of the same shift register, and i is a positive integer.

6. The pixel circuit according to claim 1, wherein one frame display period includes a refresh frame and a hold frame, the control terminal of the driving module being refreshed at the refresh frame, the control terminal of the driving module not being refreshed at the hold frame;

the refresh frame and the hold frame include the offset phase;

preferably, one picture display period includes 1 refresh frame and N hold frames, N is a positive integer, and the refresh frame and the N hold frames each include the offset stage.

7. The pixel circuit of claim 2, wherein the first and second switch modules each comprise an oxide thin film transistor;

preferably, the first switch module and the second switch module each include an N-type transistor.

8. A driving method of a pixel circuit, characterized by being applied to the pixel circuit according to any one of claims 1 to 7;

the driving method includes:

storing, by a memory module, a target voltage signal during a bias phase or during a target voltage signal writing phase preceding the bias phase;

and in the bias stage before the data writing stage, controlling the first switch module to be conducted so that the target voltage signal in the storage module is transmitted to the second end of the driving module through the first switch module.

9. The method for driving a pixel circuit according to claim 8, wherein the pixel circuit further comprises a second switching module;

the driving method further includes:

and in the bias stage or in a target voltage signal writing stage positioned before the bias stage, outputting the conduction level of the second switch module by controlling a first scanning signal line so as to conduct the second switch module, and transmitting the target voltage signal provided by the first reference voltage signal end to the storage module.

10. A display panel comprising the pixel circuit according to any one of claims 1-7.