CN115547236A

CN115547236A - Display panel, driving method thereof and display device

Info

Publication number: CN115547236A
Application number: CN202211312706.2A
Authority: CN
Inventors: 潘捷苗; 张宇恒
Original assignee: Xiamen Tianma Display Technology Co Ltd
Current assignee: Xiamen Tianma Display Technology Co Ltd
Priority date: 2022-10-25
Filing date: 2022-10-25
Publication date: 2022-12-30

Abstract

The embodiment of the application provides a display panel, a driving method thereof and a display device, wherein the display panel comprises: the display panel comprises at least two brightness levels, the brightness corresponding to the (i + x) th brightness level is different from the brightness corresponding to the (i) th brightness level, and both i and x are positive integers; the display panel comprises a light-emitting element, the light-emitting element emits light under the control of a light-emitting control signal, and the light-emitting control signal comprises at least one pulse within one frame of picture time of the display panel; when the luminance level is i + x, the pulse number of the corresponding light-emitting control signal in one frame of picture time is a first number; at the ith brightness level, the number of pulses of the corresponding light-emitting control signal in one frame time is a second number, and the first number is different from the second number. The embodiment of the application can reduce the number of the bias compensation voltages required by the display panel and reduce the production cost.

Description

Display panel, driving method thereof and display device

Technical Field

The application belongs to the technical field of display, and particularly relates to a display panel, a driving method thereof and a display device.

Background

The display panel is provided with a pixel circuit and a light emitting element. The pixel circuit comprises a driving module, and the driving module is used for driving the light-emitting element to emit light. However, the threshold voltage Vth of the driving module may drift, resulting in low brightness of the first frame. In order to improve the problem of low brightness of the first frame caused by the drift of the threshold voltage Vth of the driving module, an offset compensation voltage can be provided to the driving module to adjust the threshold voltage Vth of the driving module.

However, the inventor of the present application has found that the current display panel needs a plurality of different sets of offset compensation voltages to adjust the threshold voltage Vth of the driving module, which further results in higher requirements for the driving chip and higher production cost.

Disclosure of Invention

The embodiment of the application provides a display panel, a driving method thereof and a display device, which can reduce the number of bias compensation voltages required by the display panel and reduce the production cost.

In a first aspect, an embodiment of the present application provides a display panel, including: the display panel comprises at least two brightness levels, the brightness corresponding to the (i + x) th brightness level is different from the brightness corresponding to the ith brightness level, and both i and x are positive integers; the display panel comprises a light-emitting element, the light-emitting element emits light under the control of a light-emitting control signal, and the light-emitting control signal comprises at least one pulse within one frame of picture time of the display panel; when the number of the pulses of the corresponding light-emitting control signals in one frame of picture time is the first number at the (i + x) th brightness level; at the ith brightness level, the number of pulses of the corresponding light-emitting control signal in one frame time is a second number, and the first number is different from the second number.

In a second aspect, an embodiment of the present application provides a driving method for a display panel, where the display panel includes a pixel circuit and a light emitting element, the pixel circuit includes a driving module, the driving module is configured to drive the light emitting element to emit light, the light emitting element emits light under control of a light emission control signal, and the light emission control signal includes at least one pulse within a frame time of the display panel; the driving method comprises the following steps: the pulse number of the light-emitting control signals corresponding to at least two brightness levels in one frame of picture time is predetermined, and the pulse numbers of the light-emitting control signals corresponding to different brightness levels in one frame of picture time are different; under the condition that the display panel switches the brightness level, determining the pulse number of a corresponding light-emitting control signal of the brightness level to be switched of the display panel in one frame of picture time; providing pulses to the pixel circuit as the corresponding number of light-emitting control signals according to the number of pulses of the corresponding light-emitting control signals within one frame of picture time of the brightness level to be switched of the display panel; and providing the bias compensation voltage signal of the target voltage value to the pixel circuit so as to adjust the bias state of the driving module.

In a third aspect, an embodiment of the present application provides a display device, which includes the display panel provided in the first aspect.

The inventor of the present application has found that the magnitude of the offset compensation voltage at the corresponding brightness level can be changed by adjusting the number of pulses of the emission control signal within one frame of the picture time. In view of this, the display panel, the driving method thereof and the display device according to the embodiments of the present application can adjust the number of pulses of the light emission control signal within one frame of image time at a plurality of brightness levels, so that the corresponding offset compensation voltages at different brightness levels are the same or similar, thereby reducing the number of offset compensation voltages required by the display panel, reducing the requirements on the driving chip, and further reducing the production cost.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a diagram illustrating the Id-Vg curve drift of a driving module in a pixel circuit;

FIG. 2 is a diagram illustrating optimal offset compensation voltages corresponding to the ith and jth luminance levels, respectively;

FIG. 3 is a diagram illustrating the number of pulses of the light-emitting control signal corresponding to the ith luminance level and the (i + x) th luminance level within a frame time;

fig. 4 is a schematic top view of a display panel according to an embodiment of the present disclosure;

FIG. 5 is a timing diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure;

FIG. 6a is a timing diagram of another pixel circuit in a display panel according to an embodiment of the present disclosure;

FIG. 6b is a schematic timing diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure;

fig. 7 is a circuit diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure;

FIG. 8 is a timing diagram of the pixel circuit shown in FIG. 7;

fig. 9 is another circuit diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure;

fig. 10 is a schematic circuit diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure;

fig. 11 is a schematic flowchart of a driving method of a display panel according to an embodiment of the present disclosure;

fig. 12 is a schematic flowchart of S1101 in a driving method of a display panel according to an embodiment of the present application;

fig. 13 is another schematic flow chart of S1101 in the driving method of the display panel according to the embodiment of the present application;

fig. 14 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative only and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

The transistors in the embodiments of the present application may be N-type transistors or P-type transistors. For an N-type transistor, the on level is high and the off level is low. That is, when the gate of the N-type transistor is at a high level, the first pole and the second pole of the N-type transistor are turned on, and when the gate of the N-type transistor is at a low level, the first pole and the second pole of the N-type transistor are turned off. For a P-type transistor, the on level is low and the off level is high. That is, when the control terminal of the P-type transistor is at a low level, the first pole and the second pole of the P-type transistor are turned on, and when the control terminal of the P-type transistor is at a high level, the first pole and the second pole of the P-type transistor are turned off. In a specific implementation, the gate of each transistor is used as its control electrode, and according to the signal of the gate of each transistor and its type, the first electrode of each transistor can be used as its source and the second electrode as its drain, or the first electrode of each transistor can be used as its drain and the second electrode as its source, which are not distinguished herein.

In the embodiments of the present application, the term "electrically connected" may mean that two components are directly electrically connected, or may mean that two components are electrically connected to each other via one or more other components.

In the embodiment of the present application, the first node, the second node, and the third node are defined only for convenience of describing a circuit structure, and the first node, the second node, and the third node are not an actual circuit unit.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application cover the modifications and variations of this application provided they come within the scope of the corresponding claims (the claimed subject matter) and their equivalents. It should be noted that the embodiments provided in the embodiments of the present application can be combined with each other without contradiction.

Before explaining the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically explains the problems existing in the related art:

the inventor of the present application has found that fig. 1 is a schematic diagram of a curve drift of a driving module Id-Vg in a pixel circuit. As shown in fig. 1, in non-offset stages such as a light emitting stage, the pixel circuit may have a situation that the potential of the control terminal (e.g., gate) of the driving module is greater than the potential of the second terminal (e.g., drain) of the driving module, and such arrangement for a long time may cause the polarization of ions inside the driving module, and further a built-in electric field is formed inside the driving module, which causes the threshold voltage Vth of the driving module to increase continuously, and causes the Id-Vg curve to shift, thereby affecting the driving current flowing into the light emitting element, and further affecting the display uniformity. For example, when a black picture is switched to a white picture, the display brightness slowly rises, the brightness tends to be stable only after data refreshing of 4-5 frames, and human eyes can detect picture flicker because the recovery time is long.

In order to solve the problem of low first-frame brightness caused by the drift of the threshold voltage Vth of the driving module, a bias compensation voltage can be provided to the first end or the second end of the driving module, so that the potential of the second end of the driving module is equal to or greater than the potential of the control end of the driving module, the driving module is in an On-bias (OBS) state, the potential difference between the potential of the second end of the driving module and the potential of the control end is further improved, the degree of polarization of ions in the driving module is reduced, the threshold voltage Vth of the driving module is reduced, and the adjustment of the threshold voltage Vth of the driving module is realized.

However, the inventors of the present application have found that the magnitude of the bias compensation voltage is related to the data voltage Vdata, and the optimum bias compensation voltages for different luminance levels are different because the data voltage Vdata does not match each other.

Fig. 2 is a schematic diagram of optimal bias compensation voltages corresponding to the ith luminance level and the jth luminance level respectively. The abscissa of fig. 2 represents the voltage value. As shown in fig. 2, the optimum offset compensation voltage for the ith luminance level (e.g., 10 nit) is about 5.75V, the optimum offset compensation voltage for the jth luminance level (e.g., 50 nit) is about 5.9V, the optimum offset compensation voltage for the kth luminance level (e.g., 100 nit) is about 6.0V, and i, j, and k are positive integers. Therefore, since the optimal offset compensation voltages corresponding to different brightness levels may be different, the display panel needs a plurality of sets of different offset compensation voltages to adjust the threshold voltage Vth of the driving module under different brightness levels, which further results in higher requirements for the driving chip and higher production cost.

In view of the above research of the inventor, the embodiments of the present application provide a display panel, a driving method thereof, and a display device, which can solve the technical problems that the display panel in the related art needs a plurality of different sets of offset compensation voltages to adjust the threshold voltage Vth of the driving module, the requirement for the driving chip is high, and the production cost is high.

The inventor of the present application has found that the magnitude of the offset compensation voltage at the corresponding brightness level can be changed by adjusting the number of pulses of the emission control signal within one frame of the picture time. In view of this, the technical idea of the embodiments of the present application is: by adjusting the pulse number of the light-emitting control signal in one frame of picture time under a plurality of brightness levels, the corresponding bias compensation voltages under different brightness levels can be the same or similar, so that the number of the bias compensation voltages required by the display panel is reduced, the requirements on a driving chip are reduced, and the production cost is further reduced.

The following first describes a display panel provided in an embodiment of the present application.

In the embodiment of the present application, the display panel may include at least two brightness levels. Wherein the different brightness levels may be different brightness points, such as 5nit for one brightness level and 6nit for another brightness level. Alternatively, the different brightness levels may be different brightness segments, such as 0-10 nit for one brightness level and 11-20 nit for another brightness level. For any two brightness levels of the at least two brightness levels, namely the ith brightness level and the (i + x) th brightness level, the brightness corresponding to the (i + x) th brightness level is different from the brightness corresponding to the ith brightness level, and both i and x are positive integers.

The display panel includes a light emitting element. Illustratively, the Light Emitting element includes, but is not limited to, an Organic Light-Emitting Diode (OLED). The light emitting element emits light under the control of the light emitting control signal, and the light emitting control signal includes at least one pulse within one frame of the display panel.

At the i + x-th brightness level, the number of pulses of the corresponding light-emitting control signal in one frame time is the first number. At the ith brightness level, the number of pulses of the corresponding light-emitting control signal in one frame time is a second number, and the first number is different from the second number.

Fig. 3 is a schematic diagram illustrating the number of pulses of the light-emitting control signal corresponding to the ith luminance level and the (i + x) th luminance level within one frame time. As shown in fig. 3, the pulse in the emission control signal EMIT may be a pulse m corresponding to an off level (e.g., a high level). In some examples, at the i + x-th brightness level a, the number of pulses (i.e., the first number) of the corresponding light emission control signal EMIT within one frame picture time H is, for example, 1. At the i-th brightness level b, the number of pulses (i.e., the second number) of the corresponding emission control signal EMIT within, for example, one frame time H is, for example, 3. It should be noted that the numbers 1 and 3 are only used as an example and do not limit the embodiments of the present application, and the first number may be other than 1, and the second number may be other than 3.

In some specific examples, for example, the number of pulses of the light emission control signal corresponding to the i + x-th brightness level within one frame time may be adjusted based on the i-th brightness level, so that the i-th brightness level is the same as or close to the optimal bias compensation voltage corresponding to the i + x-th brightness level.

In other specific examples, for example, the number of pulses of the light emission control signal corresponding to the ith luminance level in one frame time may be adjusted based on the (i + x) th luminance level, so that the optimal bias compensation voltage corresponding to the (i + x) th luminance level is the same as or similar to the optimal bias compensation voltage corresponding to the (i + x) th luminance level.

In some specific examples, for example, the number of pulses of the light-emitting control signal within one frame time corresponding to the ith brightness level and the number of pulses of the light-emitting control signal within one frame time corresponding to the (i + x) th brightness level may be adjusted, so that the optimal offset compensation voltage corresponding to the (i) th brightness level and the optimal offset compensation voltage corresponding to the (i + x) th brightness level are the same or similar.

The display panel provided by the embodiment of the application can enable the corresponding bias compensation voltages to be the same or similar under different brightness levels by adjusting the pulse number of the light-emitting control signals in one frame of picture time under different brightness levels, thereby reducing the number of the bias compensation voltages required by the display panel, reducing the requirements on the driving chip and further reducing the production cost.

For example, the display panel includes 3 brightness levels, and the optimal bias compensation voltages for the 3 brightness levels are different. By adjusting the pulse number of the light-emitting control signal in one frame of picture time under at least one brightness level, the optimal bias compensation voltage corresponding to at least two brightness levels can be the same. That is, the number of offset compensation voltages required for the display panel is reduced from 3 to 2 or 1.

Fig. 4 is a schematic top view of a display panel according to an embodiment of the present disclosure. As shown in fig. 4, the display panel may optionally include a pixel circuit 40 according to some embodiments of the present application. Illustratively, the pixel circuit 40 includes, but is not limited to, a 7T1C pixel circuit, a 7T2C pixel circuit, an 8T1C pixel circuit, a 9T1C pixel circuit, or other types of pixel circuits. The 7T1C pixel circuit, that is, the pixel circuit, includes 7 Thin Film Transistors (TFTs) and 1 storage capacitor, and the 7T1C pixel circuit, that is, the pixel circuit, includes 7 TFTs and 2 storage capacitors, and so on, and is not described again.

The pixel circuit 40 may include a driving module (not shown in the figure), and the driving module may be used to drive the light emitting element D to emit light. Optionally, the ith brightness level and the (i + x) th brightness level may both adjust the bias state of the driving module based on the bias compensation voltage of the same voltage value. That is, by adjusting the number of pulses of the light emission control signal corresponding to the ith luminance level and/or the (i + x) th luminance level within one frame time, the optimal offset compensation voltage corresponding to the ith luminance level and the (i + x) th luminance level can be the same or similar, and further, the bias state of the driving module can be adjusted by the offset compensation voltage based on the same voltage value for both the ith luminance level and the (i + x) th luminance level.

Therefore, the optimal bias compensation voltages corresponding to different brightness levels can be the same or similar through the pulse number of the light-emitting control signal in one frame of picture time under different brightness levels. In this way, only one bias compensation voltage is required to optimize the adjustment of the bias state of the driver module at a plurality of different brightness levels. Meanwhile, the adjustment requirement of the display panel can be met only by using the driving chip capable of outputting one bias compensation voltage, and the driving chip with higher use cost is not needed, so that the production cost is reduced.

The inventor of the present application further studies and finds that, for some luminance levels with lower luminance (hereinafter, referred to as low luminance levels), by increasing the number of pulses of the light emission control signal within one frame of the image time at the low luminance levels, the optimal bias compensation voltage corresponding to the low luminance levels can be appropriately increased.

In view of the above, the present application recognizes that in order to achieve the same or similar optimum offset compensation voltage for the low luminance level and the optimum offset compensation voltage for the high luminance level, the number of pulses of the emission control signal in one frame time at the low luminance level needs to be greater than the number of pulses of the emission control signal in one frame time at the high luminance level.

Specifically, according to some embodiments of the present application, optionally, the luminance corresponding to the i + x-th luminance level is greater than the luminance corresponding to the i-th luminance level, and the first number is smaller than the second number. That is, the brighter the brightness corresponding to the brightness level is, the smaller the number of pulses of the light emission control signal in one frame of picture time is; the darker the brightness corresponding to the brightness level, the larger the number of pulses of the light-emitting control signal in one frame of picture time, so that the optimal bias compensation voltages corresponding to different brightness levels are the same or similar, thereby reducing the number of bias compensation voltages required by the display panel, reducing the requirements on the driving chip, and further reducing the production cost.

Fig. 5 is a timing diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure. As shown in fig. 5, in order to reduce power consumption, when the display panel is displayed at a low refresh rate, one frame H of the display panel may include a data write frame H1 or a hold frame H2. It should be noted that one frame refresh period Hm of the display panel may include 1 data write frame h1 and n hold frames h2, where n ≧ 1 and is an integer. Although fig. 5 is illustrated with n =1, it is understood that n may be greater than 1. And refreshing the potential of the control terminal of the driving module in the data writing frame h1, such as initializing and writing a data signal by the control terminal of the driving module. The potential of the control terminal of the driving module in the frame h2 is kept not to be refreshed, thereby reducing power consumption.

According to some embodiments of the present application, alternatively, the number of pulses of the light emission control signal corresponding to the data write frame and the hold frame may be the same at any one luminance level. For example, at the i + x-th brightness level, the number of pulses of the light emission control signal corresponding to the data write frame and the hold frame may each be the first number. For example, at the ith luminance level, the number of pulses of the light emission control signal corresponding to the data write frame and the hold frame may be each the second number. For example, as shown in fig. 5, for example, at a certain brightness level, the number of pulses of the light emission control signal corresponding to the data write frame and the hold frame is 3.

Therefore, the pulse number of the light-emitting control signals corresponding to the data writing frame and the holding frame is the same, and the display effect consistency of the data writing frame and the holding frame can be ensured. In addition, the pulse of the light-emitting control signal can be uniformly distributed, and the brightness jump can be prevented.

According to some embodiments of the application, optionally, the luminance corresponding to the i + y th luminance level is between the luminance corresponding to the i + x th luminance level and the luminance corresponding to the i + x th luminance level, and 0 < y < x. For example, the luminance corresponding to the i-th luminance level < the luminance corresponding to the i + y-th luminance level < the luminance corresponding to the i + x-th luminance level.

In some specific embodiments, at the i + y-th brightness level, the numbers of pulses of the light emission control signals corresponding to the data write frame and the hold frame are all the third numbers, and the third numbers may be different from the first numbers and the second numbers. For example, the first number < the third number < the second number.

In this way, by adjusting the pulse number of the light emission control signal in one frame time at the ith brightness level, the (i + y) th brightness level and the (i + x) th brightness level to be different, the bias compensation voltages corresponding to the (i + x) th brightness level and the (i + y) th brightness level can be the same or similar, thereby reducing the number of bias compensation voltages required by the display panel.

Fig. 6a is another timing diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure. In other specific embodiments, as shown in fig. 6a, at the i + x-th brightness level a, the width of one pulse of the emission control signal EMIT corresponding to the data write frame h1 and the hold frame h2 is the first width w1. At the ith luminance level b, the width of one pulse of the light emission control signal EMIT corresponding to the data write frame h1 and the hold frame h2 is the second width w2. At the i + y-th luminance level c, the number of pulses of the light emission control signal EMIT corresponding to the data write frame h1 and the holding frame h2 may each be the first number, a width of one pulse of the light emission control signal EMIT corresponding to the data write frame h1 and the holding frame h2 is the third width w3, and the third width w3 may be greater than the first width w1.

That is, in some embodiments, the number of pulses of the light emission control signal corresponding to the i + y th luminance level c and the i + x th luminance level a may be the same, but the width of one pulse of the light emission control signal EMIT corresponding to the i + y th luminance level c is greater than the width of one pulse of the light emission control signal EMIT corresponding to the i + x th luminance level a. That is, by adjusting the pulse width or the duty ratio of the emission control signal EMIT, the magnitude of the bias compensation voltage at the corresponding luminance level can be also appropriately changed. In this way, by making the pulse numbers of the light emission control signals corresponding to the i + y th luminance level c and the i + x th luminance level a the same, but making the pulse widths of the two different, the optimal offset compensation voltages corresponding to the i + y th luminance level c and the i + x th luminance level a can be made the same or similar, thereby reducing the number of offset compensation voltages required by the display panel.

Fig. 6b is a timing diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure. As shown in fig. 6b, unlike the embodiment shown in fig. 6a, in further specific embodiments, at the i + y-th brightness level c, the number of pulses of the emission control signal EMIT corresponding to the data write frame h1 and the hold frame h2 may each be the second number, one pulse of the emission control signal EMIT corresponding to the data write frame h1 and the hold frame h2 may have a third width w3, and the third width w3 may be smaller than the second width w2.

That is, in some embodiments, the number of pulses of the light emission control signal corresponding to the i + y-th luminance level c and the i-th luminance level b may be the same, but the width of one pulse of the light emission control signal EMIT corresponding to the i + y-th luminance level c is smaller than the width of one pulse of the light emission control signal EMIT corresponding to the i-th luminance level b. That is, by adjusting the pulse width or the duty ratio of the emission control signal EMIT, the magnitude of the bias compensation voltage at the corresponding luminance level can be also appropriately changed. In this way, by making the pulse numbers of the light emission control signals corresponding to the i + y-th luminance level c and the i-th luminance level b the same, but making the pulse widths of the two different, the optimal offset compensation voltages corresponding to the i + y-th luminance level c and the i-th luminance level b can be made the same or similar, thereby reducing the number of offset compensation voltages required by the display panel.

For the sake of understanding, the following detailed description is made on the compensation process of the offset compensation voltage in conjunction with some specific application embodiments.

Fig. 7 is a circuit diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure. As shown in fig. 7, according to some embodiments of the present application, optionally, the pixel circuit 40 may include an offset compensation module 701, a control terminal of the offset compensation module 701 is electrically connected to the first scan signal terminal S1, a first terminal of the offset compensation module 701 is electrically connected to the offset compensation voltage signal terminal VH, and a second terminal of the offset compensation module 701 is electrically connected to the first terminal or the second terminal of the driving module 702. The bias compensation module 701 may be configured to provide a bias compensation voltage signal to a first terminal or a second terminal of the driving module 702, and the bias compensation voltage signal is used to adjust a bias state of the driving module 702. Specifically, after the offset compensation voltage signal is transmitted to the second terminal of the driving module 702, the potential of the second terminal of the driving module 702 may be equal to or greater than the potential of the control terminal of the driving module 702, so that the driving module 702 is in an offset state, and the threshold voltage Vth of the driving module 702 is adjusted.

It should be noted that, although fig. 7 illustrates an example that the second end of the offset compensation module 701 is electrically connected to the second end (i.e., the end b in fig. 7) of the driving module 702, in other embodiments, the second end of the offset compensation module 701 may also be electrically connected to the first end (i.e., the end a in fig. 7) of the driving module 702, which is not limited in this embodiment of the application.

The offset compensation module 701 may provide the offset compensation voltage signal having the same voltage value to the first terminal or the second terminal of the driving module 702 at the ith luminance level or the (i + x) th luminance level. For example, at the ith brightness level or the (i + x) th brightness level, the bias compensation module 701 may provide a bias compensation voltage signal having a voltage value of 6V to the first terminal or the second terminal of the driving module 702.

Therefore, the optimal bias compensation voltages corresponding to different brightness levels can be the same or similar through the pulse number of the light-emitting control signal in one frame of picture time under different brightness levels. Thus, the bias compensation module 701 can meet the optimization of the bias state adjustment of the driving modules under a plurality of different brightness levels only by using the same bias compensation voltage, reduce the number of the bias compensation voltages required by the display panel, reduce the requirements on the driving chip and further reduce the production cost.

FIG. 8 is a timing diagram of the pixel circuit shown in FIG. 7. As shown in fig. 7 and 8, according to some embodiments of the present application, optionally, the offset compensation module 701 is turned on in response to the turn-on level of the first scan signal terminal S1 at the time of the holding frame h2 of the ith luminance level or the holding frame h2 of the (i + x) th luminance level, and transmits the offset compensation voltage signal of the offset compensation voltage signal terminal VH to the first terminal or the second terminal of the driving module 702.

In some embodiments, the driving module is in a bias state because the driving module writes the data signal in the data writing frame, so as to adjust the threshold voltage of the driving module; and the drive module in the retention frame is not written with the data signal, so that the drive module is not in a bias state, the threshold voltage of the drive module cannot be adjusted, further, the threshold voltage of the drive module in the data writing frame and the threshold voltage of the drive module in the retention frame have deviation, and the display effect of the data writing frame and the display effect of the retention frame are inconsistent.

And by writing the bias compensation voltage signal in the frame keeping process, the driving module in the frame keeping process can be in a bias state, so that the threshold voltage of the driving module is adjusted, the threshold voltage of the driving module in the data writing frame is the same as or similar to the threshold voltage of the driving module in the frame keeping process, and the display effect of the data writing frame is the same as or similar to that of the frame keeping process.

Fig. 9 is another circuit schematic diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure. As shown in fig. 9, according to some embodiments of the present application, the bias compensation module 701 may optionally include a first transistor T1, and the driving module 702 may further include a second transistor T2. The gate of the first transistor T1 is electrically connected to the first scan signal terminal S1, the first pole of the first transistor T1 is electrically connected to the bias compensation voltage signal terminal VH, and the second pole of the first transistor T1 is electrically connected to the first pole or the second pole of the second transistor T2. Illustratively, the first pole of the second transistor T2 may be a source of the second transistor T2, and the second pole of the second transistor T2 may be a drain of the second transistor T2. The first transistor T1 may be used to transmit the bias compensation voltage signal of the bias compensation voltage signal terminal VH to the first pole or the second pole of the second transistor T2. When the bias compensation voltage signal of the bias compensation voltage signal terminal VH is transmitted to the first pole of the second transistor T2, the second transistor T2 is in a conducting state, so the bias compensation voltage signal can be transmitted to the second pole of the second transistor T2 through the conducting second transistor T2, so that the second pole potential of the second transistor T2 is higher than the gate potential of the second transistor T2.

With continuing reference to fig. 9, according to some embodiments of the present application, optionally, the pixel circuit 40 may further include: a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a storage capacitor Cst. The gate of the second transistor T2 is electrically connected to the first node N1, the first pole of the second transistor T2 is electrically connected to the second node N2, and the second pole of the second transistor T2 is electrically connected to the third node N3.

A gate electrode of the third transistor T3 is electrically connected to the second scan signal terminal S2, a first pole of the third transistor T3 is electrically connected to the data signal terminal data, and a second pole of the third transistor T3 is electrically connected to the second node N2. Referring to fig. 5, in the data writing phase T2, the third transistor T3 is turned on in response to the on level of the second scan signal terminal S2 for transmitting the data signal of the data signal terminal data to the second node N2.

A gate of the fourth transistor T4 is electrically connected to the third scan signal terminal S3, a first pole of the fourth transistor T4 is electrically connected to the first node N1, and a second pole of the fourth transistor T4 is electrically connected to the third node N3. As shown in fig. 5, in the data writing phase T2, the fourth transistor T4 is turned on in response to the turn-on level of the third scan signal terminal S3 for connecting the second pole of the second transistor T2 and the gate of the second transistor T2, so as to implement the threshold voltage compensation of the second transistor T2. The fourth transistor T4 is illustrated as an N-type transistor.

A gate of the fifth transistor T5 is electrically connected to the fourth scan signal terminal S4, a first pole of the fifth transistor T5 is electrically connected to the first reference voltage signal terminal vref1, and a second pole of the fifth transistor T5 is electrically connected to the first node N1. As shown in fig. 5, in the initialization period T1, the fifth transistor T5 is turned on in response to the turn-on level of the fourth scan signal terminal S4 for transmitting the first reference voltage signal of the first reference voltage signal terminal vref1 to the first node N1 to initialize the first node N1. The fifth transistor T5 is illustrated as an N-type transistor.

A gate of the sixth transistor T6 is electrically connected to the fifth scan signal terminal S5, a first electrode of the sixth transistor T6 is electrically connected to the second reference voltage signal terminal vref2, and a second electrode of the sixth transistor T6 is electrically connected to the first electrode of the light emitting element D. The first electrode of the light emitting element D may be an anode, and the second electrode of the light emitting element D may be a cathode. As shown in fig. 5, in the data writing period T2, the sixth transistor T6 is turned on in response to the turn-on level of the fifth scan signal terminal S5 for transmitting the second reference voltage signal of the second reference voltage signal terminal vref2 to the first electrode of the light emitting element D to initialize the first electrode of the light emitting element D.

In some embodiments, optionally, the second scan signal terminal S2 and the fifth scan signal terminal S5 can be multiplexed, so as to reduce the number of traces in the display panel.

A gate electrode of the seventh transistor T7 is electrically connected to the emission control signal line EM, a first electrode of the seventh transistor T7 is electrically connected to the first power voltage signal terminal PVDD, and a second electrode of the seventh transistor T7 is electrically connected to the second node N2.

A gate of the eighth transistor T8 is electrically connected to the emission control signal line EM, a first electrode of the eighth transistor T8 is electrically connected to the third node N3, and a second electrode of the eighth transistor T8 is electrically connected to the first electrode of the light emitting element D. As shown in connection with fig. 5, in the light emitting period T3, the seventh transistor T7 and the eighth transistor T8 are turned on in response to the on level of the light emission control signal line EM, and the light emitting element D emits light.

A first plate of the storage capacitor Cst is electrically connected to the first power voltage signal terminal PVDD, and a second plate of the storage capacitor Cst is electrically connected to the first node N1, for maintaining a potential of the first node N1.

Fig. 10 is a circuit diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure. As shown in fig. 10, according to other embodiments of the present application, optionally, the pixel circuit 40 may include a data writing module 1001, a control terminal of the data writing module 1001 is electrically connected to the second scan signal terminal S2, a first terminal of the data writing module 1001 is electrically connected to the data signal terminal data, and a second terminal of the data writing module 1001 is electrically connected to the first terminal or the second terminal of the driving module 702. The data writing module 1001 is configured to write a data signal of the data signal terminal data into the first terminal or the second terminal of the driving module 702 in a data writing frame.

Alternatively, in the embodiment shown in fig. 10, the offset compensation module 701 may multiplex the data writing module 1001, the first scan signal terminal S1 may multiplex the second scan signal terminal S2, and the offset compensation voltage signal terminal VH may multiplex the data signal terminal data. The data writing module 1001 is further configured to provide a bias compensation voltage signal to the first terminal or the second terminal of the driving module 702 during the sustain frame. That is, the data write module 1001 writes not only the data signal but also the offset compensation voltage signal in the data write frame.

In this way, the offset compensation voltage signal is written in the retention frame by the multiplexed data writing module 1001, so that the number of transistors and wires in the display panel can be reduced while the threshold voltage of the driving module in the retention frame is adjusted, the wiring space can be saved, and the production cost can be reduced.

With continued reference to fig. 10, the driving module 702 may optionally further include a second transistor T2 according to some embodiments of the present application. A gate of the second transistor T2 is electrically connected to the first node N1, a first pole of the second transistor T2 is electrically connected to the second node N2, and a second pole of the second transistor T2 is electrically connected to the third node N3. The data writing module 1001 may include a third transistor T3, a gate of the third transistor T3 is electrically connected to the second scan signal terminal S2, a first pole of the third transistor T3 is electrically connected to the data signal terminal data, and a second pole of the third transistor T3 is electrically connected to the second node N2. In a data writing stage of a data writing frame, the third transistor T3 is turned on in response to the turn-on level of the second scan signal terminal S2 for transmitting the data signal of the data signal terminal data to the second node N2. In the hold frame, the third transistor T3 is turned on in response to the turn-on level of the second scan signal terminal S2 for transmitting the bias compensation voltage signal of the data signal terminal data to the second node N2.

The pixel circuit 40 may further include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a storage capacitor Cst. The connection relationship and the operation process of the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the storage capacitor Cst in fig. 10 are the same as those in fig. 9, and are not repeated herein.

According to some embodiments of the present application, optionally, the present application considers that the minimum value of the number of pulses of the corresponding light emission control signal within one frame picture time is 1. Therefore, when the number of pulses of the corresponding light emission control signal within one frame time is 1, the number of pulses of the light emission control signal cannot be reduced any more. Therefore, in some embodiments, the luminance level corresponding to the luminance control signal having the number of pulses of 1 in one frame of picture time may be used as the target luminance level, and the number of pulses of the luminance control signal corresponding to the luminance levels other than the target luminance level in one frame of picture time may be adjusted, so that the optimal bias compensation voltages corresponding to the luminance levels are the same.

Specifically, the display panel may use a voltage value of the offset compensation voltage corresponding to the target luminance level as the reference voltage value. The number of pulses of the corresponding light-emitting control signal of the target brightness level in one frame of picture time is equal to 1. And adjusting the pulse number of the corresponding light-emitting control signals of the other brightness levels except the target brightness level in one frame of picture time so as to enable the voltage values of the bias compensation voltages corresponding to the other brightness levels to be equal to the reference voltage value.

In this way, by adjusting the number of pulses of the light-emitting control signal corresponding to the brightness levels other than the target brightness level within one frame time, the optimal bias compensation voltages corresponding to the brightness levels other than the target brightness level can be the same as the optimal bias compensation voltage corresponding to the target brightness level, thereby ensuring that all the brightness levels can be compensated based on the bias compensation voltage with the same voltage value.

In some particular embodiments, the display panel may include a plurality of brightness levels, such as including but not limited to brightness level a, brightness level B, and brightness level C. For example, the brightness corresponding to the brightness level a is 110nit, and the number of pulses of the light-emitting control signal corresponding to the brightness level a in one frame time is 1; the brightness corresponding to the brightness level B is 50nit, and the pulse number of the light-emitting control signal corresponding to the brightness level B in one frame of picture time is 3; the luminance level C corresponds to a luminance of 1nit, and the number of pulses of the light emission control signal corresponding to the luminance level C in one frame time is 16. By adjusting the number of pulses of the light emission control signal corresponding to the luminance level a, the luminance level B, and/or the luminance level C in one frame time, the adjusted luminance level a, the adjusted luminance level B, and the adjusted luminance level C can be compensated based on, for example, a bias compensation voltage having a voltage value of 6V.

Based on the display panel provided by the above embodiment, correspondingly, the embodiment of the application further provides a driving method of the display panel. Please see the examples below.

In an embodiment of the present application, a display panel includes a pixel circuit and a light emitting element, the pixel circuit includes a driving module, and the driving module is configured to drive the light emitting element to emit light. The light emitting element emits light under the control of the light emitting control signal, and the light emitting control signal includes at least one pulse within one frame of picture time of the display panel.

Fig. 11 is a flowchart illustrating a driving method of a display panel according to an embodiment of the present disclosure. As shown in fig. 11, the driving method of the display panel provided by the embodiment of the present application may include the following steps S1101 to S1104.

S1101, determining the number of pulses of the light emission control signal corresponding to at least two luminance levels within one frame of picture time in advance, wherein the number of pulses of the light emission control signal corresponding to different luminance levels within one frame of picture time is different.

Assuming that the display panel includes N luminance levels, in S1101, the number of pulses of the light emission control signal corresponding to each of the N luminance levels in one frame time may be determined, where N is a positive integer.

And S1102, under the condition that the display panel switches the brightness level, determining the pulse number of the corresponding light-emitting control signal of the brightness level to be switched of the display panel in one frame of picture time.

The number of pulses of the light emission control signal corresponding to each of the plurality of luminance levels within one frame time has been previously determined. Then, the number of pulses of the light emission control signal corresponding to the luminance level to be switched within one frame time can be inquired.

S1103, providing the pixel circuit with pulses as the corresponding number of light-emitting control signals according to the number of pulses of the corresponding light-emitting control signals within one frame of picture time of the brightness level to be switched of the display panel.

And S1104, providing the bias compensation voltage signal of the target voltage value to the pixel circuit so as to adjust the bias state of the driving module.

The target voltage value can be predetermined, and the N brightness levels can adjust the bias state of the driving module based on the bias compensation voltage signals of M voltage values, wherein M is more than or equal to 1 and less than N.

According to the driving method of the display panel, the number of the pulses of the light-emitting control signals in one frame of picture time under different brightness levels is adjusted, so that the corresponding bias compensation voltages under different brightness levels are the same or similar, the number of the bias compensation voltages required by the display panel is reduced, the requirements for the driving chip are reduced, and further the production cost is reduced.

According to some embodiments of the present application, optionally, the display panel may include at least two brightness levels, where the brightness corresponding to the (i + x) th brightness level is greater than the brightness corresponding to the (i) th brightness level, and both i and x are positive integers. When the luminance level is i + x, the pulse number of the corresponding light-emitting control signal in one frame of picture time is a first number; at the ith brightness level, the number of pulses of the corresponding light-emitting control signal in one frame of picture time is a second number, and the first number is smaller than the second number. And the ith brightness level and the (i + x) th brightness level adjust the bias state of the driving module based on the bias compensation voltage with the same voltage value.

Fig. 12 is a schematic flowchart of S1101 in a driving method of a display panel according to an embodiment of the present application. As shown in fig. 12, according to some embodiments of the present application, optionally, S1101, predetermining the number of pulses of the light-emitting control signal corresponding to at least two brightness levels in one frame of picture time, may specifically include the following steps:

s1201, regarding the brightness level of which the pulse number of the corresponding light-emitting control signal is 1 in one frame of picture time as a target brightness level, and regarding the voltage value of the bias compensation voltage corresponding to the target brightness level as a reference voltage value;

s1202, adjusting the pulse number of the light-emitting control signals corresponding to the other brightness levels except the target brightness level in one frame of picture time to enable the voltage values of the bias compensation voltages corresponding to the other brightness levels to be equal to the reference voltage value;

and S1203, recording the number of pulses of the corresponding light-emitting control signals when the voltage values of the bias compensation voltages corresponding to other brightness levels are equal to the reference voltage value.

In this way, by adjusting the number of pulses of the light-emitting control signal corresponding to the brightness levels other than the target brightness level within one frame time, the optimal bias compensation voltages corresponding to the brightness levels other than the target brightness level can be the same as the optimal bias compensation voltage corresponding to the target brightness level, thereby ensuring that all the brightness levels can be compensated based on the bias compensation voltage of the same voltage value.

Fig. 13 is another schematic flow chart of S1101 in the driving method of the display panel according to the embodiment of the present application. As shown in fig. 13, according to another embodiment of the present application, optionally, S1101 may determine in advance the number of pulses of the light-emitting control signal corresponding to at least two luminance levels in one frame of picture time, and specifically may include the following steps S1301 to S1303.

And S1301, setting a reference voltage value according to the voltage output capability of the driving chip.

Specifically, the reference voltage value can be flexibly set according to the voltage output capability or the voltage output range of the driving chip. For example, the driver chip can only output a bias compensation voltage signal of 6V, and then 6V is set as the reference voltage value. For example, the driver chip can output the offset compensation voltage signal of a plurality of voltage values, and then one voltage value can be selected from the plurality of voltage values as the reference voltage value.

S1302, for any jth brightness level, adjusting the pulse number of the light emitting control signal corresponding to the jth brightness level in a frame time, so that the voltage value of the bias compensation voltage corresponding to the jth brightness level is equal to the reference voltage value, where j is a positive integer.

And S1303, recording the pulse number of the corresponding light-emitting control signal when the voltage value of the bias compensation voltage corresponding to the jth brightness level is equal to the reference voltage value.

Therefore, the reference voltage value is flexibly set according to the voltage output capability or the voltage output range of the driving chip, and the pulse number of the light-emitting control signal corresponding to each brightness grade in one frame of picture time is adjusted by taking the reference voltage value as a reference, so that all the brightness grades can be compensated based on the bias compensation voltage with the same voltage value.

It should be noted that specific processes of each step in the method embodiment may refer to the description part in the product embodiment, and both can achieve the same or corresponding technical effects, and for brevity, no further description is provided here.

Based on the display panel that above-mentioned embodiment provided, correspondingly, this application still provides a display device, includes the display panel that this application provided. Referring to fig. 14, fig. 14 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. Fig. 14 provides a display device 1100 including a display panel according to any of the embodiments described above in the present application. The display device 1100 is described in the embodiment of fig. 14, for example, taking a mobile phone as an example, it is understood that the display device provided in the embodiment of the present application may be other display devices having a display function, such as a wearable product, a computer, a television, and a vehicle-mounted display device, and the present application is not limited thereto. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application, and specific reference may be specifically made to the specific description of the display panel in each of the above embodiments, which is not repeated herein.

It should be understood that the specific structures of the circuits and the cross-sectional structures of the display panels provided in the drawings of the embodiments of the present application are only examples, and are not intended to limit the present application. In addition, the above embodiments provided by the present application may be combined with each other without contradiction.

It should be clear that the embodiments in this specification are described in a progressive manner, and the same or similar parts between the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In accordance with the embodiments of the present application as described above, these embodiments are not exhaustive and do not limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated. The application is limited only by the claims and their full scope and equivalents.

It will be appreciated by persons skilled in the art that the above embodiments are illustrative and not restrictive. Different features which are present in different embodiments may be combined to advantage. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art upon studying the drawings, the specification, and the claims. In the claims, the term "comprising" does not exclude other structures; the quantities relate to "a" and "an" but do not exclude a plurality; the terms "first" and "second" are used to denote a name and not to denote any particular order. Any reference signs in the claims shall not be construed as limiting the scope. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A display panel is characterized in that the display panel comprises at least two brightness levels, the brightness corresponding to the (i + x) th brightness level is different from the brightness corresponding to the ith brightness level, and both i and x are positive integers;

the display panel comprises a light-emitting element, the light-emitting element emits light under the control of a light-emitting control signal, and the light-emitting control signal comprises at least one pulse within one frame of picture time of the display panel;

when the luminance level is at the (i + x) th luminance level, the pulse number of the corresponding light-emitting control signal in the frame time is a first number; and at the ith brightness level, the number of pulses of the corresponding light-emitting control signal in the one-frame picture time is a second number, and the first number is different from the second number.

2. The display panel according to claim 1,

the display panel comprises a pixel circuit, the pixel circuit comprises a driving module, the driving module is used for driving the light-emitting element to emit light, and the ith brightness grade and the (i + x) th brightness grade adjust the bias state of the driving module based on the bias compensation voltage with the same voltage value.

3. The display panel according to claim 1, wherein the luminance corresponding to the i + x-th luminance level is greater than the luminance corresponding to the i-th luminance level, and wherein the first number is smaller than the second number.

4. The display panel according to claim 1, wherein one frame of the display panel includes a data write frame in which a potential of the control terminal of the driving module is refreshed or a hold frame in which a potential of the control terminal of the driving module is not refreshed;

at the i + x th brightness level, the pulse numbers of the light emission control signals corresponding to the data write frame and the hold frame are both the first number;

at the ith brightness level, the numbers of pulses of the light emission control signals corresponding to the data write frame and the hold frame are both the second number.

5. The display panel according to claim 4, wherein the luminance corresponding to the i + y th luminance level is between the luminance corresponding to the i + x th luminance level and the luminance corresponding to the i + x th luminance level, and 0 < y < x;

at the i + x th brightness level, the width of one pulse of the light emission control signal corresponding to the data write frame and the hold frame is a first width;

at the ith brightness level, the width of one pulse of the light emission control signal corresponding to the data write frame and the hold frame is a second width;

at the i + y th brightness level, the numbers of pulses of the light emission control signals corresponding to the data write frame and the holding frame are both a third number, which is different from the first number and the second number; alternatively, the first and second electrodes may be,

at the i + y-th brightness level, the pulse numbers of the light emission control signals corresponding to the data write frame and the hold frame are both the first number, the width of one pulse of the light emission control signal corresponding to the data write frame and the hold frame is a third width, and the third width is greater than the first width; alternatively, the first and second electrodes may be,

at the i + y-th brightness level, the numbers of pulses of the light emission control signals corresponding to the data write frame and the hold frame are both the second number, the width of one of the pulses of the light emission control signals corresponding to the data write frame and the hold frame is a third width, and the third width is smaller than the second width.

6. The display panel according to claim 1, wherein the pixel circuit comprises:

the control end of the bias compensation module is electrically connected with a first scanning signal end, the first end of the bias compensation module is electrically connected with a bias compensation voltage signal end, the second end of the bias compensation module is electrically connected with the first end or the second end of the driving module, the bias compensation module is used for providing a bias compensation voltage signal to the first end or the second end of the driving module, and the bias compensation voltage signal is used for adjusting the bias state of the driving module;

and when the ith brightness level or the (i + x) th brightness level is reached, the bias compensation module provides the bias compensation voltage signal with the same voltage value to the first end or the second end of the driving module.

7. The display panel according to claim 6, wherein one frame of the display panel includes a data write frame in which the potential of the control terminal of the driving module is refreshed or a hold frame in which the potential of the control terminal of the driving module is not refreshed;

and when the holding frame of the ith brightness level or the holding frame of the (i + x) th brightness level, the bias compensation module provides the bias compensation voltage signal with the same voltage value to the first end or the second end of the driving module.

8. The display panel according to claim 7, wherein the pixel circuit comprises:

the control end of the data writing module is electrically connected with the second scanning signal end, the first end of the data writing module is electrically connected with the data signal end, the second end of the data writing module is electrically connected with the first end or the second end of the driving module, and the data writing module is used for writing the data signal of the data signal end into the first end or the second end of the driving module in the data writing frame;

the bias compensation module multiplexes the data writing module, the first scanning signal terminal multiplexes the second scanning signal terminal, and the bias compensation voltage signal terminal multiplexes the data signal terminal;

the data writing module is further used for providing the bias compensation voltage signal to the first end or the second end of the driving module in the holding frame.

9. The display panel according to claim 1, wherein the display panel adjusts the number of pulses of the emission control signal corresponding to the luminance levels other than the target luminance level in the one frame time with the voltage value of the offset compensation voltage corresponding to the target luminance level as a reference voltage value so that the voltage values of the offset compensation voltages corresponding to the other luminance levels are equal to the reference voltage value, and the number of pulses of the emission control signal corresponding to the target luminance level in the one frame time is equal to 1.

10. The driving method of the display panel is characterized in that the display panel comprises a pixel circuit and a light-emitting element, the pixel circuit comprises a driving module, the driving module is used for driving the light-emitting element to emit light, the light-emitting element emits light under the control of a light-emitting control signal, and the light-emitting control signal comprises at least one pulse within one frame of picture time of the display panel;

the driving method includes:

predetermining the pulse number of the light-emitting control signals corresponding to at least two brightness levels in the one frame of picture time, wherein the pulse number of the light-emitting control signals corresponding to different brightness levels in the one frame of picture time is different;

under the condition that the display panel switches the brightness level, determining the pulse number of the corresponding light-emitting control signal within the one-frame picture time of the brightness level to be switched of the display panel;

providing pulses to the pixel circuit as the corresponding number of the light-emitting control signals according to the corresponding number of the light-emitting control signals within the frame of picture time of the brightness level to be switched of the display panel;

and providing a bias compensation voltage signal of a target voltage value to the pixel circuit so as to adjust the bias state of the driving module.

11. The driving method according to claim 10, wherein the display panel comprises at least two brightness levels, the brightness corresponding to the (i + x) th brightness level is greater than the brightness corresponding to the (i) th brightness level, and both i and x are positive integers;

when the luminance level is at the (i + x) th luminance level, the pulse number of the corresponding light-emitting control signal in the frame time is a first number; at the ith brightness level, the number of pulses of the corresponding light-emitting control signal in the frame time is a second number, and the first number is smaller than the second number;

and the ith brightness level and the (i + x) th brightness level adjust the bias state of the driving module based on the bias compensation voltage with the same voltage value.

12. The driving method according to claim 10, wherein the predetermining the number of pulses of the light emission control signal corresponding to at least two luminance levels in the one frame time comprises:

setting the brightness level with the pulse number of 1 of the corresponding light-emitting control signal in the one-frame picture time as a target brightness level, and setting the voltage value of the bias compensation voltage corresponding to the target brightness level as a reference voltage value;

adjusting the pulse number of the light-emitting control signals corresponding to the brightness levels except the target brightness level in the frame time so as to enable the voltage values of the bias compensation voltages corresponding to the other brightness levels to be equal to the reference voltage value;

and recording the pulse number of the corresponding light-emitting control signal when the voltage value of the bias compensation voltage corresponding to other brightness levels is equal to the reference voltage value.

13. The driving method according to claim 10, wherein the predetermining the number of pulses of the light emission control signal corresponding to at least two luminance levels in the one frame picture time comprises:

setting a reference voltage value according to the voltage output capability of the driving chip;

for any jth brightness level, adjusting the pulse number of the light-emitting control signal corresponding to the jth brightness level in the one frame time, so that the voltage value of the bias compensation voltage corresponding to the jth brightness level is equal to the reference voltage value, and j is a positive integer;

and recording the pulse number of the corresponding light-emitting control signal when the voltage value of the bias compensation voltage corresponding to the jth brightness level is equal to the reference voltage value.

14. A display device characterized by comprising the display panel according to any one of claims 1 to 9.