CN115410529A

CN115410529A - Pixel compensation circuit and display panel

Info

Publication number: CN115410529A
Application number: CN202211002666.1A
Authority: CN
Inventors: 张丽君
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd; Huizhou China Star Optoelectronics Display Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd; Huizhou China Star Optoelectronics Display Co Ltd
Priority date: 2022-08-19
Filing date: 2022-08-19
Publication date: 2022-11-29
Also published as: WO2024036897A1

Abstract

The application discloses a pixel compensation circuit and a display panel. The pixel compensation circuit comprises a driving transistor, a compensation module, a first writing module, a second writing module, a light emitting module, a first capacitor and a second capacitor. The compensation module is connected to the second global signal and connected to the first node and the first grid of the driving transistor; the first write-in module is connected to the third global signal, the first initialization signal, the fourth global signal and the second initialization signal and is connected to the second node and the first grid of the driving transistor; the light emitting module is connected to the first global signal and is connected in series between the second power supply end and the first node. According to the display panel, internal compensation can be realized only by 1 group of line scanning level signals, and the display uniformity of the display panel is improved.

Description

Pixel compensation circuit and display panel

Technical Field

The application relates to the technical field of display, in particular to a pixel compensation circuit and a display panel.

Background

In the conventional pixel compensation circuit, the light emitting device is usually driven to emit light by adopting a current driving method. However, the above driving method is sensitive to the electrical variation of the driving transistor, and the threshold voltage drift of the driving transistor may affect the brightness uniformity of the image display.

Currently, there are two main threshold voltage compensation methods, namely external compensation and internal compensation. The external compensation has a large threshold voltage compensation range for the driving transistor, but the driving system is complex and high in cost. The internal compensation driving system is relatively simple and low in cost, but the internal compensation requires multiple groups of line scanning level signals.

Disclosure of Invention

The application provides a pixel compensation circuit and a display panel, which are used for solving the technical problem that an internal compensation circuit needs a plurality of groups of line scanning level transmission signals in the prior art.

The application provides a pixel compensation circuit, it includes:

a driving transistor, a source of which is connected to a first power supply terminal, and a drain of which is connected to a first node;

the light-emitting module comprises a first control end, a first end and a second end; the first control end is connected with a first signal line, the first end is connected with a second power supply end, the second end is connected with the first node, and the light-emitting module is used for emitting light under the control of a first global signal transmitted by the first signal line;

the compensation module comprises a second control end, a third end and a fourth end, the second control end is connected with a second signal line, the third end is connected with the first node, the fourth end is connected with the first grid electrode of the driving transistor, and the compensation module is used for compensating the threshold voltage of the driving transistor under the control of a second global signal transmitted by the second signal line;

the first write-in module comprises a third control end, a fourth control end, a first input end, a second input end, a first output end and a second output end, wherein the third control end is connected with a third signal line, the first input end is connected with a first routing, the fourth control end is connected with a fourth signal line, the second input end is connected with a second routing, the first output end is connected with a second node, and the second output end is connected with a first grid electrode of the driving transistor; the first write-in module is configured to output a first initialization signal transmitted by the first trace to the second node under the control of a third global signal transmitted by the third signal line, and output a second initialization signal transmitted by the second trace to the first gate of the driving transistor under the control of a fourth global signal transmitted by the fourth signal line;

the second write-in module comprises a fifth control end, a third input end and a third output end, the fifth control end is connected with a scanning line, the third input end is connected with a data line, the third output end is connected with the second node, and the second write-in module is used for outputting a data signal transmitted by the data line to the second node under the control of a scanning signal transmitted by the scanning line;

one end of the first capacitor is connected with the second node, and the other end of the first capacitor is connected with the first grid electrode of the driving transistor; and

and one end of the second capacitor is connected with the first grid electrode of the driving transistor, and the other end of the second capacitor is connected with the first power supply end.

Optionally, in some embodiments of the present application, the first writing module includes a first transistor and a second transistor;

the gate of the first transistor is connected to the third signal line, the source of the first transistor is connected to the first trace, and the drain of the first transistor is connected to the second node; the grid electrode of the second transistor is connected with the fourth signal wire, the source electrode of the second transistor is connected with the second routing wire, and the drain electrode of the second transistor is connected with the first grid electrode of the driving transistor.

Optionally, in some embodiments of the present application, the first initialization signal is a signal accessed by the first power source terminal, and the second initialization signal is a signal accessed by the second power source terminal.

Optionally, in some embodiments of the present application, the first initialization signal and the data signal are both output from the corresponding data line, and the second initialization signal is a signal accessed by the second power source terminal.

Optionally, in some embodiments of the present application, the first initialization signal is independent of a signal accessed by the first power source terminal, and the second initialization signal is independent of a signal accessed by the second power source terminal.

Optionally, in some embodiments of the present application, a voltage value of the first initialization signal is smaller than a voltage value of the data signal.

Optionally, in some embodiments of the present application, the driving transistor is a double-gate transistor, and the second gate of the driving transistor is connected to the third signal line to receive an adjustment signal.

Optionally, in some embodiments of the present application, the compensation module includes a compensation transistor;

wherein a gate of the compensation transistor is connected to the second signal line, a source of the compensation transistor is connected to the first gate of the driving transistor, and a drain of the compensation transistor is connected to the first node.

Optionally, in some embodiments of the present application, the light emitting module includes a switching transistor and a light emitting device;

wherein a gate of the switching transistor is connected to the first signal line, a source of the switching transistor is connected to the second power supply terminal, a drain of the switching transistor is connected to an anode of the light emitting device, and a cathode of the light emitting device is connected to the first node;

alternatively, a gate of the switching transistor is connected to the first signal line, a source of the switching transistor is connected to a cathode of the light emitting device, a drain of the switching transistor is connected to the first node, and an anode of the light emitting device is connected to the second power source terminal.

Correspondingly, the application also provides a display panel, the display panel comprises a plurality of pixel units arranged in an array, and each pixel unit comprises any one of the pixel compensation circuits.

The application provides a pixel compensation circuit and a display panel. The pixel compensation circuit comprises a driving transistor, a compensation module, a first writing module, a second writing module, a light emitting module, a first capacitor and a second capacitor. The pixel compensation circuit provided by the application can carry out internal compensation on the threshold voltage drift of the driving transistor by setting the compensation module, and the brightness uniformity of the display panel is improved. In addition, the second global signal, the third global signal, the fourth global signal and the first global signal are adopted in the pixel compensation circuit to correspondingly control the compensation module, the first writing module and the light-emitting module respectively, the number of progressive scanning signals is reduced to one, the circuit structure is simple, and the narrow frame of the display panel or the power consumption of a chip are favorably realized.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a pixel compensation circuit provided in the present application;

FIG. 2 is a first circuit schematic of a pixel compensation circuit provided herein;

FIG. 3 is a signal timing diagram of the pixel compensation circuit shown in FIG. 2;

FIG. 4 is a second circuit schematic of a pixel compensation circuit provided herein;

FIG. 5 is a third circuit schematic of a pixel compensation circuit provided herein;

FIG. 6 is a fourth circuit schematic of a pixel compensation circuit provided herein;

FIG. 7 is a signal timing diagram of the pixel compensation circuit shown in FIG. 6

FIG. 8 is a fifth circuit schematic of a pixel compensation circuit provided herein;

fig. 9 is a schematic structural diagram of a display panel provided in the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or as implying a number of the indicated technical features. Thus, features defined as "first" and "second", etc. may explicitly or implicitly include one or more of the described features and are therefore not to be construed as limiting the application. Furthermore, unless expressly stated or limited otherwise, the terms "connected" and "coupled" are to be construed broadly and encompass, for example, both mechanical and electrical coupling; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

The present application provides a pixel compensation circuit and a display panel, which are described in detail below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments in this application.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a pixel compensation circuit according to the present disclosure. In the embodiment of the present application, the pixel compensation circuit 10 includes a driving transistor Td, a compensation module 102, a first writing module 104, a second writing module 101, a light emitting module 103, a first capacitor C1, and a second capacitor Cst.

Wherein, the source electrode of the driving transistor Td is connected to the first power source terminal VSS. The drain of the driving transistor Td is connected to the first node P.

The light emitting module 103 includes a first control terminal a, a first terminal b, and a second terminal c. The first control terminal a is connected to the first signal line 21 to access the first global signal EM. The first terminal b is connected to the second power source terminal VDD. The second terminal c is connected to the first node P. The light emitting module 103 is configured to emit light under the control of the first global signal EM.

The compensation module 102 includes a second control terminal d, a third terminal e, and a fourth terminal f. The second control terminal d is connected to the second signal line 22 to access the second global signal Comp. The third terminal e is connected to the first node P. The fourth terminal f is connected to the first gate of the driving transistor Td. The compensation module 102 is used for compensating the threshold voltage of the driving transistor Td under the control of the second global signal Comp.

The first write module 104 includes a third control terminal g, a fourth control terminal h, a first input terminal i, a second input terminal j, a first output terminal k, and a second output terminal m. The third control terminal g is connected to the third signal line 23 to access the third global signal Ctr. The first input terminal i is connected to the first trace 25 to access the first initialization signal V1. The fourth control terminal h is connected to the fourth signal line 24 for accessing the fourth global signal Res. The second input terminal j is connected to the second trace 26 to access the second initialization signal V2. The first output terminal k is connected to the second node Q. The second output terminal m is connected to the first gate of the driving transistor Td. The first write module 104 is configured to output the first initialization signal V1 to the second node Q under the control of the third global signal Ctr, and output the fourth global signal Res to the first gate of the driving transistor Td under the control of the fourth global signal Res.

The second write module 101 includes a fifth control terminal r, a third input terminal s, and a third output terminal t. The fifth control terminal r is connected to the scan line 27 for receiving the scan signal SPAM. The third input s is connected to the data line 28 for receiving the data signal Da. The third output terminal t is connected to the second node Q. The second write module 101 is configured to output the data signal Da to the second node Q under the control of the scan signal SPAM.

One end of the first capacitor C1 is connected to the second node Q. The other end of the first capacitor C1 is connected to a first gate of the driving transistor Td.

One end of the second capacitor Cst is connected to the first gate of the driving transistor Td. The other end of the second capacitor Cst is connected to the first power terminal VSS.

In the embodiment of the application, the compensation module 102 is disposed in the pixel compensation circuit 10, so that the threshold voltage drift of the driving transistor Td can be compensated, and the brightness uniformity of the display panel can be improved. In addition, the pixel compensation circuit 10 respectively controls the compensation module 102, the first write-in module 104, and the light-emitting module 103 by using the second global signal Comp, the third global signal Ctr, the fourth global signal Res, and the first global signal EM, so that the pixel compensation circuits 10 in the display panel can simultaneously perform the steps of resetting, threshold voltage compensation, data writing, and the like, thereby reducing the number of progressive scanning signals to one, that is, only the scanning signal SPAM is a multi-level signal, and the circuit structure is simple.

Specifically, when the level-shift scanning signal is generated by the GOA circuit, the pixel compensation circuit 10 in the embodiment of the present application only needs one group of GOA circuits, and the circuit structure is simple, thereby facilitating the realization of the narrow frame of the display panel. When the stage-transmission scanning signal is generated by the chip, the internal circuit structure of the chip can be simplified, and the power consumption of the chip is reduced.

In the embodiment of the present application, the first power source terminal VSS and the second power source terminal VDD are both used for receiving a predetermined voltage signal. In addition, in the embodiment of the present application, the potential of the signal to which the first power source terminal VSS is connected is smaller than the potential of the signal to which the second power source terminal VDD is connected. Specifically, the potential of the signal connected to the first power source terminal VSS may be the potential of the ground terminal. Of course, it is understood that the potential of the signal connected to the first power source terminal VSS may be other.

In an embodiment of the present application, please refer to fig. 2, wherein fig. 2 is a first circuit diagram of a pixel compensation circuit provided in the present application. As shown in conjunction with fig. 1 and 2, the first writing module 104 includes a first transistor T1 and a second transistor T2.

The gate of the first transistor T1 is connected to the third signal line 23 to receive the third global signal Ctr. The source of the first transistor T1 is connected to the first trace 25 to receive the first initialization signal V1. The drain of the first transistor T1 is connected to the second node Q. The gate of the second transistor T2 is connected to a fourth signal line 24 to switch in a fourth global signal Res. The source of the second transistor T2 is connected to the second trace 26 to access the second initialization signal V2. The drain of the second transistor T2 is connected to the first gate of the driving transistor Td.

The compensation module 102 includes a compensation transistor T4. The gate of the compensation transistor T4 is connected to the second signal line 22 for switching in the second global signal Comp. The source of the compensation transistor T4 is connected to the first gate of the driving transistor Td. The drain of the compensation transistor T4 is connected to the drain of the driving transistor Td.

The second write module 101 includes a third transistor T3. The gate of the third transistor T3 is connected to the scan line 27 to receive the scan signal SPAM. The source of the third transistor T3 is connected to the data line 28 to receive the data signal Da. The drain of the third transistor T3 is connected to the second node Q. Of course, it is understood that the second writing module 101 may also be formed using a plurality of transistors connected in series.

The light emitting module 103 includes a switching transistor T5 and a light emitting device D. The gate of the switching transistor T5 is connected to the first signal line 21 to switch in the first global signal EM. The source of the switching transistor T5 is connected to the second power source terminal VDD. The drain of the switching transistor T5 is connected to the anode of the light emitting device D. The cathode of the light emitting device D is connected to the drain of the driving transistor Td.

Of course, it can be understood that, in the pixel compensation circuit 10 provided in the embodiment of the present application, the light emitting module 103 may include 2, 3, 4 or more transistors. Each transistor is connected in series between a first power supply terminal VSS and a second power supply terminal VDD. The plurality of transistors may be connected to the same first global signal EM or to different emission control signals.

It should be noted that the transistors used in all embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and the drain of the transistors used herein are symmetrical, the source and the drain may be interchanged. In the embodiment of the present application, to distinguish two poles of a transistor except for a gate, one of the two poles is referred to as a source, and the other pole is referred to as a drain. The form in the drawing provides that the middle end of the switching transistor is a grid, the signal input end is a source, and the output end is a drain. In addition, the transistors used in the embodiments of the present application may include a P-type transistor and/or an N-type transistor, where the P-type transistor is turned on when the gate is at a low level and turned off when the gate is at a high level, and the N-type transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.

In the following embodiments of the present application, each transistor in the pixel compensation circuit 10 is an N-type transistor as an example, but the present application is not limited thereto.

Referring to fig. 3, fig. 3 is a signal timing diagram of the pixel compensation circuit shown in fig. 2. With reference to fig. 2 and 3, the combination of the second global signal Comp, the third global signal Ctr, the fourth global signal Res, the first global signal EM, and the scan signal SPAM corresponds to the reset phase t1, the threshold voltage compensation phase t2, the data writing phase t3, and the light emitting phase t4 in sequence. That is, in one frame time, the driving control timing of the pixel compensation circuit 10 provided in the embodiment of the present application includes a reset phase t1, a threshold voltage compensation phase t2, a data writing phase t3, and a light emitting phase t4.

In the reset stage T1, the third global signal Ctr and the fourth global signal Res are both high, the second global signal Comp, the first global signal EM, and the scan signal SPAM are all low, at this time, the first transistor T1 and the second transistor T2 are turned on, the third transistor T3, the compensation transistor T4, and the switching transistor T5 are all turned off, and the first initialization signal V1 is output to the second node Q through the first transistor T1. The second initialization signal V2 is output to the first gate of the driving transistor Td through the second transistor T2. The potential of the second node Q is reset to the potential of the first initialization signal V1. The potential of the first gate of the driving transistor Td is reset to the potential of the second initialization signal V2.

In some embodiments, the timing of the third global signal Ctr precedes the timing of the fourth global signal Res during the reset phase. That is, the third global signal Ctr is high, and after a period of time, the fourth global signal Res changes from low to high.

It is understood that the third global signal Ctr first changes from the low level to the high level, the first transistor T1 is turned on, and the potential of the second node Q is reset to the potential of the first initialization signal V1. Then, when the fourth global signal Res changes from the low potential to the high potential, and the potential of the first gate of the driving transistor Td is reset to the potential of the second initialization signal V2, since the first transistor T1 is continuously turned on, the potential of the second node Q can be stabilized at the potential of the first initialization signal V1, and the potential of the first gate of the driving transistor Td is prevented from being coupled to the second node Q through the first capacitor C1, thereby preventing the subsequent threshold voltage compensation from being affected.

In the threshold voltage compensation stage T2, the third global signal Ctr and the second global signal Comp are both high potential, the fourth global signal Res, the first global signal EM, and the scan signal SPAM are all low potential, at this time, the second transistor T2, the third transistor T3, and the switching transistor T5 are all turned off, the first transistor T1 is kept on to stabilize the potential of the second node Q at the potential of the first initialization signal V1, the compensation transistor T4 and the driving transistor Td are turned on, the potential of the first gate of the driving transistor Td starts to leak through the compensation transistor T4, the driving transistor Td, and the first power terminal VSS until the driving transistor Td is turned off, at this time, the potential of the first gate of the driving transistor Td is + VSS. Where Vth is a threshold voltage of the driving transistor Td, and Vss represents a potential of a signal to which the first power source terminal Vss is connected.

It is understood that the driving transistor Td is in an on state under the driving of the second initialization signal V2. Therefore, the voltage value of the second initialization signal V2 needs to be greater than the sum of the voltage value of the signal to which the first power source terminal VSS is connected and the threshold voltage of the driving transistor Td.

In the data writing phase T3, the scan signal SPAM is at a high level, the third transistor T3 is turned on, and the data signal Da is written to the first gate of the driving transistor Td through the third transistor T3 and the first capacitor C1. At this time, the second global signal Comp, the third global signal Ctr, the fourth global signal Res, and the first global signal EM are all low, and the first transistor T1, the second transistor T2, the compensation transistor T4, and the switching transistor T5 are all turned off. The driving transistor Td is turned on by a voltage written to the first gate of the driving transistor Td.

The voltage Vg of the first gate of the write driving transistor Td = Vss + Vth + (Da-V1) × C1/(C1 + Cst).

It should be noted that, in the reset stage t1 and the threshold voltage compensation stage t2, since the second global signal Comp, the third global signal Ctr, the fourth global signal Res, and the first global signal EM adopted by the pixel compensation circuit 10 are all global signals, all the pixel compensation circuits 10 in the display panel perform reset and threshold voltage compensation simultaneously. In the embodiment of the present application, only the scan signal SPAM is a cascade signal, and needs to be output by a group of GOA circuits. In the data writing phase t3, the multi-line scanning signals SPAM (for example, SPAM1, SPAM2, SPAM (n)) are sequentially output, and the data signals Da are written into the corresponding pixel compensation circuits 10 row by row.

In the light-emitting period T4, the first global signal EM is at a high potential, the second global signal Comp, the third global signal Ctr, the fourth global signal Res and the scan signal SPAM are all at a low potential, at this time, the switching transistor T5 is turned on, the first transistor T1, the second transistor T2, the third transistor T3 and the compensation transistor T4 are all turned off, the second power source terminal VDD, the light-emitting device D, the switching transistor T5, the driving transistor Td and the first power source terminal VSS form a path, and the driving transistor Td generates a driving current corresponding to the data signal Da through a potential of the first gate. The driving current flows through the light emitting device D, driving the light emitting device D to emit light. Since the first global signal EM is a global signal, all the light emitting devices D in the display panel emit light at the same time, thereby displaying one frame of picture.

In the light emission period t4, the gate-source voltage difference Vgs = Vss + Vth + (Da-V1) × C1/(C1 + Cst) -Vss = Vth + (Da-V1) × C1/(C1 + Cst) of the driving transistor Td. Since the driving transistor Td operates in a saturation region, a current I = k (Vgs-Vth) flowing through the light emitting device D ² ＝k[(Da-V1)*C1/(C1+Cst)] ² Where k represents mobility. Therefore, the current flowing through the light emitting device D is independent of the threshold voltage Vth of the driving transistor Td, thereby securing the currentThe current through the light emitting device D is not changed, and even if the threshold voltage Vth of the driving transistor Td drifts, the normal light emission of the light emitting device D is not affected, thereby improving the light emission uniformity of the display panel.

Theoretically, the pixel compensation circuit 10 according to the embodiment of the present application can maintain the current variation of the driving transistor Td within the range of 0 to nV within a variation amount of 5%. Wherein the value of n depends on the voltage values of the data voltage Da, the first initializing signal V1, etc.

In addition, as can be seen from the calculation formula of the current flowing through the light emitting device D, the voltage value of the first initialization signal V1 needs to be smaller than the voltage value of the data signal Da, so as to ensure that the light emitting device D emits light normally.

Referring to fig. 2, in the embodiment of the present application, the first initialization signal V1 is a signal for accessing the first power source terminal VSS. The second initialization signal V2 is a signal that the second power terminal VDD is connected. At this time, the voltage Vg of the first gate of the write driving transistor Td = Vss + Vth + (Da-Vss) × C1/(C1 + Cst). The current I = k (Vgs-Vth) flowing through the light emitting device D ² ＝k[(Da-Vss)*C1/(C1+Cst)] ² Also, irrespective of the threshold voltage Vth of the driving transistor Td.

In the embodiment of the present application, the first initialization signal V1 and the signal accessed by the first power source terminal VSS are set as the same signal, and the second initialization signal V2 and the signal accessed by the second power source terminal VDD are set as the same signal, so that signals required by the pixel compensation circuit 10 can be reduced, and the line arrangement can be simplified.

Referring to fig. 4, fig. 4 is a second circuit diagram of the pixel compensation circuit provided in the present application. The difference from the pixel compensation circuit 10 shown in fig. 2 is that, in the light emitting module 103 of the embodiment of the present application, the gate of the switching transistor T5 is connected to the first signal line 21 to switch in the first global signal EM; the source of the switching transistor T5 is connected to the cathode of the light emitting device D; the drain of the switching transistor T5 is connected to the drain of the driving transistor Td; the anode of the light emitting device D is connected to the second power terminal VDD.

It should be noted that the signal driving timing of the pixel compensation circuit 10 in this embodiment is the same as the signal driving timing of the pixel compensation circuit 10 shown in fig. 2, and specific reference may be made to the above embodiments, which are not repeated herein.

Referring to fig. 5, fig. 5 is a third circuit diagram of a pixel compensation circuit according to the present disclosure. The difference from the pixel compensation circuit 10 shown in fig. 2 is that, in the embodiment of the present application, the first initialization signal V1 is independent of the signal accessed by the first power source terminal VSS, and the second initialization signal V2 is independent of the signal accessed by the second power source terminal VDD.

The signal driving timing of the pixel compensation circuit 10 in this embodiment can also refer to the above embodiments, and is not described herein again. At this time, the voltage Vg of the first gate of the write driving transistor Td = Vss + Vth + (Da-V1) × C1/(C1 + Cst). The current I = k (Vgs-Vth) flowing through the light emitting device D ² ＝k[(Da-V1)*C1/(C1+Cst)] ² Also, irrespective of the threshold voltage Vth of the driving transistor Td.

Meanwhile, since the first initializing signal V1 is independent of the signal to which the first power source terminal VSS is connected, the current flowing through the light emitting device D is independent of the signal to which the first power source terminal VSS is connected, and the influence of display unevenness due to IR drop (voltage drop) of the signal to which the first power source terminal VSS is connected can be reduced.

Referring to fig. 6, fig. 6 is a fourth circuit diagram of the pixel compensation circuit provided in the present application. The difference from the pixel compensation circuit 10 shown in fig. 2 is that, in the embodiment of the present application, the first initialization signal V1 and the data signal Da are both output from the corresponding data line 28, and the second initialization signal V2 is the same signal as the signal accessed by the second power source terminal VDD.

Specifically, referring to fig. 7, fig. 7 is a signal timing diagram of the pixel compensation circuit 10 shown in fig. 6. The difference between the timing diagram of fig. 3 and the timing diagram of the present invention is that, in the embodiment of the present application, the data line outputs the data signal Da twice in one frame display period. For the first time in the reset phase t1, the data signal Da output by the data line is the first initialization signal V1 to initialize the potential of the second node Q. The second time in the data writing phase t3, the data line outputs the data signal Da to the first gate of the driving transistor Td.

Similarly, the first initializing signal V1 outputted from the data line is independent of the signal connected to the first power source terminal VSS, so that the current flowing through the light emitting device D is independent of the signal connected to the first power source terminal VSS, thereby reducing the influence of display unevenness caused by IR drop (voltage drop) of the signal connected to the first power source terminal VSS. And the signal wiring in the plane can be further simplified by the first initialization signal V1 output via the data line.

Referring to fig. 8, fig. 8 is a fifth circuit diagram of a pixel compensation circuit according to the present disclosure. The difference from the pixel compensation circuit 10 shown in fig. 2 is that, in the embodiment of the present application, the driving transistor Td is a double gate transistor. The second gate of the driving transistor Td is connected to the third signal line 29 to receive an adjustment signal BG.

Specifically, the adjustment signal BG is a dc signal. When the adjustment signal BG is negative, the threshold voltage Vth of the driving transistor Td may be adjusted in a positive direction. When the adjustment signal BG is a positive voltage, the threshold voltage Vth of the driving transistor Td can be adjusted in a negative direction.

The embodiment of the application can also enlarge the compensation range of the threshold voltage Vth, enable the compensation range to shift from 0-nV to-mV- + pV, and realize the compensation of the negative drift of the threshold voltage Vth, thereby realizing the compensation of the threshold voltage Vth under the condition of the negative drift and the positive drift. Where n, m, p may be determined by the practical application of the driving transistor Td.

Referring to fig. 9, fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. The embodiment of the present application further provides a display panel 100, which includes a plurality of pixel units 11 arranged in an array. Each pixel unit 11 includes the pixel compensation circuit 10, which is described above, and specific reference may be made to the description of the pixel compensation circuit 10, which is not described herein again.

In the embodiment of the present application, the display panel 100 may be an OLED (Organic Light-Emitting Diode) display panel, a Mini LED (Mini Light-Emitting Diode) display panel, a Micro LED (Micro Light-Emitting Diode) display panel, or the like.

In the display panel 100 provided in the embodiment of the present application, the pixel compensation circuit 10 includes a driving transistor, a compensation module, a first writing module, a second writing module, a light emitting module, a first capacitor, and a second capacitor. The pixel compensation circuit 10 provided in the embodiment of the present application can compensate for the threshold voltage difference of the driving transistor by setting the compensation module, so as to improve the brightness uniformity of the display panel 100. In addition, the pixel compensation circuit 10 adopts the second global signal, the third global signal, the fourth global signal and the first global signal to correspondingly control the compensation module, the first write-in module and the light-emitting module respectively, only 1 group of line scanning level signals is needed to realize internal compensation, the circuit structure is simple, and the narrow frame of the display panel 100 is favorably realized or the power consumption of a chip is favorably reduced.

The pixel compensation circuit and the display panel provided in the embodiments of the present application are described in detail above, and a specific example is applied in the description to explain the principles and embodiments of the present application, and the description of the embodiments above is only used to help understand the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A pixel compensation circuit, comprising:

a driving transistor, a source of the driving transistor being connected to a first power supply terminal, a drain of the driving transistor being connected to a first node;

2. The pixel compensation circuit of claim 1, wherein the first write module comprises a first transistor and a second transistor;

3. The pixel compensation circuit of claim 1, wherein the first initialization signal is a signal accessed by the first power supply terminal, and the second initialization signal is a signal accessed by the second power supply terminal.

4. The pixel compensation circuit according to claim 1, wherein the first initialization signal and the data signal are both output from the corresponding data line, and the second initialization signal is a signal accessed by the second power source terminal.

5. The pixel compensation circuit according to claim 1, wherein the first initialization signal is independent of a signal accessed by the first power supply terminal, and the second initialization signal is independent of a signal accessed by the second power supply terminal.

6. The pixel compensation circuit of any one of claims 1-5, wherein a voltage value of the first initialization signal is less than a voltage value of the data signal.

7. The pixel compensation circuit of claim 1, wherein the driving transistor is a dual gate transistor, and the second gate of the driving transistor is connected to a third signal line for receiving an adjustment signal.

8. The pixel compensation circuit of claim 1, wherein the compensation module comprises a compensation transistor;

9. The pixel compensation circuit of claim 1, wherein the light emitting module comprises a switching transistor and a light emitting device;

wherein a gate of the switching transistor is connected to the first signal line, a source of the switching transistor is connected to the second power source terminal, a drain of the switching transistor is connected to an anode of the light emitting device, and a cathode of the light emitting device is connected to the first node;

10. A display panel comprising a plurality of pixel units arranged in an array, each of the pixel units comprising the pixel compensation circuit according to any one of claims 1 to 9.