CN117832298A - Solar cell and preparation method thereof - Google Patents

Solar cell and preparation method thereof Download PDF

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Publication number
CN117832298A
CN117832298A CN202311680571.XA CN202311680571A CN117832298A CN 117832298 A CN117832298 A CN 117832298A CN 202311680571 A CN202311680571 A CN 202311680571A CN 117832298 A CN117832298 A CN 117832298A
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layer
nickel
copper
solar cell
tin
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CN202311680571.XA
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朱万宇
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Tongwei Solar Chengdu Co Ltd
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Tongwei Solar Chengdu Co Ltd
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Abstract

The embodiment of the application provides a solar cell and a preparation method thereof, and relates to the field of solar cells. The solar cell comprises a cell and a grid line positioned on the surface of the cell, wherein the grid line comprises a copper layer, a nickel layer and a tin layer which are sequentially laminated from the direction close to the surface to the direction far away from the surface. According to the solar cell and the preparation method, the copper grid line is protected from being corroded to cause the increase of the line resistance, and the power generation efficiency of the cell is improved.

Description

Solar cell and preparation method thereof
Technical Field
The application relates to the field of solar cells, in particular to a solar cell and a preparation method thereof.
Background
At present, copper interconnection solar cells rely on copper grid lines for current collection and on electroplated tin layers on the copper grid lines for welding. The battery piece is subjected to high temperature of about 200-300 ℃ in the light injection process and the welding process, an IMC alloy layer is formed at the interface of a copper layer and a tin layer at the high temperature, and the main component is Cu 6 Sn 5 And Cu 3 Sn. The formation of the IMC alloy layer reduces the thickness of the copper layer, and the resistance of the IMC alloy layer is significantly higher than that of the copper layer, thereby increasing the line resistance of the gate line.
The copper interconnection solar cell is very sensitive to the change of the line resistance, and the series resistance of the cell can be improved along with the increase of the grid line resistance, so that the filling factor FF is reduced, and the power generation efficiency of the cell is further influenced.
Disclosure of Invention
An object of the embodiment of the application is to provide a solar cell and a preparation method thereof, which can protect a copper grid line from being corroded to cause the increase of line resistance, thereby improving the power generation efficiency of a cell.
In a first aspect, an embodiment of the present application provides a solar cell, including a cell and a grid line located on a surface of the cell, where the grid line includes a copper layer, a nickel layer and a tin layer that are sequentially stacked from a direction close to and far from the surface.
In the technical scheme, the grid line is combined into the copper layer, the nickel layer and the tin layer, and the nickel layer forms the barrier layer in the middle, and the melting point of nickel Ni is 1453 ℃, which is far higher than the light injection and welding temperature, in the light injection process and the welding process, the copper layer and the tin layer can not form the ICM alloy layer, and the copper layer and the nickel layer can not form the IMC alloy layer, so that the copper grid line is protected from being corroded to cause the increase of line resistance, and the power generation efficiency of the battery piece is further improved.
In one possible implementation, the copper layer has a thickness of 8 to 10 μm, the nickel layer has a thickness of 0.5 to 2 μm, and the tin layer has a thickness of 0.5 to 2 μm.
In the above technical scheme, the grid line combination is a copper layer (thickness about 8-10 μm) +nickel layer (thickness about 1-2 μm) +tin layer (thickness about 1-2 μm), the total thickness of the copper layer, nickel layer and tin layer can be 10-14 μm, and the total thickness of the grid line can be leveled compared with that before improvement. Meanwhile, the resistivity of copper Cu is 1.678 mu ohm/cm, the resistivity of nickel Ni is 6.84 mu ohm/cm, the resistivity of tin Sn is 11.0 mu ohm/cm, and the resistivity of nickel Ni is lower than the resistivity of tin Sn, so that the line resistance of the grid line adopting copper, nickel and tin in the application is lower than that of the grid line adopting copper and tin before improvement under the condition that the thickness of the copper layer and the total thickness of the grid line are unchanged.
In one possible implementation, the gate line further includes a nickel-tin alloy layer between the nickel layer and the tin layer, the nickel-tin alloy layer including Ni 3 Sn 2 、Ni 4 Sn 3 Ni and Ni 3 Sn 7 At least one of them.
In the technical proposal, the nickel layer forms a barrier layer between the copper layer and the tin layer, and Cu is not formed in the light injection process and the welding process 6 Sn 5 And Cu 3 An IMC alloy layer of Sn, but forms Ni 3 Sn 2 、Ni 4 Sn 3 Ni and Ni 3 Sn 7 Thereby protecting the copper grid line from being corroded to cause the increase of the line resistance.
In one possible implementation, the nickel-tin alloy layer has a thickness of 0.1 to 1 μm.
In one possible implementation, the gate line further includes a seed layer on a side of the copper layer adjacent to the surface, the seed layer including copper.
In the above technical solution, the seed layer provides conductivity to enable electroplating to proceed smoothly.
In one possible implementation, the battery piece includes an N-type silicon wafer, a first intrinsic amorphous silicon layer, an N-type doped layer, and a first TCO conductive layer on the front side of the N-type silicon wafer are sequentially stacked, and a second intrinsic amorphous silicon layer, a P-type doped layer, and a second TCO conductive layer on the back side of the N-type silicon wafer are sequentially stacked.
In the technical scheme, the photoelectric conversion efficiency of the heterojunction battery is high.
In one possible implementation, the grid lines are disposed on both the front and back sides of the battery plate.
In a second aspect, an embodiment of the present application provides a method for preparing a solar cell provided in the first aspect, including the following steps: and electroplating a copper layer on the surface of the battery piece, electroplating a nickel layer on the copper layer, and electroplating a tin layer on the nickel layer.
In the technical scheme, after copper plating and before tin plating, nickel plating is added, and the method is applied to the copper interconnection solar cell, so that the line resistance can be reduced.
In one possible implementation, the plating solution used to plate the nickel layer includes: 350-400 g/L of nickel sulfamate, 5-10 g/L of nickel chloride and 30-40 g/L of boric acid.
In the technical scheme, the electroplating solution realizes nickel layer electroplating.
In one possible implementation, the temperature of the electroplated nickel layer is 50-60 ℃ for 80-100 s.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a solar cell according to an embodiment of the present disclosure;
FIG. 2 is a scanning electron microscope image of a cross section of a gate line of embodiment 1;
FIG. 3 is a scanning electron microscope image of a cross section of a gate line of comparative example 1.
Icon: 100-solar cell; a 110-N type silicon wafer; 120-a first intrinsic amorphous silicon layer; 130-N type doped layer; 140-a first TCO conductive layer; 150-a first gate line; 151-a first copper seed layer; 152-a first copper layer; 153-a first nickel layer; 154-a first tin layer; 160-a second intrinsic amorphous silicon layer; 170-P-type doped layer; 180-a second TCO conductive layer; 190-a second gate line; 191-a second copper seed layer; 192-a second copper layer; 193-a second nickel layer; 194-second tin layer.
Detailed Description
In the existing preparation process of the copper interconnection heterojunction battery, firstly, texturing and cleaning treatment is carried out on an N-type monocrystalline silicon wafer, then intrinsic amorphous silicon and N-type amorphous silicon films are deposited on the front surface of the silicon wafer, intrinsic amorphous silicon and P-type amorphous silicon films are deposited on the back surface of the silicon wafer, then transparent conductive films (TCO conductive layers) are plated on the amorphous silicon films on the front surface and the back surface, and then a seed layer is plated on the transparent conductive films in a copper plating mode, so that a semi-finished product obtained by completing seed layer deposition is called a yellow membrane. And on the basis of the yellow diaphragm, a grid line pattern is made by using an exposure and development technology, and finally, a copper grid line and a tin protective layer are respectively electroplated on the copper seed layer in copper electroplating solution and tin electroplating solution through electrolytic cell effect.
Copper interconnect cells achieve current collection by electroplated copper (thickness about 8-10 μm) and soldering by electroplated tin (thickness about 2-4 μm), but now existThe light injection process and the welding process are subjected to high temperature of 200-300 ℃, an IMC alloy layer is formed at the interface of copper and tin at the high temperature, and the component is Cu 6 Sn 5 And Cu 3 Sn, the thickness of which is about 2 mu m, only 6-8 mu m remains in the pure copper, and the plating of the IMC alloy layer is significantly higher than the resistance of the pure copper, so that the line resistance of the grid line is improved.
In the traditional PCB (printed circuit board ) industry, there is also a phenomenon of mutual melting of plating layers, but more emphasis is placed on weldability and welding tension of the PCB, and the increase of the line resistance does not cause adverse effects, which is ignored in the battery electrode plating process transferred from the traditional PCB industry.
However, the copper-interconnected solar cell is very sensitive to the change of the line resistance, and the series resistance of the cell can be improved along with the increase of the grid line resistance, so that the filling factor FF is reduced, and the power generation efficiency of the cell is further influenced.
It is therefore desirable to devise a method for reducing the line resistance for copper interconnect solar cells.
In order to make the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below. The specific conditions are not noted in the examples and are carried out according to conventional conditions or conditions recommended by the manufacturer. The reagents or apparatus used were conventional products commercially available without the manufacturer's attention.
The solar cell and the preparation method of the embodiment of the application are specifically described below.
Referring to fig. 1, an embodiment of the present application provides a solar cell 100, which includes a cell and a grid line located on a surface of the cell, wherein the grid line includes a copper layer, a nickel layer and a tin layer sequentially stacked from a direction close to a surface far away from the surface.
In one possible implementation, the copper layer has a thickness of 8-10 μm, the nickel layer has a thickness of 0.5-2 μm, and the tin layer has a thickness of 0.5-2 μm. Illustratively, the copper layer has a thickness of 8 μm, 9 μm, 10 μm, or an intermediate value between any two of the foregoing, the nickel layer has a thickness of 0.5 μm, 1 μm, 1.5 μm, 2 μm, or an intermediate value between any two of the foregoing, and the tin layer has a thickness of 0.5 μm, 1 μm, 1.5 μm, 2 μm, or an intermediate value between any two of the foregoing.
The battery is subjected to a light injection process and a welding process, the nickel layer and the tin layer are mutually fused at high temperature to form a nickel-tin alloy layer, the grid line further comprises the nickel-tin alloy layer positioned between the nickel layer and the tin layer, and the nickel-tin alloy layer comprises Ni 3 Sn 2 、Ni 4 Sn 3 Ni and Ni 3 Sn 7 The thickness of the nickel-tin alloy layer is 0.1-1 mu m.
In one possible implementation, the gate line further includes a seed layer on a side of the copper layer proximate the surface, the seed layer including copper.
In one possible implementation, the battery cell includes an N-type silicon wafer 110, a first intrinsic amorphous silicon layer 120, an N-type doped layer 130, and a first TCO conductive layer 140 on the front side of the N-type silicon wafer 110, and a second intrinsic amorphous silicon layer 160, a P-type doped layer 170, and a second TCO conductive layer 180 on the back side of the N-type silicon wafer 110, are stacked in sequence.
In the embodiments of the present application, "front" and "back" are not limited to a certain surface, but refer to two opposite surfaces, where, for each functional layer, one surface on the same side is a front surface, and the other surface on the same side is a back surface.
In one possible implementation, the front and back sides of the battery cells are each provided with a grid line. Specifically, the front surface of the first TCO conductive layer 140 is provided with a first gate line 150, where the first gate line 150 includes a first copper seed layer 151, a first copper layer 152, a first nickel layer 153, and a first tin layer 154 that are sequentially stacked from the front surface to the outside; the front surface of the second TCO conductive layer 180 is provided with a second gate line 190, and the second gate line 190 includes a second copper seed layer 191, a second copper layer 192, a second nickel layer 193, and a second tin layer 194 sequentially stacked from the back surface to the outside.
The line resistance of the grid line (copper layer, nickel layer and tin layer) before improvement is 120-140 mΩ, and the line resistance of the grid line (copper layer, nickel layer and tin layer) after improvement in the application is 50-60 mΩ. The efficiency BL of the solar cell 100 of the embodiment of the present application is improved by about 0.05% compared to the solar cell 100 before improvement.
In addition, the embodiment of the application provides a preparation method of the solar cell, which comprises the following steps: electroplating a copper layer on the surface of the battery piece, electroplating a nickel layer on the copper layer, and electroplating a tin layer on the nickel layer.
In one possible implementation, the plating solution used to plate the nickel layer includes: 350-400 g/L of nickel sulfamate, 5-10 g/L of nickel chloride and 30-40 g/L of boric acid.
In one possible implementation, the temperature of the electroplated nickel layer is 50-60 ℃ for 80-100 s.
As one embodiment, the production process of the solar cell includes the steps of:
step one, edge wrapping: and wrapping the four edges and the edge positions of the yellow film with edge wrapping glue, wherein the width of the edge wrapping glue is less than or equal to 50 mu m, and the thickness of the edge wrapping glue is 10-15 mu m.
Huang Mopian the structure of the semi-finished product for completing the deposition of the seed layer comprises an N-type silicon wafer, a first intrinsic amorphous silicon layer, an N-type doped layer and a first TCO conductive layer which are sequentially stacked on the front surface of the N-type silicon wafer, and a second intrinsic amorphous silicon layer, a P-type doped layer and a second TCO conductive layer which are sequentially stacked on the back surface of the N-type silicon wafer, wherein the front surface of the first TCO conductive layer is provided with a copper seed layer, and the back surface of the second TCO conductive layer is provided with a copper seed layer.
Secondly, coating: coating photoresist on the front and back of the yellow membrane, and fully covering the yellow membrane, wherein the thickness of the photoresist is controlled to be 10-15 mu m;
third step, laser printing: the established pattern is printed on the photosensitive film by laser according to the designed grid line pattern, the photosensitive film is sensitive to the light and is denatured, and the photosensitive film can be distinguished from the area which is not sensitive to the light;
fourth step, developing: cleaning and removing the photosensitive photoresist area by using an alkaline solution to expose the copper seed layer of the bottom layer;
fifth step, electroplating: electroplating copper layer in copper sulfate electroplating solution with copper layer height controlled at 8-10 microns; then nickel layer electroplating is carried out in nickel sulfamate, the height of the nickel layer is controlled to be 0.5-2 mu m, the formula of the nickel sulfamate is 350-400 g/L of nickel sulfamate, 5-10 g/L of nickel chloride, 30-40 g/L of boric acid, a plurality of additives are added, the temperature is 50-60 ℃ and the time is 80-100 s; finally, carrying out electrotinning in the tin methylsulfonate electroplating solution, wherein the height of the tin layer is controlled to be 0.5-2 mu m;
sixth, removing the film and back etching: firstly, removing all photoresist and mask materials in alkaline (NaOH, KOH and the like) solution, secondly, removing a copper seed layer in a non-grid line area and a tin oxide layer at a grid line in dilute sulfuric acid solution, and finally, only leaving a grid line on the surface of an ITO conductive layer;
seventhly, carrying out light injection treatment on the battery piece subjected to film removal and back etching, wherein the light injection temperature is 200-220 ℃ and the time is 60-120 s;
and eighth, manufacturing the battery piece, and testing the welding binding force of the battery grid line.
The features and capabilities of the present application are described in further detail below in connection with the examples.
Example 1
The embodiment provides a solar cell, which has the following production process:
step one, edge wrapping: and wrapping the four edges and the edge positions of the yellow film with edge wrapping glue, wherein the width of the edge wrapping glue is 30 mu m, and the thickness of the edge wrapping glue is 10 mu m.
Huang Mopian the structure of the semi-finished product for completing the seed layer deposition comprises an N-type silicon wafer, wherein the surface of the N-type silicon wafer is provided with a uniform 'positive pyramid' suede, the size of the N-type silicon wafer is 5 μm, a first intrinsic amorphous silicon layer, an N-type doped layer and a first TCO conductive layer which are positioned on the front surface of the N-type silicon wafer are sequentially stacked, a second intrinsic amorphous silicon layer, a P-type doped layer and a second TCO conductive layer which are positioned on the back surface of the N-type silicon wafer are sequentially stacked, the thickness of the first intrinsic amorphous silicon layer is 4nm, the thickness of the N-type doped layer is 8nm, the thickness of the first TCO conductive layer is 100nm, the thickness of the second intrinsic amorphous silicon layer is 6nm, the thickness of the P-type doped layer is 10nm, the thickness of the second TCO conductive layer is 100nm, the front surface of the first TCO conductive layer is provided with a first copper seed layer corresponding to the position of a grid line, the back surface of the second TCO conductive layer is provided with a second copper seed layer corresponding to the position of the grid line, the thickness of the first copper seed layer is 150nm, and the thickness of the second copper seed layer is 150nm.
Secondly, coating: coating photoresist on the front and back of the yellow film, and covering the yellow film completely, wherein the thickness of the photoresist is controlled to be 10 mu m;
third step, laser printing: the established pattern is printed on the photosensitive film by laser according to the designed grid line pattern, the photosensitive film is sensitive to the light and is denatured, and the photosensitive film can be distinguished from the area which is not sensitive to the light;
fourth step, developing: cleaning and removing the photosensitive photoresist area by using an alkaline solution to expose the copper seed layer of the bottom layer;
fifth step, electroplating: electroplating copper layer in copper sulfate electroplating solution with copper layer height controlled at 8 microns; then nickel layer is electroplated in nickel sulfamate, the height of the nickel layer is controlled to be 1 mu m, the formula of the nickel sulfamate is 350g/L of nickel sulfamate, 5g/L of nickel chloride, 30g/L of boric acid, a plurality of additives are added, the temperature is 50 ℃, and the time is 80s; finally, carrying out electrotinning in the tin methylsulfonate electroplating solution, wherein the height of the tin layer is controlled to be 1 mu m;
sixth, removing the film and back etching: firstly, removing all photoresist and mask materials in NaOH solution, secondly, removing a copper seed layer in a non-grid line area and a tin oxide layer at a grid line in dilute sulfuric acid solution, and finally, only leaving the grid line on the surface of the ITO conductive layer;
seventhly, carrying out light injection treatment on the battery piece subjected to film removal and back etching, wherein the light injection temperature is 200 ℃ and the time is 60s;
and eighth, manufacturing the battery piece, and testing the welding binding force of the battery grid line.
The scanning electron microscope image of the grid line section of the obtained solar cell is shown in fig. 2.
Example 2
The present embodiment provides a solar cell, which is different from embodiment 1 in that: the height of the copper layer is controlled to be 9 mu m; the height of the nickel layer is controlled to be 1 mu m; the tin layer height was controlled at 1 μm.
Example 3
The present embodiment provides a solar cell, which is different from embodiment 1 in that: the height of the copper layer is controlled to be 10 mu m; the height of the nickel layer is controlled to be 2 mu m; the tin layer height was controlled at 2 μm.
Comparative example 1
The present comparative example provides a solar cell, which is different from comparative example 1 in that: the nickel layer is not arranged, and the height of the copper layer is controlled to be 8 mu m; the tin layer height was controlled at 2 μm.
The scanning electron microscope image of the grid line section of the obtained solar cell is shown in fig. 3.
Through experimental tests, the solar cell of example 1 has an efficiency BL improved by 0.05% over the solar cell of comparative example 1.
In summary, according to the solar cell and the preparation method of the embodiment of the application, the copper grid line is protected from being corroded to cause the increase of the line resistance, and the power generation efficiency of the cell is further improved.
The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (10)

1. The solar cell is characterized by comprising a cell and a grid line positioned on the surface of the cell, wherein the grid line comprises a copper layer, a nickel layer and a tin layer which are sequentially stacked from the direction close to the surface to the direction far away from the surface.
2. The solar cell according to claim 1, wherein the copper layer has a thickness of 8 to 10 μm, the nickel layer has a thickness of 0.5 to 2 μm, and the tin layer has a thickness of 0.5 to 2 μm.
3. The solar cell of claim 1, wherein the grid line further comprises a nickel-tin alloy layer between the nickel layer and the tin layer, the nickel-tin alloy layer comprising Ni 3 Sn 2 、Ni 4 Sn 3 Ni and Ni 3 Sn 7 At least one of them.
4. A solar cell according to claim 3, wherein the nickel-tin alloy layer has a thickness of 0.1-1 μm.
5. The solar cell of claim 1, wherein the gate line further comprises a seed layer on a side of the copper layer proximate the surface, the seed layer comprising copper.
6. The solar cell of claim 1, wherein the cell comprises an N-type silicon wafer, a first intrinsic amorphous silicon layer, an N-type doped layer, and a first TCO conductive layer on the front side of the N-type silicon wafer, and a second intrinsic amorphous silicon layer, a P-type doped layer, and a second TCO conductive layer on the back side of the N-type silicon wafer, stacked in that order.
7. The solar cell according to claim 1 or 6, wherein the grid lines are provided on both the front and back sides of the cell sheet.
8. A method of manufacturing a solar cell according to any one of claims 1 to 7, comprising the steps of: and electroplating a copper layer on the surface of the battery piece, electroplating a nickel layer on the copper layer, and electroplating a tin layer on the nickel layer.
9. The method of manufacturing a solar cell according to claim 8, wherein the plating solution used for the nickel plating comprises: 350-400 g/L of nickel sulfamate, 5-10 g/L of nickel chloride and 30-40 g/L of boric acid.
10. The method of manufacturing a solar cell according to claim 8, wherein the temperature of the electroplated nickel layer is 50 to 60 ℃ for 80 to 100 seconds.
CN202311680571.XA 2023-12-07 2023-12-07 Solar cell and preparation method thereof Pending CN117832298A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311680571.XA CN117832298A (en) 2023-12-07 2023-12-07 Solar cell and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311680571.XA CN117832298A (en) 2023-12-07 2023-12-07 Solar cell and preparation method thereof

Publications (1)

Publication Number Publication Date
CN117832298A true CN117832298A (en) 2024-04-05

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