CN218160394U - Heterojunction battery structure for improving battery efficiency - Google Patents
Heterojunction battery structure for improving battery efficiency Download PDFInfo
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- CN218160394U CN218160394U CN202222068669.7U CN202222068669U CN218160394U CN 218160394 U CN218160394 U CN 218160394U CN 202222068669 U CN202222068669 U CN 202222068669U CN 218160394 U CN218160394 U CN 218160394U
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- amorphous silicon
- electrode
- silicon substrate
- type amorphous
- doping layer
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- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 34
- 239000010703 silicon Substances 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000002002 slurry Substances 0.000 claims abstract description 17
- 239000000853 adhesive Substances 0.000 claims abstract description 6
- 230000001070 adhesive effect Effects 0.000 claims abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 238000003466 welding Methods 0.000 abstract description 8
- 238000006243 chemical reaction Methods 0.000 abstract description 5
- 239000007788 liquid Substances 0.000 abstract description 5
- 239000010408 film Substances 0.000 description 18
- 210000004027 cell Anatomy 0.000 description 14
- 235000012431 wafers Nutrition 0.000 description 12
- 238000007639 printing Methods 0.000 description 11
- 238000007747 plating Methods 0.000 description 8
- 239000000843 powder Substances 0.000 description 8
- 238000007650 screen-printing Methods 0.000 description 8
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000007787 solid Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000004050 hot filament vapor deposition Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 210000005056 cell body Anatomy 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- NEIHULKJZQTQKJ-UHFFFAOYSA-N [Cu].[Ag] Chemical compound [Cu].[Ag] NEIHULKJZQTQKJ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000839 emulsion Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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Abstract
The utility model relates to an improve heterojunction battery structure of battery efficiency, the silicon substrate, the grid line corresponding position at the front and the back of silicon substrate all is equipped with an electrode tank of inside concave yield, the front and the back of silicon substrate all are equipped with amorphous silicon intrinsic layer, the outside on the positive amorphous silicon intrinsic layer of silicon substrate is equipped with N type amorphous silicon doping layer, and the outside on the amorphous silicon intrinsic layer at the back of silicon substrate is equipped with P type amorphous silicon doping layer, the outside on N type amorphous silicon doping layer is equipped with one deck positive TCO conducting film, the outside on P type amorphous silicon doping layer is equipped with one deck back TCO conducting film; the electrode structure is characterized in that a metal lead is arranged in the electrode groove and fixed at the bottom of the electrode groove through conductive adhesive, low-temperature slurry is printed in the electrode groove, and the low-temperature slurry outside the electrode groove forms an electrode. The utility model discloses thereby reduce series resistance and improve battery photoelectric conversion efficiency and increase the welding pulling force of low temperature thick liquids.
Description
Technical Field
The utility model relates to a photovoltaic cell technical field especially relates to an improve battery efficiency's heterojunction battery structure.
Background
The current manufacturing process of heterojunction batteries: cleaning and texturing, coating amorphous silicon, PVD or RPD coating and screen printing to prepare a metal electrode; the process temperature of the four main processes is below 250 ℃, wherein the electrode is prepared by using low-temperature slurry through a screen printing technology, and the low-temperature slurry is printed on a printing stock through a screen printing machine with specific patterns and parameters.
The low-temperature slurry is required to have: high conductivity, welding tension above 1N/mm, good printing performance and reliability. The high conductivity is mainly determined by metal powder, the metal powder is used as a conductive medium and is wrapped and connected by resin, the metal powder does not need to be sintered according to the quantum tunneling effect, and electrons generated in the solar cell can be transmitted between the TCO film layer and the metal powder to form a conductive path only by resin crosslinking. Compared with high-temperature sintering slurry, low-temperature slurry has poorer bulk resistance and contact resistance, and most of the low-temperature slurry has contact resistanceAt 5E-05. Omega. Cm 2 The bulk resistance is in the range of 5E-06 Ω cm.
The welding tension is required to be more than 1N/mm, the welding tension is mainly adhered to the TCO by the adhesive force provided by the resin in the paste, the conductivity of the paste is reduced by too much resin, and the welding tension cannot meet the requirement by less resin;
the low-temperature slurry is adjusted by a solvent, the solid content (metal powder: silver powder and silver-copper complex) in the low-temperature slurry is about 95 percent, the solvent is relatively less, and in order to improve the conductivity of the conductive metal powder, part of the powder is flaky, and the flaky powder is also one of the main influence factors of the printability. Reliability is mainly regulated by resin.
In order to improve the conversion efficiency of the photovoltaic cell, the series resistance is preferably smaller. In the grid lines (the main grid line width is about 100um, the height is about 15um, the front side auxiliary grid line width is about 55um, the height is about 18 um) prepared by using the conventional screen printing plate (photosensitive emulsion screen printing plate and PI film screen printing plate) in the conventional multi-main grid heterojunction battery, the series resistance is found to have a larger reduction space through secondary printing; however, the increase of the width of the grid line in the secondary printing can reduce the short-circuit current loss caused by the light receiving area of the battery, and the improvement of the photoelectric conversion efficiency is influenced.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to overcome the aforesaid not enough, provide an improve battery efficiency's heterojunction battery structure, solve the poor, the pulling force of pulling force low and the poor problem of printability of grid line aspect ratio, thereby reduce the welding pulling force that series resistance improves battery photoelectric conversion efficiency and increases low temperature thick liquids.
The purpose of the utility model is realized like this:
a heterojunction battery structure for improving battery efficiency comprises a silicon substrate, wherein inwards recessed electrode grooves are formed in positions, corresponding to grid lines, of the front surface and the back surface of the silicon substrate respectively, amorphous silicon intrinsic layers are arranged on the front surface and the back surface of the silicon substrate respectively, an N-type amorphous silicon doping layer is arranged on the outer side of the amorphous silicon intrinsic layer on the front surface of the silicon substrate, a P-type amorphous silicon doping layer is arranged on the outer side of the amorphous silicon intrinsic layer on the back surface of the silicon substrate, a front TCO conductive film is arranged on the outer side of the N-type amorphous silicon doping layer, and a back TCO conductive film is arranged on the outer side of the P-type amorphous silicon doping layer; a metal wire is arranged in the electrode groove, and low-temperature slurry is printed in the electrode groove to realize the pre-embedding of the metal wire; and the low-temperature slurry outside the electrode groove forms an electrode.
Further, the width of the electrode groove is 10-20um, and the depth is 8-15um.
Further, the metal wire is a copper wire.
Furthermore, the metal lead is fixed in the electrode groove through conductive adhesive.
Compared with the prior art, the beneficial effects of the utility model are that:
(1) The battery piece of the utility model reduces the shielding area of the grid line, increases the sectional area of the conductive grid line and improves the conductivity; the utility model optimizes the appearance of the grid line, improves the height-width ratio and the uniformity of the grid line, reduces the resistance loss of the grid line and increases the light receiving area of the battery; the utility model increases the contact area between the grid line and the TCO film layer to reduce the contact resistance between the grid line (metal electrode) and the TCO film layer; the utility model discloses a area of contact increase of main grid line and TCO membrane to improve the welding pulling force of main grid line.
(2) The utility model discloses a positive back of battery piece is equipped with the electrode slot, changes into pre-buried solid metal conductor in the recess, like the copper conductor, solid copper conductor electric conductivity is greater than low temperature silver thick liquid electric conductivity to can reduce the silver thick liquid consumption about 50%, greatly reduced silver thick liquid consumption, greatly reduced the manufacturing cost of heterojunction battery.
(3) The utility model discloses a cell body structure can reduce printing half tone parameter requirement, and the attenuate half tone is thick, promotes printing speed.
Drawings
Fig. 1 is a schematic structural diagram of a photovoltaic cell according to the present invention.
Fig. 2 is a partial sectional view of the electrode of the present invention.
Fig. 3 is a schematic sectional view of the electrode cell of the present invention.
Wherein:
the solar cell comprises a silicon substrate 1, an amorphous silicon intrinsic layer 2, an N-type amorphous silicon doping layer 3, a P-type amorphous silicon doping layer 4, a front TCO conductive film 5, a back TCO conductive film 6, an electrode groove 7, a metal wire 8 and an electrode 9.
Detailed Description
For better understanding of the technical solution of the present invention, the following detailed description will be made with reference to the accompanying drawings. It should be understood that the following embodiments are not intended to limit the embodiments of the present invention, but only the embodiments of the present invention. It should be noted that the description of the positional relationship of the components, such as the component a is located above the component B, is based on the description of the relative positions of the components in the drawings, and is not intended to limit the actual positional relationship of the components.
Example 1:
referring to fig. 1-3, fig. 1 depicts a front view of a heterojunction cell structure of example 1 that improves cell efficiency. As shown in the figures, the photovoltaic module without the main grid related to the embodiment 1 includes a silicon substrate 1, wherein an electrode groove 7 recessed inwards is respectively disposed at the corresponding positions of grid lines on the front surface and the back surface of the silicon substrate 1, and the width of the electrode groove 7 is 15um, and the depth of the electrode groove 7 is 10um;
the front and the back of the silicon substrate 1 are both provided with amorphous silicon intrinsic layers 2, an N-type amorphous silicon doping layer 3 is arranged on the outer side of the amorphous silicon intrinsic layer 2 on the front of the silicon substrate 1, a P-type amorphous silicon doping layer 4 is arranged on the outer side of the amorphous silicon intrinsic layer 2 on the back of the silicon substrate 1, a front TCO conductive film 5 is arranged on the outer side of the N-type amorphous silicon doping layer 3, and a back TCO conductive film 6 is arranged on the outer side of the P-type amorphous silicon doping layer 4.
A metal wire 8 is arranged in the electrode groove 7, the metal wire 8 is fixed at the bottom of the electrode groove 7 through conductive adhesive, and low-temperature slurry is printed in the electrode groove 7 to realize pre-embedding of the metal wire 8; the low temperature slurry outside the electrode tank 7 forms the electrodes 9.
Referring to fig. 1 to fig. 3, the present invention relates to a method for manufacturing a heterojunction battery structure with improved battery efficiency, including the following steps:
s1, laser grooving
Selecting a silicon wafer, and forming an electrode groove at the corresponding position of the grid line on the front side and the back side of the silicon wafer;
s2, cleaning and texturing silicon wafers
Texturing and cleaning the slotted silicon wafer; organic dirt, metal impurities and a surface damage layer on the surface of the silicon wafer are removed through a cleaning process; etching the silicon wafer after efficient cleaning, wherein suede layers are formed on the front side and the back side of the silicon wafer;
s3, coating film of amorphous silicon intrinsic layer
Respectively plating amorphous silicon intrinsic layers on the front side and the back side of a silicon wafer, plating an intrinsic amorphous silicon thin film on a cell by PECVD, HWCVD or LPCVD technology, wherein the thickness of the amorphous silicon intrinsic layer on the front side is 6nm, and the thickness of the amorphous silicon intrinsic layer on the back side is 4nm;
s4, coating film of N-type amorphous silicon doped layer and P-type amorphous silicon doped layer
Plating an N-type amorphous silicon doped layer on the front surface of the silicon wafer, and plating an N-type doped amorphous silicon film on the cell by PECVD, HWCVD or LPCVD technology, wherein the thickness of the N-type amorphous silicon doped layer is 8nm;
plating a P-type amorphous silicon doped layer on the back surface of the silicon wafer, and plating an N-type doped amorphous silicon film on the cell by PECVD, HWCVD or LPCVD technology, wherein the thickness of the P-type amorphous silicon doped layer is 10nm;
s5, TCO conductive film deposition
Plating transparent TCO conductive films on the front side and the back side of the silicon wafer by adopting a PVD or RPD equipment technology;
s6, embedding the metal wire
Arranging a solid metal wire such as a copper wire in the electrode groove, and fixing the metal wire through a conductive adhesive;
s7, metallization
Printing low-temperature slurry in electrode grooves on the front side and the back side of a silicon wafer by adopting screen printing to respectively prepare metal electrodes;
s8, sorting test
And selecting the required battery pieces through a sorting test.
The thickness of a single-side film plated by the two processes of PECVD (plasma enhanced chemical vapor deposition) and RPD (or PVD) plating is about 200nm, the change of the internal size of an electrode groove is small, finally, a front-side auxiliary grid is printed above a groove body through screen printing, the line division height between the top of the auxiliary grid and the surface part of the TCO film is 13um, the line division height of the groove body is 10um, the bus height can be increased to 23um, and the line width of the auxiliary grid is 35um.
Therefore the utility model discloses a printing step only needs to adopt conventional half tone, about the membrane is thick 15um, can below the opening width 25um (the thick 25-30um of conventional heterojunction half tone, opening width 28-33um is left and right sides), the battery piece collocation after having increased the cell body knot is gone up the low membrane and is thick, the half tone of low opening width, the higher that grid line aspect ratio can be done, grid line and TCO rete contact surface can be bigger, printing speed also can be improved, thereby grid line body resistance has been reduced, surface contact resistance has been reduced, grid line shading area has been reduced, the fluting printing can also promote the welding pulling force under the main grid.
Will the utility model discloses a cell performance data of embodiment 1 does not adopt the heterojunction battery contrast of buried wire printing with the conventionality, and the electrical performance contrast table of this embodiment 1 and prior art shows below, mainly embodies from short-circuit current Isc, fill factor FF and open circuit voltage Voc, can obtain the utility model discloses a solar cell performance parameter's promotion makes solar cell's conversion efficiency Eta have absolute 1% promotion.
| Isc（A） | Uoc(V) | FF(%) | Eta(%) | |
| Prior Art | 9.682 | 0.7517 | 84.41 | 24.562 |
| Example 1 | 10.001 | 0.7520 | 85.00 | 25.559 |
The above is only a specific application example of the present invention, and does not constitute any limitation to the protection scope of the present invention. All the technical solutions formed by equivalent transformation or equivalent replacement fall within the protection scope of the present invention.
Claims (4)
1. A heterojunction battery structure for improving battery efficiency is characterized in that: the silicon substrate comprises a silicon substrate (1), wherein inwards recessed electrode grooves (7) are formed in positions corresponding to grid lines on the front surface and the back surface of the silicon substrate (1), amorphous silicon intrinsic layers (2) are formed on the front surface and the back surface of the silicon substrate (1), an N-type amorphous silicon doping layer (3) is arranged on the outer side of the amorphous silicon intrinsic layer (2) on the front surface of the silicon substrate (1), a P-type amorphous silicon doping layer (4) is arranged on the outer side of the amorphous silicon intrinsic layer (2) on the back surface of the silicon substrate (1), a front TCO conductive film (5) is arranged on the outer side of the N-type amorphous silicon doping layer (3), and a back TCO conductive film (6) is arranged on the outer side of the P-type amorphous silicon doping layer (4); a metal lead (8) is arranged in the electrode groove (7), and low-temperature slurry is printed in the electrode groove (7); and the low-temperature slurry outside the electrode tank (7) forms an electrode (9).
2. A heterojunction cell structure according to claim 1, wherein: the width of the electrode groove (7) is 10-20um, and the depth is 8-15um.
3. A heterojunction cell structure according to claim 1, wherein: the metal wire is a copper wire.
4. A heterojunction cell structure according to claim 1, wherein: the metal lead is fixed in the electrode groove through conductive adhesive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222068669.7U CN218160394U (en) | 2022-08-08 | 2022-08-08 | Heterojunction battery structure for improving battery efficiency |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222068669.7U CN218160394U (en) | 2022-08-08 | 2022-08-08 | Heterojunction battery structure for improving battery efficiency |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218160394U true CN218160394U (en) | 2022-12-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222068669.7U Active CN218160394U (en) | 2022-08-08 | 2022-08-08 | Heterojunction battery structure for improving battery efficiency |
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| Country | Link |
|---|---|
| CN (1) | CN218160394U (en) |
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2022
- 2022-08-08 CN CN202222068669.7U patent/CN218160394U/en active Active
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 313100 in the factory area of Zhejiang Aikang Photoelectric Technology Co., Ltd., zheneng Smart Energy Technology Industrial Park, Meishan Town, Changxing County, Huzhou City, Zhejiang Province Patentee after: Huzhou Aikang Photoelectric Technology Co.,Ltd. Patentee after: Zhejiang Aikang Photoelectric Technology Co.,Ltd. Patentee after: Zhejiang Aikang New Energy Technology Co.,Ltd. Address before: 313100 in the factory area of Zhejiang Aikang Photoelectric Technology Co., Ltd., zheneng Smart Energy Technology Industrial Park, Meishan Town, Changxing County, Huzhou City, Zhejiang Province Patentee before: Huzhou Aikang Photoelectric Technology Co.,Ltd. Patentee before: Zhejiang Aikang Photoelectric Technology Co.,Ltd. Patentee before: JIANGYIN AKCOME SCIENCE AND TECHNOLOGY Co.,Ltd. |
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| CP01 | Change in the name or title of a patent holder |