CN117790302A - RC-IGBT structure with p floating region at collector side and manufacturing method - Google Patents
RC-IGBT structure with p floating region at collector side and manufacturing method Download PDFInfo
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- CN117790302A CN117790302A CN202311761131.7A CN202311761131A CN117790302A CN 117790302 A CN117790302 A CN 117790302A CN 202311761131 A CN202311761131 A CN 202311761131A CN 117790302 A CN117790302 A CN 117790302A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000010410 layer Substances 0.000 claims description 40
- 238000002347 injection Methods 0.000 claims description 20
- 239000007924 injection Substances 0.000 claims description 20
- 239000011229 interlayer Substances 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 239000007943 implant Substances 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 abstract description 4
- 230000001965 increasing effect Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 12
- 230000010354 integration Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Abstract
The invention aims to provide an RC-IGBT structure with a p floating region at the collector side and a manufacturing method thereof. The p floating region is introduced above the n+ short circuit region at the collector side at the back of the chip, and at the initial stage of forward conduction, the p floating region depletes the electron channel below, so that the electron channel has high resistance, belongs to a high-resistance region, the flow of electrons is blocked, electrons are accumulated at the collector side, the potential difference at the two ends of a p+/N-buffer junction is increased, the p+/N-buffer junction is started to inject holes in advance, the device enters a bipolar mode earlier, the conversion of the single bipolar mode of the device is effectively controlled, and the snapback phenomenon is restrained or even eliminated.
Description
Technical Field
The invention belongs to the technical field of semiconductor discrete devices, and relates to an RC-IGBT structure with a p floating region at a collector side and a manufacturing method thereof.
Background
In an actual inverter circuit, when an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) is turned off under an inductive load, an anti-parallel diode is required to freewheel because the current on the load cannot be suddenly changed. This not only increases the system volume, but also introduces additional parasitic inductance into the circuit, thereby affecting the reliability of the system. Therefore, it is necessary to integrate the IGBT with the diode to form a reverse-conducting IGBT.
However, the RC-IGBT has a transition from a unipolar mode to a bipolar mode when being conducted in the forward direction, thereby forming a remarkable snapback phenomenon. This can introduce electromagnetic oscillations into the circuit, severely affecting system stability.
The integration of the IGBT and the freewheeling diode (FWD) is achieved by the conventional RC-IGBT by introducing an n+ short-circuit region at the collector. This design reduces stray inductance, manufacturing and packaging costs to a large extent.
However, the voltage foldback (snapback) phenomenon exists in the forward conduction process of the traditional RC-IGBT, so that the turn-on power consumption and the reliability of the device are seriously affected.
In order to solve the problem, the conventional RC-IGBT suppresses the snapback phenomenon by increasing the width of the p+ collector region, but this greatly increases the chip size, and an excessively large width ratio of the p+ collector region to the n+ short-circuit region may cause uneven carrier distribution when the device is turned on, thereby reducing the reliability of the device.
The existing RC-IGBT structure, such as the traditional RC-IGBT, increases the short circuit resistance of the collector side by increasing the width of the p+ collector region; the BIGT enables the device to enter a bipolar mode firstly by introducing an IGBT without an n+ short circuit area as a guiding IGBT; the TFP-RC-IGBT introduces an oxide trench and a P floating region at the collector side to increase the collector side resistance; the SJ-RC-IGBT adopting the super junction structure can inhibit reducing the turning voltage difference by reducing the resistance of the drift region. However, these techniques either result in a significant increase in chip size, or are complex and costly.
Disclosure of Invention
The invention aims to provide an RC-IGBT structure with a p floating region at the collector side and a manufacturing method thereof, wherein the p floating region is introduced above an n+ short circuit region at the collector side at the back of a chip, so that the conversion of a single-bipolar mode of a device is effectively controlled, and the snapback phenomenon is restrained or even eliminated.
The specific technical scheme of the invention is as follows:
the manufacturing method of the RC-IGBT structure with the p floating region at the collector side specifically comprises the following steps:
step one, selecting an N-type silicon wafer with proper resistivity as an N-drift region;
step two, performing CS layer injection on the front surface of the n-drift region;
digging a groove, wherein the groove passes through the bottom of the CS layer to contact with the n-drift region, and a gate oxide layer and heavily doped polysilicon are sequentially filled in the groove;
step four, injecting a Pbody region, wherein the injection position is a CS layer outside the groove;
step five, n+ injection is carried out, and the n+ injection is positioned above Pbody areas on two sides of the upper surface groove;
depositing an interlayer dielectric layer, typically an oxide layer, and performing hole etching to form an interlayer dielectric layer on the upper surface of a certain groove, and injecting p+ ohmic contact between n+ regions;
step seven, depositing a metal layer, shorting two grooves which are not deposited with an interlayer dielectric layer with an n+ emission area to form an Emitter electrode Emitter, forming a grid G by a groove grid which is deposited with the interlayer dielectric layer, and performing front passivation;
step eight, injecting an N-buffer area, wherein the injection position is at the bottom of the N-drift area;
step nine, p+ injection is carried out in the N-buffer area;
step ten, carrying out p floating region injection on one side of the N-buffer region by adopting a back doping process, wherein the bottom surface of the p floating region is positioned above p+, and the upper surface of the p floating region is lower than the upper surface of the N-buffer region;
step eleven, injecting an n+ short-circuit region below the p floating region, wherein the upper surface of the n+ short-circuit region is contacted with the lower surface of the p floating region and is not contacted with the N-buffer region;
and twelve, depositing a metal structure at the corresponding positions of the back p+ and the back n+ and carrying out back etching, and shorting the p+ Collector and the n+ short-circuit region to form a Collector.
In the third step, three grooves are dug in the unit structure, the grooves are uniformly distributed, and CS layers are arranged among the grooves.
In the fourth step, after the injection of the Pbody area is completed, the layer height of the Pbody area is larger than that of the CS layer.
In the fifth step, n+ is injected to form an upper n+ region, and the upper n+ region is arranged at the upper contact angle position of the Pbody region and the side wall of the groove.
And step six, depositing an interlayer dielectric layer above the rightmost groove of the three grooves in the unit structure, wherein the left and right boundaries of the interlayer dielectric layer are in two adjacent upper n+ regions, p+ injection is carried out between the two upper n+ regions to form an upper p+ region, and the interlayer dielectric layer is not contacted with the upper p+ region.
In the eighth step, the implantation position of the N-buffer area is specifically the lower left corner of the N-drift area of the unit structure.
In step nine, a p+ implant forms a lower p+ region, which is inside the N-buffer region.
In step ten, the sidewall of the p floating region is contacted with the N-buffer region.
An RC-IGBT structure with a p floating region on the collector side manufactured according to the manufacturing method.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
the invention provides an RC-IGBT structure with a p floating region at the collector side. According to the structure, the p floating region is introduced above the n+ short circuit region at the collector side of the back side of the chip, so that the snapback phenomenon in the forward conduction process is effectively eliminated. The structure is simple in manufacturing process, small in chip size and capable of meeting urgent requirements of power integration application.
In the early stage of forward conduction, the resistance of the electron channel increases due to the depletion effect of the p floating region on the electron channel below, and a high-resistance region is formed, so that the flow of electrons is blocked, and the electrons are accumulated on the collector side. This process further increases the potential difference across the p+/N-buffer junction, so that the p+/N-buffer junction opens up the injected holes in advance. Due to the interaction of the series of physical processes, the device can enter a bipolar mode earlier, so that the conversion of a single bipolar mode of the device is effectively controlled, and the snapback phenomenon is further inhibited or even eliminated.
At smaller cell sizes, the structure can completely eliminate snapback phenomenon at the early stage of forward conduction. Therefore, the RC-IGBT structure with the p floating region has remarkable advantages in terms of improving device performance and reliability, and provides a more optimized solution for power integration application.
Drawings
FIG. 1 is a schematic diagram of step one of the present invention.
FIG. 2 is a schematic diagram of a second step of the present invention.
FIG. 3 is a schematic diagram of step three of the present invention.
FIG. 4 is a schematic diagram of step four of the present invention.
FIG. 5 is a schematic diagram of step five of the present invention.
FIG. 6 is a schematic diagram of step six of the present invention.
Fig. 7 is a schematic diagram of step seven of the present invention.
Fig. 8 is a schematic diagram of step eight of the present invention.
Fig. 9 is a schematic diagram of step nine of the present invention.
Fig. 10 is a schematic diagram of step ten of the present invention.
Fig. 11 is a schematic diagram of step eleven.
FIG. 12 is a schematic diagram of a step twelve of the present invention.
Fig. 13 is a conventional prior art conventional RC-IGBT structure.
Fig. 14 is a forward and reverse turn-on characteristic curve of the RC-IGBT structure according to the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings:
the invention provides an RC-IGBT structure with a p floating region at a collector side and a manufacturing method thereof, which specifically comprises the following steps:
1. selecting an N-type silicon wafer with proper resistivity as an N-drift region, as shown in figure 1;
2. performing CS layer injection on the front surface of the n-drift region, as shown in FIG. 2;
3. digging grooves, namely digging three grooves in the left, middle and right of the unit structure, and sequentially filling a gate oxide layer and heavily doped polysilicon in the grooves, as shown in fig. 3;
4. performing Pbody region implantation, as shown in FIG. 4, to form Pbody regions between the trenches;
5. performing n+ implantation, as shown in fig. 5, to form an upper n+ region, wherein the upper n+ region is positioned at an upper contact angle between the Pbody region and the side wall of the groove;
6. depositing an interlayer dielectric layer, typically an oxide layer, and performing hole etching to form an interlayer dielectric layer above the left trench, wherein the width of the interlayer dielectric layer is larger than the width of the trench but smaller than the distance between two adjacent upper n+ regions, and injecting p+ ohmic contact between the two adjacent upper n+ regions, as shown in fig. 6, namely an upper p+ region;
7. depositing a metal layer, shorting the two grooves on the middle and right sides with an n+ emission area to form an Emitter Emitter, forming a grid G on the groove grid on the left side, and performing front passivation, wherein the front passivation is shown in FIG. 7;
8. performing N-buffer region injection, wherein the injection position is at the bottom of the N-drift region, as shown in FIG. 8;
9. p+ implantation is performed in the N-buffer region, as shown in FIG. 9;
the right side of the N-buffer region is subjected to p floating region injection by adopting a back doping process, as shown in FIG. 10;
11. performing n+ short-circuit region implantation below the p floating region as shown in fig. 11;
12. and depositing a metal structure on the back surface and reversely etching, and shorting the p+ Collector and the n+ short circuit region to form a Collector, thereby completing the chip manufacturing flow of the invention, as shown in figure 12.
In the RC-IGBT structure with the p floating region on the collector side, which is obtained by the manufacturing method, the p floating region is introduced above the n+ short circuit region on the collector side on the back surface of the chip to form RC inhibition. In the early stage of forward conduction, the p floating region depletes the electron channel below, so that the electron channel resistance is large, the electron channel belongs to a high-resistance region, the flow of electrons is blocked, electrons are accumulated at the collector side, the potential difference of the two ends of a p+/N-buffer junction is further increased, the p+/N-buffer junction is started to inject holes in advance, the device enters a bipolar mode earlier, the conversion of a single bipolar mode of the device is effectively controlled, and the snapback phenomenon is restrained or even eliminated. As shown in fig. 14, the snapback phenomenon at the early stage of forward conduction is completely eliminated at smaller cell sizes.
The foregoing description of the embodiments of the present invention will be presented with reference to the accompanying drawings, but the present invention is not limited to the embodiments described above, and it is within the scope of the present invention to those skilled in the art to adopt equivalent means for the technical scheme of the present invention by reading the description of the present invention.
Claims (9)
1. The manufacturing method of the RC-IGBT structure with the p floating region at the collector side is characterized by comprising the following steps of:
step one, selecting an N-type silicon wafer with proper resistivity as an N-drift region;
step two, performing CS layer injection on the front surface of the n-drift region;
digging a groove, wherein the groove passes through the bottom of the CS layer to contact with the n-drift region, and a gate oxide layer and heavily doped polysilicon are sequentially filled in the groove;
step four, injecting a Pbody region, wherein the injection position is a CS layer outside the groove;
step five, n+ injection is carried out, and the n+ injection is positioned above Pbody areas on two sides of the upper surface groove;
depositing an interlayer dielectric layer, typically an oxide layer, and performing hole etching to form an interlayer dielectric layer on the upper surface of a certain groove, and injecting p+ ohmic contact between n+ regions;
step seven, depositing a metal layer, shorting two grooves which are not deposited with an interlayer dielectric layer with an n+ emission area to form an Emitter electrode Emitter, forming a grid G by a groove grid which is deposited with the interlayer dielectric layer, and performing front passivation;
step eight, injecting an N-buffer area, wherein the injection position is at the bottom of the N-drift area;
step nine, p+ injection is carried out in the N-buffer area;
step ten, carrying out p floating region injection on one side of the N-buffer region by adopting a back doping process, wherein the bottom surface of the p floating region is positioned above p+, and the upper surface of the p floating region is lower than the upper surface of the N-buffer region;
step eleven, injecting an n+ short-circuit region below the p floating region, wherein the upper surface of the n+ short-circuit region is contacted with the lower surface of the p floating region and is not contacted with the N-buffer region;
and twelve, depositing a metal structure at the corresponding positions of the back p+ and the back n+ and carrying out back etching, and shorting the p+ Collector and the n+ short-circuit region to form a Collector.
2. The method of manufacturing an RC-IGBT structure with a p floating region on the collector side according to claim 1, wherein in step three, three trenches are dug in the cell structure, the trenches are uniformly distributed, and the CS layer is spaced between the trenches.
3. The method of manufacturing an RC-IGBT structure with a p floating region on the collector side according to claim 2, wherein in step four, the Pbody region has a layer height greater than the layer height of the CS layer after the Pbody region is implanted.
4. A method of fabricating an RC-IGBT structure with a p floating region on the collector side according to claim 3, wherein in step five, n+ implant forms an upper n+ region, the upper n+ region being at the upper contact angle position of the Pbody region and the trench sidewall.
5. The method of manufacturing an RC-IGBT structure having a p floating region on the collector side as recited in claim 4, wherein in step six, an interlayer dielectric layer is deposited over the rightmost trench of the three trenches in the cell structure, the left and right boundaries of the interlayer dielectric layer are in the two upper n+ regions adjacent to each other, and p+ implantation is performed between the two upper n+ regions to form an upper p+ region, and the interlayer dielectric layer is not in contact with the upper p+ region.
6. The method of manufacturing an RC-IGBT structure having a p floating region on the collector side as recited in claim 5, wherein in step eight, the N-buffer implant is specifically the lower left corner of the N-drift region of the cell structure.
7. The method of claim 6, wherein in step nine, the p+ implant forms a lower p+ region, the lower p+ region being inside the N-buffer region.
8. The method for manufacturing an RC-IGBT structure with a p floating region on the collector side of claim 7 wherein in step ten the sidewall of the p floating region is in contact with the N-buffer region.
9. An RC-IGBT structure having a p floating region on the collector side based on the manufacturing method according to any one of claims 1 to 8.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311761131.7A CN117790302A (en) | 2023-12-20 | 2023-12-20 | RC-IGBT structure with p floating region at collector side and manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311761131.7A CN117790302A (en) | 2023-12-20 | 2023-12-20 | RC-IGBT structure with p floating region at collector side and manufacturing method |
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| CN117790302A true CN117790302A (en) | 2024-03-29 |
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| CN202311761131.7A Pending CN117790302A (en) | 2023-12-20 | 2023-12-20 | RC-IGBT structure with p floating region at collector side and manufacturing method |
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