CN117673132A - 与肖特基二极管集成的绝缘栅双极型晶体管及其制备方法 - Google Patents
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Abstract
本发明涉及绝缘栅双极型晶体管，具体涉及一种与肖特基二极管集成的绝缘栅双极型晶体管及其制备方法，用于解决绝缘栅双极型晶体管在保持击穿特性时，无法同时优化正向导通电压VF和关断损耗Eoff的不足之处。该与肖特基二极管集成的绝缘栅双极型晶体管包括栅介质层，以及分别设置在栅介质层两侧的高阻硅衬底和肖特基二极管结构，其中肖特基二极管结构由N1区、N+区、N2区构成；本发明通过将常规结构的漂移区面积减小，并将部分栅电极、部分集电极设置为肖特基接触，使IGBT通过栅介质层与类似于肖特基二极管的N‑N+N‑结构集成。同时。本发明公开一种与肖特基二极管集成的绝缘栅双极型晶体管的制备方法。
Description
技术领域
本发明涉及绝缘栅双极型晶体管，具体涉及一种与肖特基二极管集成的绝缘栅双极型晶体管及其制备方法。
背景技术
绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，IGBT)可以等效为一个由金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-EffectTransistor，MOSFET)驱动的PNP晶体管，能够同时兼顾MOSFET和双极型晶体管的优点，是目前中高压领域中较为理想的电力电子开关器件。随着行业内对节能环保、能源利用率等方面要求越来越高，IGBT因为其输入阻抗高、正向电压低、开关损耗小等优越性能而得到了广泛关注和高速发展。
IGBT的设计优化主要包含击穿电压VB、正向导通电压VF等静态特性和关断时间Toff、关断损耗Eoff等动态特性。这些特性中主要存在两大矛盾，一个是击穿电压和正向导通电压的矛盾关系，一个是正向导通电压和关断损耗的矛盾。目前为缓解上述矛盾，研究者们使用的方法主要包括电荷存储技术、超结技术、辅助栅极技术、寿命控制工艺技术、短路阳极技术和电场调制技术等，但上述矛盾尤其是正向导通电压VF和关断损耗Eoff之间的矛盾，仍然是IGBT设计过程中最主要的技术难题。
发明内容
本发明的目的是解决绝缘栅双极型晶体管在保持击穿特性时，无法同时优化正向导通电压VF和关断损耗Eoff的不足之处，而提供一种与肖特基二极管集成的绝缘栅双极型晶体管及其制备方法。
为了解决上述现有技术所存在的不足之处，本发明提供了如下技术解决方案：
一种与肖特基二极管集成的绝缘栅双极型晶体管，其特殊之处在于：包括栅介质层，以及分别设置在栅介质层两侧的高阻硅衬底和肖特基二极管结构；
所述高阻硅衬底上部设置有P型基区，P型基区上部设置有发射区，发射区包括N+发射区和P+发射区，N+发射区靠近所述栅介质层设置，发射区顶面设置有发射极；所述高阻硅衬底下部由上至下依次设置有N型缓冲层、P+集电区；
所述P型基区、N型缓冲层、栅介质层之间形成漂移区，漂移区为N型或P型；
所述栅介质层顶面高度与发射区顶面相等，栅介质层底面高度与P+集电区底面高度相等；
所述肖特基二极管结构包括由上至下依次设置且相互连接的N1区、N+区、N2区，所述N1区、N+区分别和漂移区、N型缓冲层位置对应且厚度相等；
所述栅介质层靠近N1区一侧设置有常规栅电极，所述N1区顶面设置有肖特基接触栅电极，常规栅电极与肖特基接触栅电极通过外部金属连接构成栅电极，具有相同电势；
所述P+集电区底面设置有常规集电极，所述N2区底面设置有肖特基接触集电极，常规集电极与肖特基接触集电极通过外部金属连接构成集电极，具有相同电势。
进一步地，所述N1区掺杂浓度、N2区掺杂浓度均与漂移区掺杂浓度相等，为1×1013cm-3～1×1015cm-3；所述N+区掺杂浓度为1×1019cm-3～1×1020cm-3。
进一步地，所述N+区厚度为1～2μm；所述N2区厚度为1～4μm。
进一步地，所述P型基区的掺杂浓度为1×1016cm-3～1×1017cm-3；所述N型缓冲层的掺杂浓度为1×1017cm-3～5×1017cm-3；所述P+集电区的掺杂浓度不低于1×1019cm-3。
进一步地，所述漂移区厚度根据所需击穿电压范围设置，宽度为1～8μm。
进一步地，所述栅介质层的材料为二氧化硅或高K材料，其宽度为0.05～2μm。
进一步地，所述N1区掺杂浓度、N2区掺杂浓度均与漂移区掺杂浓度相等，为1×1014cm-3～5×1014cm-3；所述N+区掺杂浓度为5×1019cm-3～1×1020cm-3。
进一步地，所述P型基区的掺杂浓度为3×1016cm-3～8×1016cm-3；所述N型缓冲层的掺杂浓度为3×1017cm-3～5×1017cm-3；所述P+集电区的掺杂浓度为3×1019cm-3～8×1019cm-3。
同时，本发明提供一种上述与肖特基二极管集成的绝缘栅双极型晶体管的制备方法，其特殊之处在于，包括如下步骤：
步骤1、选取所需掺杂浓度的高阻硅衬底作为器件漂移区；
步骤2、在高阻硅衬底上部通过离子注入形成P型基区，并在P型基区的上部形成发射区，发射区包括N+发射区和P+发射区，再在发射区顶面通过淀积金属形成发射极；
步骤3、在高阻硅衬底下部通过离子注入依次形成N型缓冲层和P+集电区；
步骤4、在发射极靠近N+发射区一侧的高阻硅衬底上通过刻蚀形成沟槽，沟槽厚度小于高阻硅衬底厚度；
步骤5、在沟槽靠近发射极一侧的内壁上生长栅介质层，栅介质层厚度等于沟槽厚度，栅介质层宽度小于沟槽宽度；
步骤6、在沟槽内从下向上依次生长出N2区、N+区、N1区；
步骤7、在栅介质层侧面、N1区顶面分别形成第一栅电极与第二栅电极，将第一栅电极与具有肖特基接触的第二栅电极通过刻蚀工艺分隔开，将常规栅电极与肖特基接触栅电极通过外部金属连接构成栅电极；
步骤8、研磨高阻硅衬底底面直至露出N2区；
步骤9、在P+集电区底面、N2区底面通过淀积金属分别形成常规集电极、肖特基接触集电极，将常规栅电极与肖特基接触栅电极通过外部金属连接构成栅电极；
步骤10、在步骤9所得到的整体表面形成钝化层，完成与肖特基二极管集成的绝缘栅双极型晶体管的制备。
与现有技术相比，本发明的有益效果是：
本发明一种与肖特基二极管集成的绝缘栅双极型晶体管，包括栅介质层，以及分别设置在栅介质层两侧的高阻硅衬底和肖特基二极管结构，其中肖特基二极管结构由N1区、N+区、N2区构成；本发明通过将常规结构的漂移区面积减小，并将部分栅电极、部分集电极设置为肖特基接触，使IGBT通过栅介质层与类似于肖特基二极管的N-N+N-结构集成；
本发明结构中的所述漂移区可为N型或P型，相比于常规结构均起到优化作用；
本发明结构中的肖特基二极管结构在IGBT正反向电压中，均呈现出截止状态，其N1区、N2区内靠近栅介质层界面处具有竖直方向上的近似恒定的正电压，使漂移区内靠近栅介质层处形成电子积累层，从而有效降低正向导通电压VF；
当本发明结构中的漂移区为N型时，相比于常规IGBT结构，本发明结构能在保持击穿特性的基础上相较常规结构使正向导通电压VF下降59.48％，关断损耗Eoff下降30.01％；
当本发明结构中的漂移区为P型时，由于刚开始关断时的本发明结构的米勒电容远小于常规结构及具有N型漂移区的本发明结构，使得关断电压缓慢上升，从而有效降低关断损耗Eoff，本发明结构能在保持击穿特性的基础上相较常规结构使正向导通电压VF下降59.42％，关断损耗Eoff下降54.37％。
本发明可在保持击穿特性的同时，降低IGBT的正向导通电压和关断损耗，缓解IGBT正向导通电压和关断损耗的矛盾关系。
附图说明
图1为本发明一种与肖特基二极管集成的绝缘栅双极型晶体管一个实施例的结构示意图；
图2为本发明实施例与常规结构的击穿电压对比示意图；
图3为本发明实施例与常规结构的导通特性对比示意图；
图4为本发明实施例与常规结构的关断特性对比示意图；
图5为本发明实施例与常规结构的米勒电容特性对比示意图。
附图标记说明如下：1-发射极；2-栅介质层；3-栅电极；4-P+发射区；5-N+发射区；6-P型基区；7-漂移区；8-N1区；9-N型缓冲层；10-N+区；11-P+集电区；12-N2区；13-集电极。
具体实施方式
下面结合附图和示例性实施例对本发明作进一步地说明。
绝缘栅双极型晶体管(IGBT)在正向导通过程中为降低正向导通电压VF，需要降低漂移区导通电阻，并增加非平衡载流子(电子-空穴)浓度。但在IGBT关断过程中，大量“电子-空穴”载流子使IGBT在关断时出现较大的拖尾电流，造成关断损耗增加。因此IGBT设计优化过程中最主要的技术难题是如何更好的缓解正向导通电压VF与关断损耗Eoff的矛盾关系。
为了解决上述矛盾关系，本发明公开一种与肖特基二极管集成的绝缘栅双极型晶体管，如图1所示，包括栅介质层2，以及分别设置在栅介质层2两侧的高阻硅衬底和肖特基二极管结构。
高阻硅衬底上部设置有P型基区6，P型基区6上部设置有发射区，发射区顶面设置有发射极1，发射区包括N+发射区和P+发射区4，N+发射区靠近所述栅介质层2设置；P型基区6掺杂浓度为3×1016cm-3～8×1016cm-3，厚度为1～2μm，宽度与高阻硅衬底相等。
高阻硅衬底下部由上至下依次设置有N型缓冲层9、P+集电区11；N型缓冲层9掺杂浓度为3×1017cm-3～5×1017cm-3，厚度为1～2μm；P+集电区11掺杂浓度为3×1019cm-3～8×1019cm-3。
所述P型基区6、N型缓冲层9、栅介质层2之间形成厚度为30μm的漂移区7，漂移区7为N型或P型，掺杂浓度为1×1014cm-3～5×1014cm-3，厚度根据所需击穿电压范围设置，宽度为1～8μm。
栅介质层2顶面高度与发射区相等，栅介质层2底面高度与P+集电区11底面高度相等；其中栅介质层2的材料可为二氧化硅或高K介质，宽度为0.05～2μm。
所述肖特基二极管结构包括由上至下依次设置且相互连接的N1区8、N+区10、N2区12，所述N1区8、N+区10分别和漂移区7、N型缓冲层9位置对应且厚度相等；N1区8掺杂浓度、N2区12掺杂浓度均与漂移区7一致，N+区10掺杂浓度为5×1019cm-3～1×1020cm-3，N2区12厚度为2～3μm。肖特基二极管结构宽度可根据工艺限制合理设置，应不小于1μm，也需符合元胞面积越小，集成度越高的原则。
所述栅介质层2靠近N1区8一侧设置有常规栅电极，所述N1区8顶面设置有肖特基接触栅电极，常规栅电极与肖特基接触栅电极通过外部金属连接构成栅电极3，具有相同电势。肖特基接触栅电极用于增加肖特基二极管正反向截止时在轻掺杂区域的电压。
所述P+集电区11底面设置有常规集电极，所述N2区12底面设置有肖特基接触集电极，常规集电极与肖特基接触集电极通过外部金属连接构成集电极13，具有相同电势。
上述与肖特基二极管集成的绝缘栅双极型晶体管的制备方法，包括如下步骤：
步骤1、选取所需掺杂浓度的高阻硅衬底作为器件漂移区7；
步骤2、在高阻硅衬底上部通过离子注入形成P型基区6，并在P型基区6上部形成发射区，再在发射区顶面通过淀积金属形成发射极1；
步骤3、在高阻硅衬底下部通过离子注入依次形成N型缓冲层9和P+集电区11；
步骤4、在发射极1靠近N+发射区一侧的高阻硅衬底上通过刻蚀形成沟槽，沟槽厚度小于高阻硅衬底厚度；
步骤5、在沟槽靠近发射极1一侧的内壁上生长栅介质层2，栅介质层2厚度等于沟槽厚度，栅介质层2宽度小于沟槽宽度；
步骤6、在沟槽内从下向上依次生长出N2区12、N+区10、N1区8；
步骤7、在栅介质层2侧面、N1区8顶面分别形成常规栅电极与肖特基接触栅电极,将常规栅电极与肖特基接触栅电极通过刻蚀工艺分隔开，将常规栅电极与肖特基接触栅电极通过外部金属连接构成栅电极3；
步骤8、研磨高阻硅衬底底面直至露出N2区12；
步骤9、在P+集电区11底面、N2区12底面通过淀积金属分别形成常规集电极、肖特基接触集电极，将常规栅电极与肖特基接触栅电极通过外部金属连接构成栅电极13；
步骤10、在步骤9所得到的整体表面形成钝化层，完成与肖特基二极管集成的绝缘栅双极型晶体管的制备。
本发明的仿真结果如下：
参见图2，本发明结构与常规结构的击穿电压对比结果说明：本发明结构保持了与常规结构同等的击穿特性，均能在漂移区7为30μm时，达到600V的耐压范围。
参见图3，本发明结构与常规结构的导通特性对比结果说明：本发明结构不论是具有N型漂移区还是P型漂移区都能使器件在保持击穿特性的同时，正向导通电压VF降低约59.4％。
参见图4和图5，本发明结构与常规结构的关断特性和米勒电容对比结果说明：本发明的漂移区7为N型时，虽然米勒电容略高于常规结构，但在较低关断电压时肖特基结处于反偏状态，会阻止电容放电，使关断电压上升速率变小，因此使本发明结构关断损耗Eoff(1.1207mJ/cm2)相比于常规结构关断损耗Eoff(1.6032mJ/cm2)下降了30.01％；当漂移区为P型时，由于刚开始关断时的本发明结构的米勒电容远小于常规IGBT及具有N型漂移区的本发明结构，关断时其电压上升明显变缓慢，因此本发明结构能在保持击穿特性的基础上，使本发明结构关断损耗Eoff(0.7315mJ/cm2)相比于常规结构关断损耗Eoff(1.6032mJ/cm2)下降了54.37％。
本实施例中的IGBT也可以为P沟道，其结构与本实施例中的N沟道IGBT等同。
以上实施例仅用以说明本发明的技术方案，而非对其限制，对于本领域的普通专业技术人员来说，可以对前述各实施例所记载的具体技术方案进行修改，或者对其中部分技术特征进行等同替换，而这些修改或者替换，并不使相应技术方案的本质脱离本发明所保护技术方案的范围。
Claims (9)
1.一种与肖特基二极管集成的绝缘栅双极型晶体管，其特征在于：包括栅介质层(2)，以及分别设置在栅介质层(2)两侧的高阻硅衬底和肖特基二极管结构；
所述高阻硅衬底上部设置有P型基区(6)，P型基区(6)上部设置有发射区，发射区包括N+发射区(5)和P+发射区(4)，N+发射区(5)靠近所述栅介质层(2)设置，发射区顶面设置有发射极(1)；所述高阻硅衬底下部由上至下依次设置有N型缓冲层(9)、P+集电区(11)；
所述P型基区(6)、N型缓冲层(9)、栅介质层(2)之间形成漂移区(7)，漂移区(7)为N型或P型；
所述栅介质层(2)顶面高度与发射区顶面相等，栅介质层(2)底面高度与P+集电区(11)底面高度相等；
所述肖特基二极管结构包括由上至下依次设置且相互连接的N1区(8)、N+区(10)、N2区(12)，所述N1区(8)、N+区(10)分别和漂移区(7)、N型缓冲层(9)位置对应且厚度相等；
所述栅介质层(2)靠近N1区(8)一侧设置有常规栅电极，所述N1区(8)顶面设置有肖特基接触栅电极，常规栅电极与肖特基接触栅电极通过外部金属连接构成栅电极(3)，具有相同电势；
所述P+集电区(11)底面设置有常规集电极，所述N2区(12)底面设置有肖特基接触集电极，常规集电极与肖特基接触集电极通过外部金属连接构成集电极(13)，具有相同电势。
2.根据权利要求1所述的与肖特基二极管集成的绝缘栅双极型晶体管，其特征在于：所述N1区(8)掺杂浓度、N2区(12)掺杂浓度均与漂移区(7)掺杂浓度相等，为1×1013cm-3～1×1015cm-3；所述N+区(10)掺杂浓度为1×1019cm-3～1×1020cm-3。
3.根据权利要求2所述的与肖特基二极管集成的绝缘栅双极型晶体管，其特征在于：所述N+区(10)厚度为1～2μm；所述N2区(12)厚度为1～4μm。
4.根据权利要求3所述的与肖特基二极管集成的绝缘栅双极型晶体管，其特征在于：所述P型基区(6)的掺杂浓度为1×1016cm-3～1×1017cm-3；所述N型缓冲层(9)的掺杂浓度为1×1017cm-3～5×1017cm-3；所述P+集电区(11)的掺杂浓度不低于1×1019cm-3。
5.根据权利要求4所述的与肖特基二极管集成的绝缘栅双极型晶体管，其特征在于：所述漂移区(7)厚度根据所需击穿电压范围设置，宽度为1～8μm。
6.根据权利要求1至5任一所述的与肖特基二极管集成的绝缘栅双极型晶体管，其特征在于：所述栅介质层(2)的材料为二氧化硅或高K材料，其宽度为0.05～2μm。
7.根据权利要求6所述的与肖特基二极管集成的绝缘栅双极型晶体管，其特征在于：所述N1区(8)掺杂浓度、N2区(12)掺杂浓度与漂移区(7)掺杂浓度为1×1014cm-3～5×1014cm-3；所述N+区(10)掺杂浓度为5×1019cm-3～1×1020cm-3。
8.根据权利要求7所述的与肖特基二极管集成的绝缘栅双极型晶体管，其特征在于：所述P型基区(6)的掺杂浓度为3×1016cm-3～8×1016cm-3；所述N型缓冲层(9)的掺杂浓度为3×1017cm-3～5×1017cm-3；所述P+集电区(11)的掺杂浓度为3×1019cm-3～8×1019cm-3。
9.一种权利要求1所述的与肖特基二极管集成的绝缘栅双极型晶体管的制备方法，其特征在于，包括如下步骤：
步骤1、选取所需掺杂浓度的高阻硅衬底作为器件漂移区(7)；
步骤2、在高阻硅衬底上部通过离子注入形成P型基区(6)，并在P型基区(6)的上部形成发射区，发射区包括N+发射区(5)和P+发射区(4)，再在发射区顶面通过淀积金属形成发射极(1)；
步骤3、在高阻硅衬底下部通过离子注入依次形成N型缓冲层(9)和P+集电区(11)；
步骤4、在发射极(1)靠近N+发射区一侧的高阻硅衬底上通过刻蚀形成沟槽，沟槽厚度小于高阻硅衬底厚度；
步骤5、在沟槽靠近发射极(1)一侧的内壁上生长栅介质层(2)，栅介质层(2)厚度等于沟槽厚度，栅介质层(2)宽度小于沟槽宽度；
步骤6、在沟槽内从下向上依次生长出N2区(12)、N+区(10)、N1区(8)；
步骤7、在栅介质层(2)侧面、N1区(8)顶面分别形成常规栅电极与肖特基接触栅电极，将常规栅电极与肖特基接触栅电极通过刻蚀工艺分隔开，将常规栅电极与肖特基接触栅电极通过外部金属连接构成栅电极(3)；
步骤8、研磨高阻硅衬底底面直至露出N2区(12)；
步骤9、在P+集电区(11)底面、N2区(12)底面通过淀积金属分别形成常规集电极、肖特基接触集电极，将常规栅电极与肖特基接触栅电极通过外部金属连接构成栅电极(13)；
步骤10、在步骤9所得到的整体表面形成钝化层，完成与肖特基二极管集成的绝缘栅双极型晶体管的制备。
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