CN117672876A - Forming process of chip packaging structure of through silicon via type adapter plate - Google Patents

Forming process of chip packaging structure of through silicon via type adapter plate Download PDF

Info

Publication number
CN117672876A
CN117672876A CN202410132889.2A CN202410132889A CN117672876A CN 117672876 A CN117672876 A CN 117672876A CN 202410132889 A CN202410132889 A CN 202410132889A CN 117672876 A CN117672876 A CN 117672876A
Authority
CN
China
Prior art keywords
silicon via
adapter plate
layer
chip
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202410132889.2A
Other languages
Chinese (zh)
Other versions
CN117672876B (en
Inventor
张黎
郭洪岩
张宇锋
龚嘉明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhejiang Hexin Integrated Circuit Co ltd
Original Assignee
Zhejiang Hexin Integrated Circuit Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhejiang Hexin Integrated Circuit Co ltd filed Critical Zhejiang Hexin Integrated Circuit Co ltd
Priority to CN202410132889.2A priority Critical patent/CN117672876B/en
Publication of CN117672876A publication Critical patent/CN117672876A/en
Application granted granted Critical
Publication of CN117672876B publication Critical patent/CN117672876B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention discloses a forming process of a chip packaging structure of a through silicon via type adapter plate, and belongs to the technical field of semiconductor packaging. The process comprises the following steps: manufacturing a through silicon via type adapter plate single body through a wafer level process, wherein a micro-switching structure is arranged on the front surface of the through silicon via type adapter plate single body; adopting a stamping process to manufacture micro metal bumps on the front surface of a carrier wafer, wherein the micro metal bumps are in one-to-one correspondence with micro switching structures of the through silicon via type switching plate monomers; the through silicon via type adapter plate monomer is subjected to flip-chip bonding and plastic packaging with a carrier wafer in sequence, and then the through silicon via type adapter plate monomer is thinned; packaging a plurality of chips on a through silicon via type adapter plate monomer by adopting a wafer level fan-out process, wherein the chips are single bare chips or a plurality of bare chips; further thinning the carrier wafer side; setting BGA solder balls II; dicing into monomers. The invention forms the chip packaging structure of the ultrathin through silicon via adapter plate, reduces the warpage of the packaging structure and can improve the reliability of the packaging structure.

Description

Forming process of chip packaging structure of through silicon via type adapter plate
Technical Field
The invention relates to a forming process of a chip packaging structure of a through silicon via type adapter plate, and belongs to the technical field of semiconductor packaging.
Background
Currently, in a 2.5D/3D package structure, in order to realize multi-chip, small-sized and highly integrated package, a through silicon via Interposer (TSV Interposer) is often used to stack the package in a vertical direction. As shown in fig. 1, patent CN105428260 discloses a method for manufacturing a carrier-based fan-out 2.5D/3D package structure, in which, in the stacked structure, the through-silicon via interposer shortens the interconnection length between chips, and reduces the parasitic capacitance and inductance accompanying the interconnection, thereby shortening the signal transmission delay.
The size of the current TSV Interposer is larger and larger, and because EMC (encapsulating material) is arranged on the upper side of the TSV Interposer, the upper stress and the lower stress are unbalanced, and the warping defects of two ends of the stacked packaging structure are larger and larger, so that the control is difficult; because the temporary bonding scheme is used, the thickness of the TSV can not be made very thin during CMP (chemical mechanical polishing), if the thickness is too thin, fragments or mechanical damage can be caused by uneven stress, so that the thickness of the interser is still maintained to be about 100 microns; as TSV hole requirements become smaller, the underfill failure rate increases with increasing depth, and the most common defect is the cavitation problem, which makes the reliability of the package structure during the flip-chip to substrate process a great challenge.
Disclosure of Invention
In order to overcome the defects of the existing packaging technology, the invention provides a forming technology of a chip packaging structure of a thinner through silicon via type adapter plate, so as to reduce the warpage of the packaging structure and improve the reliability of the packaging structure.
The technical scheme of the invention is as follows:
the invention provides a forming process of a chip packaging structure of a through silicon via type adapter plate, which comprises the following steps:
step one, manufacturing a through-silicon-via type adapter plate single body through a wafer-level process, wherein a micro-switching structure is arranged on the front surface of the through-silicon-via type adapter plate single body, and the micro-switching structure comprises a micro-metal column and a temporary solder layer arranged at the top end of the micro-metal column;
secondly, adopting a bumping process to manufacture micro metal bumps on the front surface of the carrier wafer, wherein the micro metal bumps are in one-to-one correspondence with micro-switching structures of the through silicon via type switching plate monomers;
step three, the through-silicon-through-hole type adapter plate monomer is subjected to flip-chip bonding and plastic packaging with a carrier wafer in sequence, and then the back surface of the through-silicon-through-hole type adapter plate monomer is thinned;
packaging a plurality of chips on the through silicon via type adapter plate monomer by adopting a wafer level fan-out process, wherein the chips are single bare chips or a plurality of bare chips, or single-group multilayer stacked chip assemblies, or a plurality of groups of multilayer stacked chip assemblies, or the combination of the bare chips and the multilayer stacked chips;
step five, further thinning the wafer side of the carrier to expose the top end face of the micro metal column of the through silicon via type adapter plate monomer;
step six, arranging Ball Grid Array (BGA) solder balls II on the top end surfaces of the micro metal columns of the through silicon via type adapter plate monomers;
and step seven, dicing into a plurality of chip packaging structure monomers of the through silicon via type adapter plate.
Further, in the first step, the through-silicon-via type interposer monomer is manufactured through a wafer, and the specific process is as follows:
step 1.1, a through silicon via array which does not penetrate through a wafer is formed on the front surface of the wafer by adopting a traditional TSV adapter plate process, the through silicon via is in a blind hole shape, metal copper is electroplated in the through silicon via to form copper columns, the front surface of the wafer is firstly covered with a PI (POLYIMIDE) layer I and a PI window is opened, then a re-wiring process is adopted to manufacture a metal re-wiring layer I, the metal re-wiring layer I is connected with the copper columns in the through silicon via in a telecommunication way through the PI window downwards, and an output bonding pad I is manufactured on the topmost layer of the metal re-wiring layer I upwards;
step 1.2, adopting a stamping (bump manufacturing technology) process, manufacturing a micro metal column on an output bonding pad I of a metal rewiring layer I, and arranging a temporary welding layer on the top end surface of the micro metal column;
and 1.3, thinning the wafer by adopting a CMP grinding process, and then scribing the wafer into a plurality of through-silicon-via type adapter plate monomers.
Further, the section size of the micro metal bump is larger than or equal to the section size of the micro metal column.
In the third step, the through-silicon via type interposer monomer is flip-chip bonded with a carrier wafer and is encapsulated, and then the back surface of the through-silicon via type interposer monomer is thinned, specifically as follows:
step 3.1, sequentially flip-chip mounting the through-silicon-via type adapter plate monomers on the front surface of a carrier wafer, and welding the micro metal columns and the micro metal bumps through a temporary welding layer;
step 3.2, performing bottom filling between the through silicon via type adapter plate monomer and the carrier wafer by adopting an underfill filling process to form a filling layer I;
step 3.3, integrally molding a through silicon via type adapter plate monomer by adopting an encapsulating material on the carrier wafer to form an encapsulating layer II;
and 3.4, thinning the back surfaces of the encapsulation layer II and the through silicon via type adapter plate monomer by adopting a CMP grinding plate process until the bottom metal copper of the through silicon via type adapter plate monomer is exposed.
Further, in step 3.4, the thickness of the thinned through-silicon-via interposer monomer is 20±2 micrometers.
In the fourth step, a wafer-level fan-out process is adopted to package a plurality of chips on the through-silicon-via type adapter plate monomer, and the method concretely comprises the following steps:
step 4.1, etching a through silicon via type adapter plate monomer by adopting a dry etching (dry etching) process to ensure that the exposed height of a copper column in a through silicon via is h, so as to form an etching surface I;
step 4.2, covering the etching surface with a PI layer II;
step 4.3, etching the PI layer II by adopting a dry etching (dry etching) process to form an etched surface II which exposes the top end face of the copper column in the through silicon via, or adopting a CMP grinding piece process to expose the top end face of the copper column in the through silicon via;
step 4.4, covering a metal rewiring layer II on the etching surface II, wherein one end of the metal rewiring layer II is in telecommunication connection with the copper column in the through silicon via, and the other end of the metal rewiring layer II is provided with an output bonding pad II at the topmost layer;
step 4.5, adopting a flip-chip technology to sequentially flip-chip the prepared chips to the output bonding pads II of the metal rewiring layer II so as to enable the chips to be in telecommunication connection with the metal rewiring layer II;
step 4.6, filling the bottom of the chip and the space between the chip to form a filling layer II by adopting an underfilling process, and enhancing the fixedly connecting strength of the chip and the metal rewiring layer II by using a filling material;
step 4.7, integrally encapsulating all chips on the carrier wafer by adopting an encapsulating material to form an encapsulating layer III;
and 4.8, thinning the encapsulation layer III by adopting a CMP lapping process to form a CMP lapping process surface, and exposing the back surface of the chip.
Further, in step 4.5, the chip adopts a flip-chip technology, specifically: the single bare chip is inversely installed on the through silicon hole type adapter plate monomer, or the bare chips are inversely installed on the through silicon hole type adapter plate monomer respectively, or the single group of multi-layer stacked chip components are inversely installed on the through silicon hole type adapter plate monomer respectively, or the combination of the bare chip and the multi-layer stacked chip is inversely installed on the through silicon hole type adapter plate monomer respectively.
Further, in step 4.1, the copper pillars in the through silicon vias expose the through silicon vias interposer monomer, and the exposed height h is 5±2 micrometers.
Further, the front surface of the chip is provided with a BGA solder ball I or provided with a metal bump under the chip and the BGA solder ball I.
In the fifth step, the carrier wafer side is further thinned to expose the top end surface of the micro metal column of the through-silicon via type interposer monomer, and the specific process is as follows:
and (3) turning the packaging wafer in the step four up and down, packaging the back surface of the wafer by adopting a CMP lapping process, and removing the carrier wafer, the micro metal bumps and the temporary solder layer until the top end surfaces of the micro metal columns are exposed.
Advantageous effects
The invention provides a forming process of a chip packaging structure of a through silicon via type adapter plate, which adopts a carrier wafer, a micro-switching structure, underfills and encapsulating materials as supports, and the upper and lower lapping processes can enable the thickness of a single body of the through silicon via type adapter plate to be very thin and about 20 micrometers, so that the single body of the through silicon via type adapter plate has higher performance and smaller loss, and the chip packaging structure of the thinner through silicon via type adapter plate is formed;
the upper and lower parts of the through silicon via type adapter plate monomer are respectively provided with an encapsulating material structure, so that the upper and lower stress of the encapsulating structure can be balanced through the material characteristics, and the warping of the encapsulating structure is overcome;
meanwhile, the through silicon via type adapter plate single body adopts an upper grinding plate and lower grinding plate thinning process, so that the part possibly with a cavity in the bottom of the TSV can be effectively removed, and the reliability of the packaging structure is improved.
Drawings
FIG. 1 is a schematic diagram of a conventional TSV Interposer package structure;
FIG. 2 is a flow chart of a process for forming a chip package structure of a through-silicon via interposer according to the present invention;
fig. 3 to 23 are schematic process diagrams of a forming process of a chip package structure of a through-silicon via interposer according to an embodiment of the present invention;
in the figure: wafer 100
Through silicon via type interposer monomer 10
Through silicon vias 11
Through silicon via inner wall 111
Passivation layer 112
Seed layer 113
Copper column 114
Copper column top end surface 1141
Metal rewiring layer I21
Micro metal column 31
Micro metal column top end surface 311
Encapsulation layer I301
Temporary solder layer 32
Carrier wafer 500
Micro metal bump 51
Filling layer I510
Encapsulation layer II530
Thinned surface 531
Etching surface I533
PI layer II57
Etched surface II573
Metal rewiring layer II23
Chip 61
BGA solder ball I611
Encapsulation layer III620
CMP pad process surface 621
Temporary solder layer 32
Filling layer II610
BGA balls II35.
Detailed Description
The present application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
The invention provides a forming process of a chip packaging structure of a through silicon via type adapter plate, which is shown in fig. 2, and comprises the following steps:
step one: manufacturing a through silicon via type adapter plate single body through a wafer level process, wherein a micro-switching structure is arranged on the front surface of the through silicon via type adapter plate single body, and comprises a micro-metal column and a temporary solder layer arranged at the top end of the micro-metal column;
step two: adopting a stamping process to manufacture micro metal bumps on the front surface of a carrier wafer, wherein the micro metal bumps are in one-to-one correspondence with micro-switching structures of the through silicon via type switching plate monomers;
step three: the through silicon via type adapter plate monomer is subjected to flip-chip bonding and plastic packaging with a carrier wafer in sequence, and then the back surface of the through silicon via type adapter plate monomer is thinned;
step four: packaging a plurality of chips on a through silicon via type adapter plate monomer by adopting a wafer level fan-out process, wherein the chips are single bare chips or a plurality of bare chips, or single-group multi-layer stacked chip assemblies, or a plurality of groups of multi-layer stacked chip assemblies, or the combination of the bare chips and the multi-layer stacked chips;
step five: further thinning the wafer side of the carrier to expose the top end face of the micro metal column of the through silicon via type adapter plate monomer;
step six: the top end face of the micro metal column of the through silicon via type adapter plate monomer is provided with a BGA solder ball II;
step seven: dicing into a plurality of chip packaging structure monomers of the through silicon via type adapter plate.
The embodiment of the invention provides a forming process of a chip packaging structure of a through silicon via type interposer, which comprises the following processes, and please refer to fig. 3 to 23.
Step one, a through-silicon-via type adapter plate monomer 10 is manufactured through a wafer-level process, a micro-switching structure is arranged on the front surface of the through-silicon-via type adapter plate monomer 10, and the micro-switching structure comprises a micro metal column 31 and a temporary solder layer 32 arranged at the top end of the micro metal column, and the specific process is as follows:
in step 1.1, as shown in fig. 3, a conventional TSV interposer process is used to form an array of through-wafer vias with a certain depth on the front surface of the wafer 100, where the through-wafer vias 11 are arranged in an array, and the pitch and depth depend on the product requirements. The through silicon via 11 is blind hole-shaped, a passivation layer 112 and a seed layer 113 are sequentially deposited on the surface of the inner wall 111 of the through silicon via, and then metal, preferably metallic copper, is electroplated to form a copper pillar 114. The passivation layer 112 is silicon oxide or silicon nitride, or is formed in a thermal oxidation form, and has a thickness ranging from 10 nm to 1 μm. The seed layer 113 is fabricated above the insulating layer by physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer 113 ranges from 1 nanometer to 1 micrometer, the seed layer can be one layer or multiple layers, and the metal material of the seed layer 113 can be one or a combination of several of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like.
The front surface of the wafer 100 is firstly covered with a PI layer I with an insulating effect and provided with a PI window (not shown in a PI layer I diagram), then a re-wiring process is adopted to manufacture a metal re-wiring layer I21, the metal re-wiring layer I21 is connected with copper columns 114 in the through silicon vias 11 in a telecommunication way through the PI window, and an output bonding pad I (not shown in the diagram) is manufactured at the topmost layer of the metal re-wiring layer I; the specific number of metal rewiring layers I21 depends on the product requirements.
In step 1.2, as shown in fig. 4, a bump (bump manufacturing technology) process is used to manufacture micro metal pillars 31 on the output pads I of the metal rewiring layer I21, so as to form a micro metal pillar array.
In step 1.3, as shown in fig. 5, an encapsulation layer I301 is formed by encapsulating the metal rewiring layer I21 and the micro metal pillars 31 with an Encapsulant (EMC), and the top end surfaces 311 of the micro metal pillars are exposed by a CMP polishing process.
In step 1.4, as shown in fig. 6, a temporary solder layer 32 is disposed on the top end surface 311 of the micro metal pillar, and the micro metal pillar 31 and the temporary solder layer 32 form a micro-junction structure.
In step 1.5, as shown in fig. 7, the back surface of the wafer 100 is thinned by using a CMP lapping process, and diced into a plurality of through-silicon via interposer monomers 10.
And secondly, adopting a bumping (bump manufacturing technology) process to manufacture micro metal bumps 51 on the front surface of the carrier wafer 500 to form a micro metal bump array, wherein the micro metal bumps 51 are in one-to-one correspondence with the micro switching structures of the through silicon via type switching board single body 10. The specific process is as follows:
as shown in fig. 8, by adopting a bumping (bump manufacturing technology) process, micro metal bumps 51 are fabricated on the front surface of a carrier wafer 500, and the pitch and diameter of the micro metal bumps 51 are in one-to-one correspondence with those of the micro metal pillars 31 of the through-silicon via interposer unit 10, and the height is about 8 micrometers as compared with the conventional UBM height. Preferably, the cross-sectional dimension of the micro metal bump 51 is larger than or equal to the cross-sectional dimension of the micro metal column 31 to improve alignment accuracy.
Step three, the through-silicon via type interposer monomer 10 is flip-chip bonded with the carrier wafer 500 and plastic-sealed in sequence, and then the back surface of the through-silicon via type interposer monomer 10 is thinned to form a thinned surface 531. The specific process is as follows:
in step 3.1, as shown in fig. 9 and 10, the through-silicon via interposer monomers 10 are sequentially flipped onto the front surface of the carrier wafer 500, and the micro metal pillars 31 and the micro metal bumps 51 are soldered by the temporary solder layer 32.
In step 3.2, as shown in fig. 11, an underfill process is adopted between the through-silicon via interposer monomer 10 and the carrier wafer 500 to form a filling layer I510, and the bonding strength between the micro metal pillars 31 and the micro metal bumps 51 is enhanced by the filling material.
In step 3.3, as shown in fig. 12, an Encapsulation Material (EMC) is used to integrally encapsulate the through-silicon via interposer monomer 10 on the carrier wafer 500 to form an encapsulation layer II530.
In step 3.4, as shown in fig. 13, the back surfaces of the encapsulation layer II530 and the through-silicon via type interposer monomer 10 are thinned by using a CMP lapping process until the bottom metal copper of the through-silicon via type interposer monomer 10 is exposed, thereby forming a thinned surface 531. The thickness of the copper pillars 114 in the through-silicon vias 11 may be thinner, up to 20 microns, than the temporary bonding scheme may be, due to the support of the encapsulation layer I301, the fill layer I510, and the encapsulation layer II530. Meanwhile, the upper section with high reliability of the through silicon via 11 can be selected, the bottom of the cavity in the through silicon via 11, which is easy to exist, is removed, the packaging reliability is improved, and the process difficulty of the through silicon via in the first step is reduced.
Alternatively, in the first step, a high-quality TSV with a shallower depth may be formed on the front surface of the wafer, preferably, the height H1 of the copper pillar 114 of the through-silicon via 11 is 20±5 microns, and the current TSV process can ensure the high quality of the copper pillar 114 without voids, and can be directly used.
And step four, packaging a plurality of chips on the through silicon via type adapter plate monomer 10 by adopting a wafer level fan-out process, wherein the chips are single bare chips or a plurality of bare chips, or single-group multi-layer stacked chip assemblies, or a plurality of groups of multi-layer stacked chip assemblies, or the combination of the bare chips and the multi-layer stacked chips.
In step 4.1, as shown in fig. 14, a dry etching (dry etching) process (e.g. fluorine-containing gas) is used to etch the thinned surface 531, exposing a small section of the copper pillar 114 in the through silicon via 11 to form an etched surface I533, and preferably, the exposed height h of the copper pillar 114 is 5±2 microns.
In step 4.2, as shown in fig. 15, the etched surface 533 is covered with an insulating PI layer II57.
In step 4.3, as shown in fig. 16, the PI layer II57 is etched by a dry etching (dry etching) process again to form an etched surface II573 exposing the top end surface 1141 of the copper pillar in the through-silicon via 11.
Step 4.4, as shown in fig. 17, a metal rewiring layer II23 is fabricated on the etched surface II573, one end of the metal rewiring layer II23 is in telecommunication connection with the copper pillar 114 in the through silicon via 11, and the other end of the metal rewiring layer II is fabricated on the topmost layer thereof with an output pad II (the output pad II is not shown in the drawing); the specific number of layers of metal rewiring layer II23 depends on the product requirements.
Step 4.5, as shown in fig. 18, the prepared chips are sequentially flip-chip connected to the output pads II of the metal rewiring layer II23 by flip-chip technology, so that the chips are in telecommunication connection with the metal rewiring layer II 23. Generally, a Ball Grid Array (BGA) Ball I is disposed on the front surface of a chip or a metal bump under the chip and a BGA Ball I are disposed on the front surface of the chip. In the figure, two chips 61 are shown as a Ball Grid Array (BGA) structure, wherein a solder Ball I611 and a metal rewiring layer II23 are flip-chip bonded.
In this embodiment, a single bare chip is mounted on the through-silicon via type interposer monomer 10 in an inverted manner, or a plurality of bare chips are mounted on the through-silicon via type interposer monomer 10 in an inverted manner, or a single group of multi-layer stacked chip assemblies are mounted on the through-silicon via type interposer monomer 10 in an inverted manner, or a plurality of groups of multi-layer stacked chip assemblies are mounted on the through-silicon via type interposer monomer 10 in an inverted manner, or a combination of a bare chip and a multi-layer stacked chip is mounted on the through-silicon via type interposer monomer 10 in an inverted manner.
Step 4.6, as shown in fig. 19, an underfill process is used to fill the bottom of the chip and the space between the chips to form a filling layer II610, and the bonding strength between the chips and the metal rewiring layer II23 is enhanced by the filling material.
Step 4.7, as shown in fig. 20, the encapsulation layer III620 is formed by encapsulating all the chips integrally with an Encapsulant (EMC) on the carrier wafer 500.
In step 4.8, as shown in fig. 21, the encapsulation layer III620 is thinned by a CMP pad process to form a CMP pad process surface 621, exposing the back surface of the chip, so as to facilitate heat dissipation of the chip.
And fifthly, further thinning the carrier wafer 500 side to expose the micro metal column top end surface 311 of the through silicon via type interposer monomer 10.
Step 5.1, as shown in fig. 22, the package wafer is turned upside down, and the back surface of the package wafer is packaged by CMP lapping process, and the carrier wafer 500, the micro metal bumps 51 and the temporary solder layer 32 are removed until the micro metal pillar top surface 311 is exposed.
Step six, the top end surface 311 of the micro metal column of the through silicon via interposer monomer 10 is provided with a BGA (Ball Grid Array) solder Ball II35, as shown in fig. 23.
In the seventh step, the chip package structure unit of the through silicon via interposer is diced into a plurality of pieces, as shown in fig. 23, the package structure has the characteristics of thinner through silicon via interposer, low cost, short interconnection, high reliability and the like, and meanwhile, as the package layers I301, II530 and III620 of the package structure are made of the same material and are respectively arranged on the upper and lower sides of the package structure, the stress of the structure can be balanced, and experiments prove that the warpage of the package structure can be overcome, and the reliability of the package structure is improved.
The embodiment of the invention provides a chip packaging structure of a through silicon via type adapter plate, which is characterized in that one end of a traditional through silicon via type adapter plate is provided with a PI layer I and a PI window (not shown in a PI layer I diagram), a rewiring process is adopted to manufacture a metal rewiring layer I21, one end of the metal rewiring layer I21 is in telecommunication connection with a copper column 114 in a through silicon via 11 through the PI window, and the other end of the metal rewiring layer I is provided with an output bonding pad I (not shown in the diagram) at the topmost layer of the metal rewiring layer I; the specific number of metal rewiring layers I21 depends on the product requirements. And arranging a micro metal column 31 on the output bonding pad I, forming an encapsulation layer I301 by adopting an Encapsulation Material (EMC) plastic package metal rewiring layer I21 and the micro metal column 31, and exposing the top end face 311 of the micro metal column to form the through-silicon via type adapter plate. Around the through-silicon via interposer monomer 10 may be a filling layer I510 that remains during processing. The encapsulation layer II530 is formed by integrally molding the through-silicon via interposer monomer 10 with an Encapsulation Material (EMC). BGA (Ball Grid Array) solder balls II35 are arranged on the top end surface 311 of the micro metal column.
Etching a section of copper column 114 in the through silicon via 11 at the other end of the through silicon via type adapter plate, wherein the exposed height h of the copper column 114 is 5+/-2 microns. And covering the etched surface with an insulated PI layer II57 and opening the PI layer II. Manufacturing a metal rewiring layer II23 on the PI layer II57, wherein one end of the metal rewiring layer II23 is in telecommunication connection with a copper column 114 in the through silicon via 11, and the other end of the metal rewiring layer II is provided with an output bonding pad II (the output bonding pad II is not shown in the drawing) at the topmost layer; the specific number of layers of metal rewiring layer II23 depends on the product requirements.
And (3) the prepared chips are sequentially flipped to the output bonding pads II of the metal rewiring layer II23 by a flip-chip technology, so that the chips are in telecommunication connection with the metal rewiring layer II23, and the underfill is filled to form a filling layer II601.
Generally, a Ball Grid Array (BGA) Ball I is disposed on the front surface of a chip or a metal bump under the chip and a BGA Ball I are disposed on the front surface of the chip. In the figure, two chips 61 are shown as a Ball Grid Array (BGA) structure, wherein a solder Ball I611 and a metal rewiring layer II23 are flip-chip bonded. And integrally encapsulating all chips by using an Encapsulating Material (EMC) to form an encapsulating layer III620.
The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the technical scope of the present invention disclosed in the embodiments of the present invention should be covered by the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims (10)

1. A molding process of a chip packaging structure of a through silicon via type adapter plate comprises the following steps of,
step one, manufacturing a through-silicon-via type adapter plate single body through a wafer-level process, wherein a micro-switching structure is arranged on the front surface of the through-silicon-via type adapter plate single body, and the micro-switching structure comprises a micro-metal column and a temporary solder layer arranged at the top end of the micro-metal column;
secondly, adopting a stamping process to manufacture micro metal bumps on the front surface of the carrier wafer, wherein the micro metal bumps correspond to micro-switching structures of the through silicon via type switching plate single body one by one;
step three, the through-silicon-through-hole type adapter plate monomer is subjected to flip-chip bonding and plastic packaging with a carrier wafer in sequence, and then the back surface of the through-silicon-through-hole type adapter plate monomer is thinned;
packaging a plurality of chips on the through silicon via type adapter plate monomer by adopting a wafer level fan-out process, wherein the chips are single bare chips or a plurality of bare chips, or single-group multilayer stacked chip assemblies, or a plurality of groups of multilayer stacked chip assemblies, or the combination of the bare chips and the multilayer stacked chips;
step five, further thinning the wafer side of the carrier to expose the top end face of the micro metal column of the through silicon via type adapter plate monomer;
step six, arranging BGA solder balls II on the top end surfaces of the micro metal columns of the through silicon via type adapter plate monomers;
and step seven, dicing into a plurality of chip packaging structure monomers of the through silicon via type adapter plate.
2. The molding process according to claim 1, wherein in the first step, the through-silicon via interposer monomer is fabricated by a wafer, and the specific process is as follows:
step 1.1, a through silicon via array which does not penetrate through a wafer is formed on the front surface of the wafer by adopting a traditional TSV adapter plate process, metal copper is electroplated in the through silicon via to form a copper column, the front surface of the wafer is firstly covered with a PI layer I and a PI window is opened, then a re-wiring process is adopted to manufacture a metal re-wiring layer I, the metal re-wiring layer I is connected with the copper column in the through silicon via in a telecommunication way through the PI window downwards, and an output bonding pad I is manufactured on the topmost layer of the metal re-wiring layer I upwards;
step 1.2, adopting a stamping process to manufacture micro metal columns on an output bonding pad I of a metal rewiring layer I, and arranging a temporary solder layer on the top end face of each micro metal column;
and 1.3, thinning the wafer by adopting a CMP grinding process, and then scribing the wafer into a plurality of through-silicon-via type adapter plate monomers.
3. The forming process according to claim 2, wherein the cross-sectional dimension of the micro-metal bump is equal to or larger than the cross-sectional dimension of the micro-metal column.
4. The molding process according to claim 2 or 3, wherein in step three, the through-silicon via type interposer monomer is flip-chip bonded and plastic-sealed with a carrier wafer in sequence, and then the back surface of the through-silicon via type interposer monomer is thinned, specifically as follows:
step 3.1, sequentially flip-chip mounting the through-silicon-via type adapter plate monomers on the front surface of a carrier wafer, and welding the micro metal columns and the micro metal bumps through a temporary welding layer;
step 3.2, performing bottom filling between the through silicon via type adapter plate monomer and the carrier wafer by adopting an underfill filling process to form a filling layer I;
step 3.3, integrally molding a through silicon via type adapter plate monomer by adopting an encapsulating material on the carrier wafer to form an encapsulating layer II;
and 3.4, thinning the back surfaces of the encapsulation layer II and the through silicon via type adapter plate monomer by adopting a CMP grinding plate process until the bottom metal copper of the through silicon via type adapter plate monomer is exposed.
5. The molding process of claim 4, wherein in step 3.4, the thickness of the thinned through-silicon via interposer monomer is 20±2 microns.
6. The molding process of claim 4, wherein in step four, a wafer level fan-out process is used to package a plurality of chips on a through-silicon via interposer monomer, specifically as follows:
step 4.1, etching a through silicon via type adapter plate monomer by adopting a dry etching process to enable the exposed height of a copper column in the through silicon via to be h, so as to form an etching surface I;
step 4.2, covering the etching surface with a PI layer II;
step 4.3, etching the PI layer II by adopting a dry etching process again to form an etched surface II which exposes the top end face of the copper column in the through silicon via, or adopting a CMP lapping process to expose the top end face of the copper column in the through silicon via;
step 4.4, covering a metal rewiring layer II on the etching surface II, wherein one end of the metal rewiring layer II is in telecommunication connection with the copper column in the through silicon via, and the other end of the metal rewiring layer II is provided with an output bonding pad II at the topmost layer;
step 4.5, adopting a flip-chip technology to sequentially flip-chip the prepared chips to the output bonding pads II of the metal rewiring layer II so as to enable the chips to be in telecommunication connection with the metal rewiring layer II;
step 4.6, filling the bottom of the chip and the space between the chip to form a filling layer II by adopting an underfilling process, and enhancing the fixedly connecting strength of the chip and the metal rewiring layer II by using a filling material;
step 4.7, integrally encapsulating all chips on the carrier wafer by adopting an encapsulating material to form an encapsulating layer III;
and 4.8, thinning the encapsulation layer III by adopting a CMP lapping process to form a CMP lapping process surface, and exposing the back surface of the chip.
7. The molding process according to claim 6, wherein in step 4.5, the chip is flip-chip bonded, specifically: the single bare chip is inversely installed on the through silicon hole type adapter plate monomer, or the bare chips are inversely installed on the through silicon hole type adapter plate monomer respectively, or the single group of multi-layer stacked chip components are inversely installed on the through silicon hole type adapter plate monomer respectively, or the combination of the bare chip and the multi-layer stacked chip is inversely installed on the through silicon hole type adapter plate monomer respectively.
8. The process of claim 6, wherein in step 4.1, the copper pillars in the through-silicon vias expose the interposer monomers with a height h of 5±2 μm.
9. The molding process of claim 7, wherein the front side of the chip is provided with BGA balls I or with under-chip metal bumps and BGA balls I.
10. The molding process according to claim 6, wherein in the fifth step, the carrier wafer side is further thinned to expose the top end surface of the micro metal pillar of the through-silicon via type interposer monomer, and the specific process is as follows:
and (3) turning the packaging wafer in the step four up and down, packaging the back surface of the wafer by adopting a CMP lapping process, and removing the carrier wafer, the micro metal bumps and the temporary solder layer until the top end surfaces of the micro metal columns are exposed.
CN202410132889.2A 2024-01-31 2024-01-31 Forming process of chip packaging structure of through silicon via type adapter plate Active CN117672876B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202410132889.2A CN117672876B (en) 2024-01-31 2024-01-31 Forming process of chip packaging structure of through silicon via type adapter plate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202410132889.2A CN117672876B (en) 2024-01-31 2024-01-31 Forming process of chip packaging structure of through silicon via type adapter plate

Publications (2)

Publication Number Publication Date
CN117672876A true CN117672876A (en) 2024-03-08
CN117672876B CN117672876B (en) 2024-06-04

Family

ID=90064527

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202410132889.2A Active CN117672876B (en) 2024-01-31 2024-01-31 Forming process of chip packaging structure of through silicon via type adapter plate

Country Status (1)

Country Link
CN (1) CN117672876B (en)

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090200662A1 (en) * 2008-02-12 2009-08-13 United Test And Assembly Center Ltd Semiconductor package and method of making the same
WO2010080068A1 (en) * 2009-01-12 2010-07-15 Ravi Kanth Kolan Method for manufacturing a low cost three dimensional stack package and resulting structures using through silicon vias and assemblies
US20110042820A1 (en) * 2009-08-18 2011-02-24 International Business Machines Corporation 3d silicon-silicon die stack structure and method for fine pitch interconnection and vertical heat transport
KR20120091867A (en) * 2011-02-10 2012-08-20 삼성전자주식회사 Semiconductor package having coc(chip on chip) structure and method for fabricating the same package
WO2020090601A1 (en) * 2018-10-30 2020-05-07 凸版印刷株式会社 Semiconductor packaging wiring substrate and method of manufacturing semiconductor packaging wiring substrate
CN111446177A (en) * 2020-04-13 2020-07-24 上海先方半导体有限公司 System-level packaging method and structure of heterogeneous integrated chip
CN111900095A (en) * 2020-08-12 2020-11-06 上海先方半导体有限公司 Multi-chip integrated packaging method and packaging structure
CN112466829A (en) * 2020-12-11 2021-03-09 中芯长电半导体（江阴）有限公司 Chip packaging structure and preparation method thereof
CN112908947A (en) * 2021-01-18 2021-06-04 上海先方半导体有限公司 Plastic package structure and manufacturing method thereof
CN112908867A (en) * 2021-01-18 2021-06-04 上海先方半导体有限公司 2.5D packaging structure and manufacturing method thereof
CN113035824A (en) * 2019-12-25 2021-06-25 台湾积体电路制造股份有限公司 Semiconductor package
CN113990815A (en) * 2021-10-28 2022-01-28 西安微电子技术研究所 Silicon-based micro-module plastic package structure and preparation method thereof
US20220384212A1 (en) * 2020-05-01 2022-12-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor Package and Method of Manufacturing The Same
CN117116899A (en) * 2023-07-13 2023-11-24 浙江大学 Wafer-level integrated packaging structure and method for core particles
US20230402346A1 (en) * 2022-06-10 2023-12-14 Taiwan Semiconductor Manufacturing Co., Ltd. Heat dissipation structures for integrated circuit packages and methods of forming the same

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090200662A1 (en) * 2008-02-12 2009-08-13 United Test And Assembly Center Ltd Semiconductor package and method of making the same
WO2010080068A1 (en) * 2009-01-12 2010-07-15 Ravi Kanth Kolan Method for manufacturing a low cost three dimensional stack package and resulting structures using through silicon vias and assemblies
US20110042820A1 (en) * 2009-08-18 2011-02-24 International Business Machines Corporation 3d silicon-silicon die stack structure and method for fine pitch interconnection and vertical heat transport
KR20120091867A (en) * 2011-02-10 2012-08-20 삼성전자주식회사 Semiconductor package having coc(chip on chip) structure and method for fabricating the same package
WO2020090601A1 (en) * 2018-10-30 2020-05-07 凸版印刷株式会社 Semiconductor packaging wiring substrate and method of manufacturing semiconductor packaging wiring substrate
CN113035824A (en) * 2019-12-25 2021-06-25 台湾积体电路制造股份有限公司 Semiconductor package
CN111446177A (en) * 2020-04-13 2020-07-24 上海先方半导体有限公司 System-level packaging method and structure of heterogeneous integrated chip
US20220384212A1 (en) * 2020-05-01 2022-12-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor Package and Method of Manufacturing The Same
CN111900095A (en) * 2020-08-12 2020-11-06 上海先方半导体有限公司 Multi-chip integrated packaging method and packaging structure
CN112466829A (en) * 2020-12-11 2021-03-09 中芯长电半导体（江阴）有限公司 Chip packaging structure and preparation method thereof
CN112908867A (en) * 2021-01-18 2021-06-04 上海先方半导体有限公司 2.5D packaging structure and manufacturing method thereof
CN112908947A (en) * 2021-01-18 2021-06-04 上海先方半导体有限公司 Plastic package structure and manufacturing method thereof
CN113990815A (en) * 2021-10-28 2022-01-28 西安微电子技术研究所 Silicon-based micro-module plastic package structure and preparation method thereof
US20230402346A1 (en) * 2022-06-10 2023-12-14 Taiwan Semiconductor Manufacturing Co., Ltd. Heat dissipation structures for integrated circuit packages and methods of forming the same
CN117116899A (en) * 2023-07-13 2023-11-24 浙江大学 Wafer-level integrated packaging structure and method for core particles

Also Published As

Publication number Publication date
CN117672876B (en) 2024-06-04

Similar Documents

Publication Publication Date Title
US10985137B2 (en) Stacked integrated circuit structure and method of forming
US11967563B2 (en) Fan-out package having a main die and a dummy die
US20240250067A1 (en) Multi-die package structures including redistribution layers
KR102114454B1 (en) Semiconductor device package and method
CN110504247B (en) Integrated circuit package and method of forming the same
CN111799227B (en) Semiconductor device and method of forming the same
US9728522B2 (en) Integrated circuit packages and methods of forming same
US11810831B2 (en) Integrated circuit package and method of forming same
US11145562B2 (en) Package structure and method of manufacturing the same
CN113113365A (en) Microelectronic device including wafer level package
CN110610907A (en) Semiconductor structure and method of forming a semiconductor structure
CN114446900A (en) Package and method of manufacturing package structure
US20220336393A1 (en) Integrated circuit package and method of forming thereof
US20210175210A1 (en) Three-Dimensional Chip Packaging Structure And Method Thereof
CN117672876B (en) Forming process of chip packaging structure of through silicon via type adapter plate
US11984422B2 (en) Semiconductor package and method of forming same
TWI777732B (en) Semiconductor device package and method for forming semiconductor device package
CN117976548A (en) Chip packaging structure of composite through hole adapter plate and forming process thereof
KR20240124176A (en) Integrated circuit packages and methods of forming the same
CN118712156A (en) Semiconductor device and method of forming the same
CN116525558A (en) Package and method of forming the same
TW202345307A (en) Device package, semiconductor package and package method
CN116741730A (en) Semiconductor device and method of forming the same
CN118116882A (en) Integrated circuit package and method of forming the same
CN116598279A (en) Package, semiconductor package and method of forming the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant