CN116598279A

CN116598279A - Package, semiconductor package and method of forming the same

Info

Publication number: CN116598279A
Application number: CN202210975353.8A
Authority: CN
Inventors: 陈明发
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-04-13
Filing date: 2022-08-11
Publication date: 2023-08-15

Abstract

Semiconductor packages including hybrid bonding and solder bonding along a first interface and methods of forming the same are disclosed. In an embodiment, a package includes: a first interposer, the first interposer comprising a first redistribution structure; a first die bonded to the first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; a second die bonded to the first surface of the first redistribution structure with a first solder bond; an encapsulant around the first die and the second die; and a plurality of conductive connections on a second side of the first redistribution structure opposite the first die and the second die. Embodiments of the present application also relate to packages.

Description

Package, semiconductor package and method of forming the same

Technical Field

Embodiments of the present application relate to packages, semiconductor packages, and methods of forming the same.

Background

The semiconductor industry has experienced a rapid growth due to the ever-increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integration density is due to the iterative decrease in minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices continues to grow, there is a need for smaller, more innovative semiconductor die packaging techniques.

As semiconductor technology has further advanced, stacked and bonded semiconductor devices have become an effective alternative to further reduce the physical size of semiconductor devices. In stacked semiconductor devices, active circuits such as logic, memory, processor circuits, etc., are fabricated at least in part on separate substrates and then physically and electrically bonded together to form a functional device. Such bonding processes utilize complex techniques, and improvements are desired.

Disclosure of Invention

Some embodiments of the application provide a package comprising: a first interposer, wherein the first interposer comprises a first redistribution structure; a first die bonded to the first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; a second die bonded to the first surface of the first redistribution structure with a first solder bond; an encapsulant around the first die and the second die; and a plurality of conductive connections on a second side of the first redistribution structure opposite the first die and the second die.

Other embodiments of the present application provide a semiconductor package comprising: a first interface die; a second interface die adjacent to the first interface die; a first encapsulant extending from the first interface die to the second interface die; a first integrated circuit die bonded to the first interface die by a dielectric-to-dielectric bond and a metal-to-metal bond; and a second integrated circuit die bonded to the second interface die by a first solder bond.

Still further embodiments of the present application provide a method of forming a semiconductor package, comprising: providing a first interposer comprising a first interconnect structure on a first interposer substrate; bonding a first die to the first interconnect structure, wherein bonding the first die comprises directly bonding a first insulating layer of the first die to a bonding layer of the first interconnect structure and directly bonding a first die connector of the first die to a first bonding pad of the first interconnect structure; bonding a second die to the first interconnect structure, wherein bonding the second die comprises solder bonding a second die connector of the second die to a second bond pad of the first interconnect structure; and encapsulating the first die and the second die in a molding compound.

Drawings

The various aspects of the application are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates a cross-sectional view of an integrated circuit die according to some embodiments.

Fig. 2-26 illustrate cross-sectional views of intermediate steps during a process for forming a package assembly, according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as "under …," "under …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Various embodiments provide packaged semiconductor devices including hybrid bond types at a single interface and methods of forming the same. The method includes hybrid bonding a first die to an interface die and solder bonding a second die to the interface die adjacent to the first die. A molding compound may be formed around the first die and the second die, and surfaces of the first die, the second die, and the molding compound may be planarized. In some embodiments, the first die may be a logic die and the second die may be a memory die. In some embodiments, the second die may be a logic die, a passive device die, or a bridge die. The first die and the second die may be electrically coupled to each other through a redistribution layer of the interface die. Bonding the first die to the interface die using hybrid bonding allows for smaller pitch connections to be formed between the first die and the interface die, reduces the form factor of the package including the first die and the interface die, and improves device performance. Bonding the second die to the interface die using solder bonding reduces cost.

Fig. 1 illustrates a cross-sectional view of an integrated circuit die 50 according to some embodiments. The integrated circuit die 50 will be packaged in subsequent processing to form an integrated circuit package. The integrated circuit die 50 may be a logic die (e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a system on a chip (SoC), an Application Processor (AP), a microcontroller, etc.); memory die (e.g., dynamic Random Access Memory (DRAM) die, static Random Access Memory (SRAM) die, NAND flash die, etc.); a power management die (e.g., a Power Management Integrated Circuit (PMIC) die); a Radio Frequency (RF) die; a sensor die; a microelectromechanical system (MEMS) die; a signal processing die (e.g., a Digital Signal Processing (DSP) die); a front end die (e.g., an Analog Front End (AFE) die); an input-output (IO) die; bridging the die; etc.; or a combination thereof.

The integrated circuit die 50 may be formed in a wafer, which may include different device regions that are singulated in subsequent steps to form a plurality of integrated circuit die. The integrated circuit die 50 may be processed according to applicable manufacturing processes to form an integrated circuit. In some embodiments, the integrated circuit die 50 includes a semiconductor substrate 52, such as an active layer of a silicon (doped or undoped) or semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 52 may comprise other semiconductor materials such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor comprising SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP and/or GaInAsP; or a combination thereof. Other substrates may be used, such as a multilayer substrate or a gradient substrate. The semiconductor substrate 52 has an active surface (e.g., an upwardly facing surface in fig. 1) sometimes referred to as a front side and a non-active surface (e.g., a downwardly facing surface in fig. 1) sometimes referred to as a back side.

Devices (represented by transistors) 54 may be formed at the front side of semiconductor substrate 52. Device 54 may be an active device (e.g., transistor, diode, etc.), capacitor, resistor, etc. An interlayer dielectric (ILD) 56 is located on the front side of the semiconductor substrate 52. ILD 56 surrounds device 54 and may cover device 54.ILD 56 may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped Silicate Glass (USG), and the like.

Conductive plugs 58 extend through ILD 56 and are electrically and physically coupled to device 54. In embodiments where device 54 is a transistor, conductive plugs 58 may be coupled to the gate and source/drain regions (e.g., source regions and/or drain regions) of the transistor. The conductive plugs 58 may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, or the like, or combinations thereof. An interconnect structure 60 is formed over ILD 56 and conductive plug 58. Interconnect structure 60 interconnects devices 54 to form an integrated circuit. In some embodiments, interconnect structure 60 may be formed from a metallization pattern in a dielectric layer over ILD 56. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. The metallization pattern of interconnect structure 60 is electrically coupled to device 54 through conductive plugs 58.

The integrated circuit die 50 also includes pads 62, such as aluminum pads, made to external connections. Pads 62 are located on the front side of semiconductor substrate 52, such as in and/or on interconnect structure 60. One or more passivation films 64 are located on portions of the integrated circuit die 50, such as the interconnect structure 60 and the pads 62. The opening extends through passivation film 64 to pad 62. Die connections 66, such as conductive pillars (e.g., formed of a metal such as copper), extend through openings in passivation film 64. Die connectors 66 may be physically and electrically coupled to respective pads 62. The die connectors 66 may be formed by plating or the like. Die attach 66 is electrically coupled to the integrated circuit of integrated circuit die 50.

Solder regions (e.g., solder balls or solder bumps) may be disposed on the pads 62. Solder balls may be used to perform Chip Probe (CP) testing on the integrated circuit die 50. CP tests may be performed on integrated circuit die 50 to determine if integrated circuit die 50 is a Known Good Die (KGD). Thus, only the integrated circuit die 50 of KGD is subjected to subsequent processing and packaged. The die that failed the CP test are not packaged. After testing, the solder areas may be removed in a subsequent processing step.

Dielectric layer 68 may (or may not) be located on the front side of semiconductor substrate 52, such as passivation film 64 and die attach 66. Dielectric layer 68 laterally encapsulates die attach 66, and dielectric layer 68 is laterally co-terminal with semiconductor substrate 52. Initially, dielectric layer 68 may bury die attach 66 such that the topmost surface of dielectric layer 68 is above the topmost surface of die attach 66. In embodiments where a solder region is disposed on die attach 66, dielectric layer 68 may also bury the solder region. Alternatively, the solder regions may be removed prior to forming dielectric layer 68.

Dielectric layer 68 may be a polymer such as PBO, polyimide, BCB, or the like; nitrides, such as silicon nitride and the like; oxides such as silicon oxide, PSG, BSG, BPSG, etc.; etc., or a combination thereof. Dielectric layer 68 may be formed by spin coating, lamination, chemical Vapor Deposition (CVD), and the like. In some embodiments, die connectors 66 are exposed through dielectric layer 68 during formation of integrated circuit die 50. In some embodiments, die connectors 66 remain buried and exposed during subsequent processes for packaging integrated circuit die 50. Exposing the die connectors 66 may remove any solder regions that may be present on the die connectors 66.

In some embodiments, integrated circuit die 50 is a stacked device that includes a plurality of semiconductor substrates 52. For example, the integrated circuit die 50 may be a memory device including a plurality of memory dies, such as a hybrid memory multidimensional dataset (HMC) module, a High Bandwidth Memory (HBM) module, or the like. In such an embodiment, the integrated circuit die 50 includes a plurality of semiconductor substrates 52 interconnected by through-substrate vias (TSVs). Each of the semiconductor substrates 52 may (or may not) have an interconnect structure 60.

Fig. 2-11 illustrate cross-sectional views of intermediate steps during a process for forming a first package assembly 200 (shown in fig. 11), in accordance with some embodiments. One or more of the integrated circuit dies 50 may be packaged to form a first package assembly 200. The first package assembly 200 may be referred to as a chip on substrate (CoWoS) package or an integrated system on chip (SoIC) package.

In fig. 2, an interface die 111 is attached to the carrier substrate 100. The carrier substrate 100 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 100 may be a wafer so that a plurality of packages may be formed simultaneously on the carrier substrate 100. Although the interface die 111 is described as a die, the interface die 111 may be a wafer that may be subsequently singulated.

A release layer 102 is formed on a carrier substrate 100. The release layer 102 may be formed of a polymer-based material, which may be removed from the interface die 111 in a subsequent step together with the carrier substrate 100. In some embodiments, the release layer 102 is an epoxy-based heat release material that loses its adhesion when heated, such as a Light To Heat Conversion (LTHC) release coating. In some embodiments, the release layer 102 may be an Ultraviolet (UV) glue that loses its adhesion when exposed to UV radiation, such as radiation from UV light. The release layer 102 may be dispensed as a liquid and cured, may be a laminate film laminated to the carrier substrate 100, or the like. The top surface of the release layer 102 may be flush and may have a high degree of planarity.

The interface die 111 may include an interface substrate 110, a dielectric layer 112 on the interface substrate 110, and conductive vias 114 in the dielectric layer 112 and the interface substrate 110. The interface substrate 110 may be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multi-layer semiconductor substrate, or the like. The interface substrate 110 may comprise a semiconductor material, such as silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination thereof. Other substrates, such as a multilayer substrate or a gradient substrate, may also be used. The interface substrate 110 may be doped or undoped. In some embodiments, the interface substrate 110 is devoid of active devices, but the interface substrate 110 may include passive devices, sometimes referred to as front sides, formed in and/or on a front side (e.g., a surface facing downward in fig. 2) of the interface substrate 110. In embodiments where integrated circuits are formed in the interface substrate 110, active devices 113 such as transistors, diodes, etc., and passive devices such as capacitors, resistors, etc., may be formed in and/or on the front side of the interface substrate 110.

A dielectric layer 112 may be formed on the interface substrate 110. In some embodiments, the dielectric layer 112 is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, or the like, that may be patterned using a photolithographic mask. In some embodiments, dielectric layer 112 is comprised of a nitride such as silicon nitride; oxides such as silicon oxide, PSG, BSG, BPSG; etc. The dielectric layer 112 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof.

In some embodiments, the conductive vias 114 may be formed by forming recesses (not separately shown) in the dielectric layer 112 and the interface substrate 110. The grooves may be formed by etching, milling, laser techniques, combinations thereof, and the like. A dielectric material may be formed in the recess, such as by using an oxidation technique. The barrier layer may be conformally deposited in the opening, such as by CVD, atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), thermal oxidation, combinations thereof, and the like. The barrier layer may be formed of an oxide, nitride, carbide, combinations thereof, or the like. A conductive material may be deposited over the barrier layer and in the recess. The conductive material may be formed by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, or the like. Examples of conductive materials include copper, tungsten, aluminum, silver, gold, combinations thereof, and the like. A planarization process may be used to remove excess material of the conductive material, barrier layer, and dielectric material from the surface of the dielectric layer 112. The planarization process may be, for example, a Chemical Mechanical Polishing (CMP), a grinding process, an etch back process, etc. The barrier layer and the remaining portion of the conductive material form a conductive via 114.

In fig. 3, the backside of the interface substrate 110 is thinned. The interface substrate 110 may be thinned by a planarization process applied to the interface substrate 110 to expose the conductive vias 114. After the conductive via 114 is exposed, the conductive via 114 extends through the interface substrate 110 and may be referred to as a TSV. Planarization may remove the portion of interface substrate 110 opposite dielectric layer 112, thereby exposing conductive via 114. Planarization may be achieved by any suitable process, such as CMP, a grinding process, an etch back process, or the like, or a combination thereof. After planarization, the conductive vias 114 may extend completely through the interface substrate 110 and provide interconnection between opposite sides of the interface substrate 110.

In fig. 4, a backside interconnect structure 121 is formed on an interface substrate 110. The backside interconnect structure 121 includes a dielectric layer 116, a metallization layer 118 (also referred to as a redistribution layer or redistribution line) located in the dielectric layer 116, a dielectric layer 120, and a bond pad 122 located in the dielectric layer 120.

The backside interconnect structure 121 may include a plurality of metallization layers 118 separated from one another by respective layers of dielectric layers 116. The metallization layer 118 and the bond pads 122 of the backside interconnect structure 121 are electrically coupled to the conductive vias 114, and the respective metallization layer 118 may be physically coupled to the conductive vias 114.

In some embodiments, the dielectric layer 116 is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, BCB-based polymer, or the like, and may be patterned using a photolithographic mask. In some embodiments, dielectric layer 116 is comprised of a nitride such as silicon nitride; oxides such as silicon oxide, PSG, BSG, BPSG; etc. The dielectric layer 116 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof. After each dielectric layer 116 is formed, each dielectric layer 116 may be patterned to expose portions of underlying conductive features, such as underlying conductive vias 114 or underlying metallization layers 118. Patterning may be performed by any acceptable process. In embodiments where dielectric layer 116 comprises a photosensitive material, patterning may include exposing dielectric layer 116 to light. The dielectric layer 116 may be developed after exposure. In some embodiments, patterning dielectric layer 116 may include etching using anisotropic etching.

The metallization layers 118 each include conductive vias and/or wires. The conductive vias extend through the respective dielectric layers 116 and the conductive lines extend along the respective dielectric layers 116, such as on the top surfaces of the respective dielectric layers 116. As an example of forming the metallization layer 118, a seed layer (not separately shown) is formed over the respective underlying components. For example, a seed layer may be formed on the respective dielectric layer 116, in openings extending through the respective dielectric layer 116, and on underlying components such as the conductive vias 114 or the metallization layer 118. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using a deposition process such as PVD, CVD, or the like. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization layer 118. Openings are patterned through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating, such as electroless plating or electroplating from a seed layer. The conductive material may comprise a metal or metal alloy such as copper, titanium, tungsten, aluminum, or the like, or combinations thereof. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by any acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, an acceptable etching process (such as wet or dry etching) is used to remove the exposed portions of the seed layer. The seed layer and the remainder of the conductive material form a metallization layer 118.

Dielectric layer 116 and metallization layer 118 of backside interconnect structure 121 are shown as examples. By repeating or omitting the previously described steps, more or less dielectric layers 116 and metallization layers 118 than shown may be formed in the backside interconnect structure 121.

A dielectric layer 120 is formed over dielectric layer 116 and metallization layer 118. The dielectric layer 120 may be formed of a material suitable for achieving a dielectric-to-dielectric bond. In some embodiments, the dielectric layer 120 may include silicon oxide, silicon nitride, silicon oxynitride, or the like. Dielectric layer 120 may be deposited using a suitable deposition process such as PVD, CVD, ALD.

Bond pad 122 is formed in dielectric layer 120. Bond pads 122 are formed for external connection to the backside interconnect structure 121. Bond pad 122 may be formed on a top surface of dielectric layer 116 and extend along a top surface of dielectric layer 116. Bond pad 122 may be physically and electrically coupled to metallization layer 118. Bond pad 122 may be electrically coupled to conductive via 114 through metallization layer 118. The bond pads 122 may be formed of the same or similar material as the metallization layer 118 and by the same or similar process as the metallization layer 118. In some embodiments, the bond pad 122 has a different size (e.g., a different thickness) than the metallization layer 118. A planarization step may be performed to make the surface of the bond pad 122 flush with the surface of the dielectric layer 120.

In fig. 5, the first integrated circuit die 50A is bonded to the backside interconnect structure 121 by hybrid bonding. The desired type and number of integrated circuit dies 50 may be bonded to the backside interconnect structure 121 by hybrid bonding. In the illustrated embodiment, a single first integrated circuit die 50A is bonded to the backside interconnect structure 121. The first integrated circuit die 50A may be a logic device such as CPU, GPU, soC, a microcontroller, or the like.

The first integrated circuit die 50A is bonded to the backside interconnect structure 121 in a hybrid bonding configuration. The first integrated circuit die 50A is disposed face down such that the front side of the first integrated circuit die 50A faces the backside interconnect structure 121 and the backside of the first integrated circuit die 50A faces away from the backside interconnect structure 121. This may be referred to as a face-to-back configuration (F2B) because the face of the first integrated circuit die 50A faces the back of the interface die 111.

The dielectric layer 68 of the first integrated circuit die 50A may be directly bonded to the dielectric layer 120 and the die connectors 66 of the first integrated circuit die 50A may be directly bonded to the bond pads 122. In some embodiments, the bond between dielectric layer 68 and dielectric layer 120 is an oxide-to-oxide bond or the like. The hybrid bonding process further bonds die connectors 66 of first integrated circuit die 50A directly to bond pads 122 by direct metal-to-metal bonding. Thus, the first integrated circuit die 50A is electrically coupled to the backside interconnect structures 121 on the interface die 111 through the physical and electrical connections of the die connectors 66 and the bond pads 122. In some embodiments, the interface also includes an electrolyte-to-metal interface between the first integrated circuit die 50A and the backside interconnect structure 121 (e.g., when the die connectors 66 and the bond pads 122 are not fully aligned and/or have different widths).

As an example, the hybrid bonding process begins with the application of a surface treatment to dielectric layer 68 and/or dielectric layer 120. The surface treatment may comprise a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsing with deionized water, etc.) that may be applied to dielectric layer 68 and/or dielectric layer 120. The die connectors of the first integrated circuit die 50A may be aligned with the bond pads 122 of the backside interconnect structure 121. The die connectors 66 may overlap with corresponding bond pads 122. The pre-bonding step is performed by placing the first integrated circuit die 50A in contact with the dielectric layer 120 and corresponding bond pads 122 of the backside interconnect structure 121. The pre-bonding may be performed at room temperature (e.g., between about 21 ℃ and about 25 ℃). After pre-bonding, annealing is performed at a temperature between about 150 ℃ and about 400 ℃ for a duration between about 0.5 hours and about 3 hours. This causes the metal (e.g., copper) of die attach 66 and the metal (e.g., copper) of bond pad 122 to interdiffuse, forming a direct metal-to-metal bond.

The first integrated circuit die 50A is bonded to the backside interconnect structure 121 without the use of solder connections (e.g., micro bumps, etc.). By directly bonding the first integrated circuit die 50A to the backside interconnect structure 121, advantages such as finer bump pitch may be realized; a small form factor package through the use of hybrid bonding; smaller bond pitch scalability for chip I/O for high density die-to-die interconnects; improved mechanical durability; improved electrical performance; reduced defects; and increased yield. Further, a shorter die-to-die distance may be achieved between the first integrated circuit die 50A and other integrated circuit dies, with the benefits of smaller form factor, higher bandwidth, improved Power Integrity (PI), improved Signal Integrity (SI), and lower power consumption.

In fig. 6, a bond pad 126 is formed on the bond pad 122 and the dielectric layer 120 of the backside interconnect structure 121, and a conductive connection 128 is formed on the bond pad 126. Bond pad 126 may be formed by forming a seed layer (not separately shown) over bond pad 122 and dielectric layer 120. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using PVD or the like. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of photoresist corresponds to bond pad 126. Openings are patterned through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, and the like. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed using an acceptable etching process. The seed layer and the remaining portion of the conductive material form bond pads 126.

Conductive connections 128 are formed on the bond pads 126. Conductive connectors 128 may be Ball Grid Array (BGA) connectors, solder balls, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by electroless nickel-electroless palladium immersion gold technique (ENEPIG), or the like. The conductive connection 128 may be formed of a reflowable conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connection 128 is formed by initially forming a solder layer by evaporation, plating, printing, solder transfer, ball placement, and the like. Once the solder layer has been formed on the structure, reflow can be performed to shape the material into the desired bump shape. In some embodiments, the bond pad 126 may be omitted and the conductive connection 128 may be formed on the bond pad 122.

In fig. 7, the second integrated circuit die 50B is bonded to the backside interconnect structure 121 on the interface die 111 by solder bonding. The desired type and number of integrated circuit dies 50 may be bonded to the backside interconnect structure 121 by solder bonding. In the illustrated embodiment, a single second integrated circuit die 50B is bonded to the backside interconnect structure 121. The second integrated circuit die 50B may be a memory device such as a DRAM die, an SRAM die, a NAND flash die, an HMC module, an HBM module, or the like. Although the second integrated circuit die 50B is shown as a single integrated circuit die, the second integrated circuit die 50B may include a plurality of stacked integrated circuit dies (also referred to as a die stack).

The second integrated circuit die 50B is attached to the interface die 111 with solder bonding, such as with conductive connections 128. The second integrated circuit die 50B may be placed on the backside interconnect structure 121 using, for example, a pick and place tool. Attaching the second integrated circuit die 50B to the interface die 111 may include placing the second integrated circuit die 50B and the reflow conductive connections 128 on the interface die 111. Conductive connections 128 form joints between bond pads 126 on interface die 111 and die connections 66 of second integrated circuit die 50B, electrically coupling interface die 111 to second integrated circuit die 50B through backside interconnect structure 121.

An underfill material 129 may be formed around the conductive connection 128 and between the second integrated circuit die 50B and the backside interconnect structure 121. The underfill material 129 may reduce stress and protect the joint due to reflowing the conductive connection 128. The underfill material 129 may be formed of any suitable underfill material, such as a molding compound, epoxy, or the like. The underfill material 129 may be formed by a capillary flow process after the second integrated circuit die 50B is attached to the backside interconnect structure 121, or may be formed by a suitable deposition method before the second integrated circuit die 50B is attached to the backside interconnect structure 121. The underfill material 129 may be applied in liquid or semi-liquid form and subsequently cured. In some embodiments, the underfill material 129 is omitted, and the underfill material 129 is omitted in subsequent figures.

The first integrated circuit die 50A and the second integrated circuit die 50B may be formed by processes of the same technology node or may be formed by processes of different technology nodes. For example, the first integrated circuit die 50A may belong to a more advanced process node than the second integrated circuit die 50B. The first integrated circuit die 50A and the second integrated circuit die 50B may have different dimensions (e.g., different heights and/or surface areas), or may have the same dimensions (e.g., the same height and/or surface area). Other combinations of integrated circuit die 50 are possible. In some embodiments, the first integrated circuit die 50A and the second integrated circuit die 50B may have a thickness greater than about 100 μm.

The first integrated circuit die 50A and the second integrated circuit die 50B may be electrically coupled to each other through the interface die 111. The first integrated circuit die 50A is physically and electrically coupled to the backside interconnect structure 121 by hybrid bonding between the die connectors 66 and the bond pads 122, and the second integrated circuit die 50B is physically and electrically coupled to the backside interconnect structure 121 by solder bonding between the die connectors 66 and the bond pads 126. In some embodiments, the first integrated circuit die 50A may be a logic die and the second integrated circuit die 50B may be a memory die. The first integrated circuit die 50A has a relatively smaller pitch and higher circuit density of die connectors 66, while the second integrated circuit die 50B has a relatively larger pitch and lower circuit density of die connectors 66. Advantages such as finer bump pitch, higher bandwidth, and improved device performance are realized by bonding the first integrated circuit die 50A to the backside interconnect structure 121 by hybrid bonding. Bonding the second integrated circuit die 50B to the backside interconnect structure 121 by solder bonding reduces cost.

In fig. 8, an encapsulant 130 is formed over the backside interconnect structure 121 and around the first integrated circuit die 50A, the second integrated circuit die 50B, the conductive connections 128, the bond pads 126, and the interface die 111. After formation, encapsulant 130 encapsulates first integrated circuit die 50A, second integrated circuit die 50B, conductive connections 128, bond pads 126, underfill material (if present), and interface die 111. The encapsulant 130 may be a molding compound, an epoxy, or the like. The sealant 130 may be applied by compression molding, transfer molding, or the like. An encapsulant 130 is formed over the interface die 111 to bury or cover the first integrated circuit die 50A, the second integrated circuit die 50B, and the interface die 111. The encapsulant 130 is formed in a gap region between the first integrated circuit die 50A and the second integrated circuit die 50B. In embodiments where the underfill material is omitted, an encapsulant 130 may be formed around the conductive connections 128 and between the second integrated circuit die 50B and the backside interconnect structure 121. The sealant 130 may be applied in liquid or semi-liquid form and subsequently cured.

The encapsulant 130 is then thinned to expose the back sides of the first and second integrated circuit dies 50A, 50B. The thinning process may be a grinding process, CMP, etchback, combinations thereof, or the like. After the thinning process, the top surfaces of the first integrated circuit die 50A, the second integrated circuit die 50B, and the encapsulant 130 are coplanar (within process variations). Thinning is performed until a desired amount of the first integrated circuit die 50A, the second integrated circuit die 50B, and the encapsulant 130 have been removed. Specifically, the thinning removes portions of the encapsulant 130 that cover the top surfaces of the first and second integrated circuit dies 50A, 50B until no encapsulant 130 remains over the first and second integrated circuit dies 50A, 50B.

In fig. 9, the structure of fig. 8 is flipped; encapsulant 130, first integrated circuit die 50A, and second integrated circuit die 50B are attached to carrier substrate 140; and removing the carrier substrate 100 and the release layer 102. The device may be flipped such that the back sides of the first and second integrated circuit dies 50A, 50B face downward. Carrier substrate 140 may be bonded to encapsulant 130, first integrated circuit die 50A, and second integrated circuit die 50B through release layer 142. The carrier substrate 140 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 140 may be a wafer so that multiple packages may be processed simultaneously on the carrier substrate 140. The release layer 142 may be formed of a polymer-based material that may be removed along with the carrier substrate 140 from the above structure that will be formed in a subsequent step. In some embodiments, the release layer 142 is an epoxy-based heat release material that loses its adhesion when heated, such as LTHC release coating. In some embodiments, the release layer 142 may be a UV glue that loses its adhesion when exposed to UV radiation (such as radiation from UV light). The release layer 142 may be dispensed as a liquid and cured, may be a laminate film laminated to the release layer 142, or the like. The top surface of the release layer 142 may be flush and may have a high degree of planarity.

Carrier substrate peeling is performed to separate (or "peel") the carrier substrate 100 from the interface die 111 and encapsulant 130. In some embodiments, the stripping includes projecting light, such as laser or UV light, onto the release layer 102 such that the release layer 102 breaks down under the heat of the light and the carrier substrate 100 may be removed. As shown in fig. 9, the surfaces of the encapsulant 130, the conductive vias 114, and the dielectric layer 112 may be exposed after removal of the carrier substrate 100 and the release layer 102.

In fig. 10, a front side interconnect structure 150 is formed on the interface die 111 and encapsulant 130 opposite the carrier substrate 140. The front-side interconnect structure 150 includes a dielectric layer 152 and a metallization layer 154 (sometimes referred to as a redistribution layer or redistribution line) in the dielectric layer 152. For example, the front-side interconnect structure 150 may include a plurality of metallization layers 154 separated from one another by respective dielectric layers 152. The metallization layer 154 of the front-side interconnect structure 150 is electrically coupled to the conductive vias 114 of the interface die 111. The metallization layer 154 is electrically coupled to the first integrated circuit die 50A and the second integrated circuit die 50B through the conductive vias 114 and the backside interconnect structure 121. The first integrated circuit die 50A and the second integrated circuit die 50B may be electrically coupled to each other through the metallization layer 118 of the backside interconnect structure 121 and/or the metallization layer 154 of the front side interconnect structure 150.

In some embodiments, the dielectric layer 152 is formed of a polymer, which may be a photosensitive material such as PBO, polyimide, BCB-based polymer, or the like, and may be patterned using a photolithographic mask. In some embodiments, dielectric layer 152 is comprised of a nitride such as silicon nitride; oxides such as silicon oxide, PSG, BSG, BPSG; etc. The dielectric layer 152 may be formed by spin coating, lamination, CVD, or the like, or a combination thereof. After each dielectric layer 152 is formed, each dielectric layer 152 may be patterned to expose portions of underlying conductive features, such as underlying conductive vias 114 or underlying metallization layer 154. Patterning may be performed by any acceptable process. In embodiments where dielectric layer 152 comprises a photosensitive material, patterning may include exposing dielectric layer 152 to light. The dielectric layer 152 may be developed after exposure. In some embodiments, patterning the dielectric layer 152 may include etching using anisotropic etching.

The metallization layers 154 each include conductive vias and/or wires. The conductive vias extend through the respective dielectric layers 152 and the conductive lines extend along the respective dielectric layers 152, such as on top of the respective dielectric layers 152. As an example of forming the metallization layer 154, a seed layer (not separately shown) is formed over the respective underlying components. For example, a seed layer may be formed on the respective dielectric layer 152, in openings extending through the respective dielectric layer 152, and on underlying components such as the conductive vias 114 or the metallization layer 154. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using a deposition process such as PVD, CVD, or the like. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization layer 154. Openings are patterned through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating, such as electroless plating or electroplating from a seed layer. The conductive material may comprise a metal or metal alloy such as copper, titanium, tungsten, aluminum, or the like, or combinations thereof. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by any acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, an acceptable etching process (such as wet or dry etching) is used to remove the exposed portions of the seed layer. The seed layer and the remainder of the conductive material form a metallization layer 154.

Dielectric layer 152 and metallization layer 154 of front-side interconnect structure 150 are shown as examples. By repeating or omitting the previously described steps, more or less dielectric layers 152 and metallization layers 154 than shown may be formed in the front-side interconnect structure 150.

An Under Bump Metal (UBM) 156 is formed for external connection to the front side interconnect structure 150.UBM 156 includes a bump portion that is located on and extends along a top surface of an uppermost dielectric layer of dielectric layers 152 of front-side interconnect structure 150 and includes a via portion that extends through the uppermost dielectric layer of dielectric layers 152 of front-side interconnect structure 150. The via portion may be physically and electrically coupled to an uppermost metallization layer of the metallization layers 154 of the front-side interconnect structure 150.UBM 156 may be electrically coupled to conductive via 114, first integrated circuit die 50A, and second integrated circuit die 50B. UBM156 may be formed from the same or similar materials and processes as those used to form metallization layer 154. In some embodiments, UBM156 has a different size (such as a larger size) than metallization layer 154.

Conductive connection 158 is formed over UBM 156. Conductive connection 158 may be a BGA connection, solder ball, metal post, C4 bump, micro bump, bump formed by ENEPIG, or the like. The conductive connection 158 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or combinations thereof. In some embodiments, the conductive connection 158 is formed by initially forming a solder layer by evaporation, plating, printing, solder transfer, ball placement, and the like. Once the solder layer has been formed on the structure, reflow soldering can be performed to mold the material into the desired bump shape. In some embodiments, the conductive connection 158 includes a metal pillar (such as a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal posts may be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal overlayer may include nickel, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or the like, or combinations thereof, and may be formed by a plating process.

In fig. 11, carrier substrate 140 is removed and a heat spreader layer 159 is optionally formed over encapsulant 130, first integrated circuit die 50A, and second integrated circuit die 50B. The heat sink layer 159, encapsulant 130, first integrated circuit die 50A, second integrated circuit die 50B, and interface die 111 form a first package assembly 200. Carrier substrate peeling is performed to separate carrier substrate 140 from encapsulant 130, first integrated circuit die 50A, and second integrated circuit die 50B. In some embodiments, the stripping includes projecting light, such as laser or UV light, onto the release layer 142 such that the release layer 142 breaks down under the heat of the light and the carrier substrate 140 may be removed. As shown in fig. 11, the surfaces of encapsulant 130, first integrated circuit die 50A, and second integrated circuit die 50B may be exposed after carrier substrate 140 and release layer 142 are removed.

A heat spreading layer 159 is formed over encapsulant 130, first integrated circuit die 50A, and second integrated circuit die 50B. The heat dissipation layer 159 is formed of a material having high thermal conductivity, such as metal or metal nitride. In some embodiments, the heat sink layer 159 may be formed of aluminum, titanium nitride, nickel vanadium, silver, gold, copper, combinations thereof, and the like. The heat sink layer 159 may be formed by a PVD process, such as sputtering or evaporation; plating processes such as electroless plating or electroplating; printing processes such as inkjet printing; etc. to be conformally formed. In some embodiments, the heat sink layer 159 is formed of copper by a sputtering process. A heat dissipation layer 159 may be included to increase heat dissipation from the first integrated circuit die 50A and the second integrated circuit die 50B. In some embodiments, heat dissipation layer 159 may be formed over encapsulant 130, first integrated circuit die 50A, and second integrated circuit die 50B prior to attaching encapsulant 130, first integrated circuit die 50A, and second integrated circuit die 50B to carrier substrate 140. In some embodiments, the heat sink layer 159 may be omitted.

The inclusion of the first and second integrated circuit dies 50A, 50B that are bonded to the interface of the backside interconnect structure 121 by hybrid bonding and solder bonding, respectively, allows for the benefits of hybrid bonding and solder bonding. For example, hybrid bonding of the first integrated circuit die 50A allows die with small pitch to be bonded to the backside interconnect structure 121, providing higher bandwidth, and providing improved device performance. Solder bonding the second integrated circuit die 50B reduces cost while still providing a sufficiently small bonding pitch.

Fig. 2-11 illustrate embodiments in which the package has a face-to-back structure in which the integrated circuit die 50 has its front side facing the back side of the interface die 111. Fig. 12-15 illustrate embodiments in which the package has a face-to-face configuration in which the integrated circuit die 50 has a front face that faces the front face of the interface die 111. Fig. 12-15 illustrate cross-sectional views of intermediate steps during a process for forming a second package assembly 300 (shown in fig. 15), according to some embodiments.

In fig. 12, an interface die 111 is provided. The interface die 111 may be the same as or similar to the interface die 111 discussed above with respect to fig. 2. As shown in fig. 12, the interface die 111 may include an interface substrate 110, a dielectric layer 112 on a front side of the interface substrate 110, active devices 113 formed in and/or on the front side of the interface substrate 110, and conductive vias 114 extending through the dielectric layer 112 and into the interface substrate 110.

In fig. 13, a front side interconnect structure 160 is formed over interface die 111. The front side interconnect structure 160 includes a dielectric layer 162, a metallization layer 164 located in the dielectric layer 162, a dielectric layer 166, and a bond pad 168 located in the dielectric layer 166. The front-side interconnect structure 160 may be formed of the same or similar materials as those of the back-side interconnect structure 121 described above with respect to fig. 4 and formed using the same or similar processes as those of the back-side interconnect structure 121 described above with respect to fig. 4. Specifically, dielectric layer 162, metallization layer 164, dielectric layer 166, and bond pad 168 may be formed of the same or similar materials as dielectric layer 116, metallization layer 118, dielectric layer 120, and bond pad 122, respectively, and using the same or similar processes as dielectric layer 116, metallization layer 118, dielectric layer 120, and bond pad 122.

In fig. 14, a first integrated circuit die 50A and a second integrated circuit die 50B are bonded to a front-side interconnect structure 160, an underfill material 129 is optionally formed between the second integrated circuit die 50B and the front-side interconnect structure 160, and an encapsulant 130 is formed around the first integrated circuit die 50A and the second integrated circuit die 50B. The first integrated circuit die 50A may be bonded to the front-side interconnect structure 160 by hybrid bonding, as described above with respect to fig. 5. The second integrated circuit die 50B may be bonded to the front side interconnect structure 160 by solder bonding through the pads 126 and the conductive connections 128, as described above with respect to fig. 6 and 7. The underfill material 129 may be formed of the same or similar materials as the underfill material 129 described above with respect to fig. 7 and formed using the same or similar processes as the underfill material 129 described above with respect to fig. 7. The sealant 130 may be formed of the same or similar materials as the sealant 130 described above with respect to fig. 8 and formed using the same or similar processes as the sealant 130 described above with respect to fig. 8. Hybrid bonding the first integrated circuit die 50A allows die with small pitch to be bonded to the front side interconnect structure 160, providing higher bandwidth, and providing improved device performance. Solder bonding the second integrated circuit die 50B reduces cost while still providing a sufficiently small bonding pitch.

In fig. 15, the backside of the interface substrate 110 is thinned, backside interconnect structures 170 are formed on the backside of the interface substrate 110, and a heat spreader layer 159 is optionally formed over the encapsulant 130, the first integrated circuit die 50A, and the second integrated circuit die 50B. The heat spreader layer 159, encapsulant 130, first integrated circuit die 50A, second integrated circuit die 50B, and interface die 111 form a second package assembly 300. The interface substrate 110 may be thinned by a planarization process applied to the interface substrate 110 to expose the conductive vias 114. After the conductive via 114 is exposed, the conductive via 114 extends through the interface substrate 110 and may be referred to as a TSV. Planarization may remove the portion of interface substrate 110 opposite dielectric layer 112, thereby exposing conductive via 114. Planarization may be achieved by any suitable process, such as CMP, a grinding process, an etch back process, or the like, or a combination thereof. After planarization, the conductive vias 114 may extend completely through the interface substrate 110 and provide interconnection between opposite sides of the interface substrate 110.

The backside interconnect structure 170 may be formed of the same or similar materials and using the same or similar processes as those of the front side interconnect structure 150 described above with respect to fig. 10. The backside interconnect structure 170 includes a dielectric layer 172 and a metallization layer 174 located in the dielectric layer 172. Dielectric layer 172 and metallization layer 174 may be formed of the same or similar materials as dielectric layer 152 and metallization layer 154, respectively, and using the same or similar processes as dielectric layer 152 and metallization layer 154.

UBM 176 and conductive connection 178 are formed for external connection to backside interconnect structure 170.UBM 176 and conductive connection 178 may be formed of the same or similar materials as UBM 156 and conductive connection 158, respectively, discussed above with respect to fig. 10, and using the same or similar processes as UBM 156 and conductive connection 158, discussed above with respect to fig. 10. UBM 176 includes a bump portion that is located on a top surface of an uppermost dielectric layer of dielectric layers 172 of back-side interconnect structure 170 and extends along a top surface of an uppermost dielectric layer of dielectric layers 172 of back-side interconnect structure 170, and includes a via portion that extends through an uppermost dielectric layer of dielectric layers 172 of back-side interconnect structure 170. The via portion may be physically and electrically coupled to an uppermost metallization layer of the metallization layers 174 of the backside interconnect structure 170.UBM 176 may be electrically coupled to conductive via 114, first integrated circuit die 50A, and second integrated circuit die 50B.

The first and second integrated circuit dies 50A, 50B including interfaces that are bonded to the front-side interconnect structure 160 by hybrid bonding and solder bonding, respectively, allow for the benefits of hybrid bonding and solder bonding. For example, hybrid bonding of the first integrated circuit die 50A allows die with small pitch to be bonded to the front side interconnect structure 160, providing higher bandwidth, and providing improved device performance. Solder bonding the second integrated circuit die 50B reduces cost while still providing a sufficiently small bonding pitch.

Fig. 16-21 illustrate an embodiment in which three integrated circuit dies 50 are bonded to two interface dies 111. Specifically, as shown in fig. 19, a first integrated circuit die 50A is hybrid bonded on a first interface die 111A, a second integrated circuit die 50B is solder bonded on the first interface die 111A and the second interface die 111B, and a third integrated circuit die 50C is solder bonded on the second interface die 111B. Fig. 16-21 illustrate embodiments in which the package has a face-to-back structure in which the integrated circuit die 50 has its front side facing the back side of the interface die 111. Fig. 16-21 illustrate cross-sectional views of intermediate steps during a process for forming a third package assembly 400 (shown in fig. 21), according to some embodiments.

In fig. 16, a first interface die 111A and a second interface die 111B are attached to the carrier substrate 100. The front sides of the first interface die 111A and the second interface die 111B are attached to the carrier substrate 100 by the release layer 102. The carrier substrate 100 and the release layer 102 may be formed of the same or similar materials as the carrier substrate 100 and the release layer 102, respectively, described above with respect to fig. 2 and using the same or similar processes as the carrier substrate 100 and the release layer 102, respectively, described above with respect to fig. 2. The first interface die 111A and the second interface die 111B may be the same or similar to the interface die 111 described above with respect to fig. 2. Each of the first interface die 111A and the second interface die 111B may include an interface substrate 110, a dielectric layer 112 on a front side of the interface substrate 110, active devices 113 formed in and/or on the front side of the interface substrate 110, and conductive vias 114 extending through the dielectric layer 112 and into the interface substrate 110. The first interface die 111A and the second interface die 111B may be laterally adjacent to each other and may be separated by a gap.

A backside interconnect structure 121 is formed over the backside of each of the first interface die 111A and the second interface die 111B. Backside interconnect structure 121 includes dielectric layer 116, metallization layer 118 located in dielectric layer 116, dielectric layer 120, and bond pad 122 located in dielectric layer 120. The metallization layer 118 is electrically coupled to the conductive vias 114 of the first interface die 111A and the second interface die 111B. The bond pads 122 are electrically coupled to the metallization layer 118 and electrically coupled to the conductive vias 114 of the first interface die 111A and the second interface die 111B through the metallization layer 118. The backside interconnect structure 121 may be formed of the same or similar materials as those of the backside interconnect structure 121 described above with respect to fig. 4 and formed using the same or similar processes as those of the backside interconnect structure 121 described above with respect to fig. 4. Specifically, dielectric layer 116, metallization layer 118, dielectric layer 120, and bond pad 122 may be formed of the same or similar materials as dielectric layer 116, metallization layer 118, dielectric layer 120, and bond pad 122, respectively, and using the same or similar processes as dielectric layer 116, metallization layer 118, dielectric layer 120, and bond pad 122.

In fig. 17, a first encapsulant 131 is formed over release layer 102 and around first interface die 111A and second interface die 111B. A first encapsulant 131 is deposited over the release layer 102 and around the first interface die 111A, the second interface die 111B, and the backside interconnect structure 121. After formation, the first encapsulant 131 encapsulates the first interface die 111A, the second interface die 111B, and the backside interconnect structure 121. The first sealant 131 may be a molding compound, an epoxy, or the like. The first sealant 131 may be applied by compression molding, transfer molding, or the like. A first encapsulant 131 is formed over the release layer 102 to bury or cover the first interface die 111A, the second interface die 111B, and the backside interconnect structure 121. The first encapsulant 131 is formed in the gap regions between the first interface die 111A and the second interface die 111B and between the backside interconnect structures 121. The first sealant 131 may be applied in liquid or semi-liquid form and then cured.

The first encapsulant 131 is then thinned to expose the bond pads 122 of the backside interconnect structure 121. The thinning process may be a grinding process, CMP, etchback, combinations thereof, or the like. After the thinning process, the first encapsulant 131, the bond pads 122, and the top surface of the dielectric layer 120 are coplanar (within process variations). Thinning is performed until bond pad 122 is exposed. In some embodiments, the thinning removes portions of the first encapsulant 131 that cover the backside interconnect structure 121 until no first encapsulant 131 remains over the backside interconnect structure 121.

In fig. 18, a first integrated circuit die 50A is bonded to a backside interconnect structure 121 over a first interface die 111A by hybrid bonding. The desired type and number of integrated circuit dies 50 can be bonded to the backside interconnect structure 121, such as one or more of the first integrated circuit dies 50A, by hybrid bonding. In the illustrated embodiment, a single first integrated circuit die 50A is bonded to the backside interconnect structure 121. The first integrated circuit die 50A may be a logic device such as CPU, GPU, soC, a microcontroller, or the like.

The first integrated circuit die 50A is bonded to the backside interconnect structure 121 in a hybrid bonding configuration. The first integrated circuit die 50A is disposed face down such that the front side of the first integrated circuit die 50A faces the backside interconnect structure 121 and the backside of the first integrated circuit die 50A faces away from the backside interconnect structure 121. This may be referred to as a face-to-back configuration (F2B) because the face of the first integrated circuit die 50A faces the back of the first interface die 111A. The dielectric layer 68 of the first integrated circuit die 50A may be directly bonded to the dielectric layer 120 and the die connectors 66 of the first integrated circuit die 50A may be directly bonded to the bond pads 122.

In fig. 19, bond pads 126 are formed on the backside interconnect structure 121 over the first interface die 111A and the second interface die 111B, the second integrated circuit die 50B is bonded to the backside interconnect structure 121 over the first interface die 111A and the second interface die 111B by solder bonding, and the third integrated circuit die 50C is bonded to the backside interconnect structure 121 over the second interface die 111B by solder bonding. The bond pads 126 and the conductive connections 128 may be formed over the backside interconnect structure 121 from the same or similar materials as those of the bond pads 126 and the conductive connections 128, respectively, described above with respect to fig. 6 and over the backside interconnect structure 121 using the same or similar processes as those of the bond pads 126 and the conductive connections 128, described above with respect to fig. 6.

The desired type and number of integrated circuit dies 50 can be bonded to the backside interconnect structure 121 by solder bonding, such as one or more of the second integrated circuit dies 50B and one or more of the third integrated circuit dies 50C. In the illustrated embodiment, a single second integrated circuit die 50B is bonded to the first interface die 111A and the backside interconnect structure 121 over the second interface die 111B, and a single third integrated circuit die 50C is bonded to the backside interconnect structure 121 over the second interface die 111B. The second integrated circuit die 50B may be a bridge die, which may be a logic device or a passive device. In embodiments in which the second integrated circuit die 50B is a logic device, the second integrated circuit die 50B may be CPU, GPU, soC, a microcontroller, or the like. In embodiments in which the second integrated circuit die 50B is a passive device, the second integrated circuit die 50B may be an input-output (IO) die, SED die, or the like. The third integrated circuit die 50C may be a memory device such as a DRAM die, an SRAM die, a NAND flash die, an HMC module, an HBM module, or the like. Although the third integrated circuit die 50C is shown as a single integrated circuit die, the third integrated circuit die 50C may include multiple stacked integrated circuit dies (also referred to as a die stack).

The second integrated circuit die 50B and the third integrated circuit die 50C are attached to the backside interconnect structure 121 with solder bonds, such as with conductive connections 128. The second integrated circuit die 50B and the third integrated circuit die 50C may be placed on the backside interconnect structure 121 using, for example, pick and place tools. Attaching the second and third integrated circuit dies 50B, 50C to the backside interconnect structure 121 may include placing the second and third integrated circuit dies 50B, 50C and the reflow conductive connections 128 on the backside interconnect structure 121. Conductive connections 128 form joints between bond pads 126 on backside interconnect structure 121 and die connections 66 of second integrated circuit die 50B and third integrated circuit die 50C, electrically coupling first interface die 111A and second interface die 111B to second integrated circuit die 50B and third integrated circuit die 50C through backside interconnect structure 121.

An underfill material 129 may be formed around the conductive connection 128 and between the backside interconnect structure 121 and each of the second integrated circuit die 50B and the third integrated circuit die 50C. As shown in FIG. 19, the underfill material 129 may be a continuous material, or two different, discontinuous materials. The underfill material 129 may reduce stress and protect the joint due to reflowing the conductive connection 128. The underfill material 129 may be formed of any suitable underfill material, such as a molding compound, epoxy, or the like. The underfill material 129 may be formed by a capillary flow process after the second and third integrated circuit dies 50B and 50C are attached to the backside interconnect structure 121, or may be formed by a suitable deposition method before the second and third integrated circuit dies 50B and 50C are attached to the backside interconnect structure 121. The underfill material 129 may be applied in liquid or semi-liquid form and subsequently cured. In some embodiments, the underfill material 129 is omitted, and the underfill material 129 is omitted in subsequent figures.

The first integrated circuit die 50A, the second integrated circuit die 50B, and the third integrated circuit die 50C may be formed by processes of the same technology node, or may be formed by processes of different technology nodes. For example, the first integrated circuit die 50A may belong to a more advanced process node than the second integrated circuit die 50B and/or the third integrated circuit die 50C. The first integrated circuit die 50A, the second integrated circuit die 50B, and/or the third integrated circuit die 50C may have different dimensions (e.g., different heights and/or surface areas), or may have the same dimensions (e.g., the same height and/or surface area). Other combinations of integrated circuit dies are also possible. In some embodiments, the first integrated circuit die 50A, the second integrated circuit die 50B, and the third integrated circuit die 50C may have a thickness greater than about 100 μm.

The first integrated circuit die 50A and the third integrated circuit die 50C may be electrically coupled to each other through the backside interconnect structure 121 and the second integrated circuit die 50B. The first integrated circuit die 50A is physically and electrically coupled to the backside interconnect structure 121 on the first interface die 111A by hybrid bonding between the die connectors 66 and the bond pads 122. The second integrated circuit die 50B is physically and electrically coupled to the backside interconnect structures 121 on the first interface die 111A and the second interface die 111B by solder bonding between the die connectors 66 and the bond pads 126. The third integrated circuit die 50C is physically and electrically coupled to the backside interconnect structure 121 on the second interface die 111B by solder bonding between the die connectors 66 and the bond pads 126. In some embodiments, the first integrated circuit die 50A may be a logic die, the second integrated circuit die 50B may be a bridge die, and the third integrated circuit die 50C may be a memory die. The first integrated circuit die 50A has a relatively smaller pitch and higher circuit density of die connectors 66, while the second and third integrated circuit dies 50B, 50C have a relatively larger pitch and lower circuit density of die connectors 66. Advantages such as finer bump pitch, higher bandwidth, and improved device performance are realized by bonding the first integrated circuit die 50A to the backside interconnect structure 121 by hybrid bonding. Bonding the second and third integrated circuit dies 50B, 50C to the backside interconnect structure 121 by solder bonding reduces cost.

In fig. 20, a second encapsulant 133 is formed over the first interface die 111A, the second interface die 111B, and the first encapsulant 131 and around the first integrated circuit die 50A, the second integrated circuit die 50B, and the third integrated circuit die 50C. The second encapsulant 133 may be formed of the same or similar materials as the encapsulant 130 described above with respect to fig. 8 and formed using the same or similar process as the encapsulant 130 described above with respect to fig. 8. The second encapsulant 133 may be thinned to expose the back sides of the first, second, and third integrated circuit dies 50A, 50B, 50C.

In fig. 21, the carrier substrate 100 is removed; forming a front-side interconnect structure 150 on the front sides of the first interface die 111A and the second interface die 111B; and optionally forming a heat sink layer 159 over the second encapsulant 133, the first integrated circuit die 50A, the second integrated circuit die 50B, and the third integrated circuit die 50C. The heat spreader 159, encapsulant 130, first integrated circuit die 50A, second integrated circuit die 50B, third integrated circuit die 50C, first interface die 111A, and second interface die 111B form a third package assembly 400. Carrier substrate lift-off is performed to separate the carrier substrate 100 from the first interface die 111A, the second interface die 111B, and the first encapsulant 131. In some embodiments, the stripping includes projecting light, such as laser or UV light, onto the release layer 102 such that the release layer 102 breaks down under the heat of the light and the carrier substrate 100 may be removed. As shown in fig. 21, the surfaces of the first interface die 111A, the second interface die 111B, and the first encapsulant 131 may be exposed after removing the carrier substrate 100 and the release layer 102.

The front side interconnect structure 150 may be formed of the same or similar materials as those of the front side interconnect structure 150 described above with respect to fig. 10 and formed using the same or similar processes as those of the front side interconnect structure 150 described above with respect to fig. 10. The front side interconnect structure 150 includes a dielectric layer 152 and a metallization layer 154 located in the dielectric layer 152. The dielectric layer 152 and the metallization layer 154 may be formed of the same or similar materials as the dielectric layer 152 and the metallization layer 154, respectively, and using the same or similar processes as the dielectric layer 152 and the metallization layer 154.

UBM 156 and conductive connection 158 are formed for external connection to front-side interconnect structure 150.UBM 156 and conductive connection 158 may be formed of the same or similar materials as UBM 156 and conductive connection 158, respectively, discussed above with respect to fig. 10, and using the same or similar processes as UBM 156 and conductive connection 158, discussed above with respect to fig. 10. UBM 156 includes a bump portion that is located on and extends along a top surface of an uppermost dielectric layer of dielectric layers 152 of front-side interconnect structure 150 and includes a via portion that extends through the uppermost dielectric layer of dielectric layers 152 of front-side interconnect structure 150. The via portion may be physically and electrically coupled to an uppermost metallization layer of the metallization layers 154 of the front-side interconnect structure 150.UBM 156 may be electrically coupled to conductive via 114, first integrated circuit die 50A, second integrated circuit die 50B, and third integrated circuit die 50C.

A heat spreading layer 159 is formed over the second encapsulant 133, the first integrated circuit die 50A, the second integrated circuit die 50B, and the third integrated circuit die 50C. The heat dissipation layer 159 is formed of a material having high thermal conductivity, such as metal or metal nitride. In some embodiments, the heat sink layer 159 may be formed of aluminum, titanium nitride, nickel vanadium, silver, gold, copper, combinations thereof, and the like. The heat sink layer 159 may be formed by a PVD process, such as sputtering or evaporation; plating processes such as electroless plating or electroplating; printing processes such as inkjet printing; and the like. In some embodiments, the heat sink layer 159 is formed of copper by a sputtering process. A heat spreading layer 159 may be included to increase heat spreading from the first integrated circuit die 50A, the second integrated circuit die 50B, and the third integrated circuit die 50C. In some embodiments, heat spreader layer 159 may be formed over second encapsulant 133, first integrated circuit die 50A, second integrated circuit die 50B, and third integrated circuit die 50C prior to removing carrier substrate 100. In some embodiments, the heat sink layer 159 may be omitted.

The inclusion of the first integrated circuit die 50A that is hybrid bonded to the backside interconnect structure 121 over the first interface die 111A and the second and third integrated circuit dies 50B, 50C that are solder bonded to the backside interconnect structure 121 over the first and second interface dies 111A, 111B allows for the benefits of hybrid bonding and solder bonding. For example, hybrid bonding of the first integrated circuit die 50A allows die with small pitch to be bonded to the backside interconnect structure 121, providing higher bandwidth, and providing improved device performance. Solder bonding the second and third integrated circuit dies 50B, 50C reduces cost while still providing a sufficiently small bonding pitch.

Fig. 22-26 illustrate an embodiment in which three integrated circuit dies 50 are bonded to two interface dies 111. Specifically, as shown in fig. 19, a first integrated circuit die 50A is hybrid bonded on a first interface die 111A, a second integrated circuit die 50B is solder bonded on the first interface die 111A and the second interface die 111B, and a third integrated circuit die 50C is solder bonded on the second interface die 111B. Fig. 22-26 illustrate embodiments in which the package has a face-to-face configuration in which the integrated circuit die 50 has its front face facing the front face of the interface die 111. Fig. 22-26 illustrate cross-sectional views of intermediate steps during a process for forming a fourth package assembly 500 (shown in fig. 26), according to some embodiments.

In fig. 22, a first interface die 111A and a second interface die 111B are attached to the carrier substrate 100. The back sides of the first interface die 111A and the second interface die 111B are attached to the carrier substrate 100 by the release layer 102. The carrier substrate 100 and the release layer 102 may be formed of the same or similar materials as the carrier substrate 100 and the release layer 102, respectively, described above with respect to fig. 2 and using the same or similar processes as the carrier substrate 100 and the release layer 102, respectively, described above with respect to fig. 2. The first interface die 111A and the second interface die 111B may be the same or similar to the interface die 111 described above with respect to fig. 2. Each of the first interface die 111A and the second interface die 111B may include an interface substrate 110, a dielectric layer 112 on a front side of the interface substrate 110, active devices 113 formed in and/or on the front side of the interface substrate 110, and conductive vias 114 extending through the dielectric layer 112 and into the interface substrate 110. The first interface die 111A and the second interface die 111B may be laterally adjacent to each other and may be separated by a gap.

A front side interconnect structure 160 is formed over the front side of each of the first interface die 111A and the second interface die 111B. The front side interconnect structure 160 includes a dielectric layer 162, a metallization layer 164 located in the dielectric layer 162, a dielectric layer 166, and a bond pad 168 located in the dielectric layer 166. The metallization layer 164 is electrically coupled to the conductive vias 114 of the first interface die 111A and the second interface die 111B. The bond pad 168 is electrically coupled to the metallization layer 164 and electrically coupled to the conductive vias 114 of the first interface die 111A and the second interface die 111B through the metallization layer 164. The front-side interconnect structure 160 may be formed of the same or similar materials as those of the back-side interconnect structure 121 described above with respect to fig. 4 and formed using the same or similar processes as those of the back-side interconnect structure 121 described above with respect to fig. 4. Specifically, dielectric layer 162, metallization layer 164, dielectric layer 166, and bond pad 168 may be formed of the same or similar materials as dielectric layer 116, metallization layer 118, dielectric layer 120, and bond pad 122, respectively, and using the same or similar processes as dielectric layer 116, metallization layer 118, dielectric layer 120, and bond pad 122.

A first encapsulant 131 is formed over the release layer 102 and around the first interface die 111A and the second interface die 111B. The first sealant 131 may be formed of the same or similar materials as the first sealant 131 discussed above with respect to fig. 17 and formed using the same or similar processes as the first sealant 131 discussed above with respect to fig. 17. The first encapsulant 131 is thinned to expose the bond pads 168 of the front side interconnect structure 160. After the thinning process, the top surfaces of the first encapsulant 131, bond pad 168, and dielectric layer 166 are coplanar (within process variations). Thinning is performed until bond pad 168 is exposed. In some embodiments, the thinning removes portions of the first encapsulant 131 that cover the front-side interconnect structure 160 until no first encapsulant 131 remains over the front-side interconnect structure 160.

In fig. 23, a first integrated circuit die 50A is bonded to a front side interconnect structure 160 over a first interface die 111A by hybrid bonding. The desired type and number of integrated circuit dies 50 can be bonded to the front-side interconnect structure 160, such as one or more of the first integrated circuit dies 50A, by hybrid bonding. In the illustrated embodiment, a single first integrated circuit die 50A is bonded to the front-side interconnect structure 160. The first integrated circuit die 50A may be a logic device such as CPU, GPU, soC, a microcontroller, or the like.

The first integrated circuit die 50A is bonded to the front side interconnect structure 160 in a hybrid bonding configuration. The first integrated circuit die 50A is disposed face down such that the front side of the first integrated circuit die 50A faces the front side interconnect structure 160 and the back side of the first integrated circuit die 50A faces away from the front side interconnect structure 160. This may be referred to as a face-to-face configuration (F2F) because the face of the first integrated circuit die 50A faces the face of the first interface die 111A. The dielectric layer 68 of the first integrated circuit die 50A may be directly bonded to the dielectric layer 166 and the die connectors 66 of the first integrated circuit die 50A may be directly bonded to the bond pads 168.

The first integrated circuit die 50A is bonded to the front-side interconnect structure 160 without the use of solder connections (e.g., micro bumps, etc.). By directly bonding the first integrated circuit die 50A to the front-side interconnect structure 160, advantages such as finer bump pitch may be realized; a small form factor package through the use of hybrid bonding; smaller bond pitch scalability for chip I/O for high density die-to-die interconnects; improved mechanical durability; improved electrical performance; reduced defects; and increased yield. Further, a shorter die-to-die distance may be achieved between the first integrated circuit die 50A and other integrated circuit dies, with the benefits of smaller form factor, higher bandwidth, improved Power Integrity (PI), improved Signal Integrity (SI), and lower power consumption.

In fig. 24, bond pads 126 are formed on the front side interconnect structures 160 over the first interface die 111A and the second interface die 111B, the second integrated circuit die 50B is bonded to the front side interconnect structures 160 over the first interface die 111A and the second interface die 111B by solder bonding, and the third integrated circuit die 50C is bonded to the front side interconnect structures 160 over the second interface die 111B by solder bonding. The bond pads 126 and the conductive connections 128 may be formed over the front-side interconnect structure 160 from the same or similar materials as those of the bond pads 126 and the conductive connections 128, respectively, described above with respect to fig. 6 and over the front-side interconnect structure 160 using the same or similar processes as those of the bond pads 126 and the conductive connections 128, described above with respect to fig. 6.

The desired type and number of integrated circuit dies 50 can be bonded to the front-side interconnect structure 160, such as one or more of the second integrated circuit dies 50B and one or more of the third integrated circuit dies 50C, by solder bonding. In the illustrated embodiment, a single second integrated circuit die 50B is bonded to the first interface die 111A and the front side interconnect structure 160 over the second interface die 111B, and a single third integrated circuit die 50C is bonded to the front side interconnect structure 160 over the second interface die 111B. The second integrated circuit die 50B may be a bridge die, which may be a logic device or a passive device. In embodiments in which the second integrated circuit die 50B is a logic device, the second integrated circuit die 50B may be CPU, GPU, soC, a microcontroller, or the like. In embodiments in which the second integrated circuit die 50B is a passive device, the second integrated circuit die 50B may be an input-output (IO) die, SED die, or the like. The third integrated circuit die 50C may be a memory device such as a DRAM die, an SRAM die, a NAND flash die, an HMC module, an HBM module, or the like. Although the third integrated circuit die 50C is shown as a single integrated circuit die, the third integrated circuit die 50C may include multiple stacked integrated circuit dies (also referred to as a die stack).

The second integrated circuit die 50B and the third integrated circuit die 50C are attached to the front-side interconnect structure 160 using solder bonding, such as using conductive connections 128. The second integrated circuit die 50B and the third integrated circuit die 50C may be placed on the front-side interconnect structure 160 using, for example, pick and place tools. Attaching the second and third integrated circuit dies 50B, 50C to the front-side interconnect structure 160 may include placing the second and third integrated circuit dies 50B, 50C and the reflow conductive connections 128 on the front-side interconnect structure 160. Conductive connections 128 form joints between bond pads 126 on front-side interconnect structure 160 and die connections 66 of second integrated circuit die 50B and third integrated circuit die 50C, electrically coupling first interface die 111A and second interface die 111B to second integrated circuit die 50B and third integrated circuit die 50C through front-side interconnect structure 160.

An underfill material 129 may be formed around the conductive connection 128 and between the front-side interconnect structure 160 and each of the second integrated circuit die 50B and the third integrated circuit die 50C. As shown in FIG. 24, the underfill material 129 may be a continuous material, or two different, discontinuous materials. The underfill material 129 may reduce stress and protect the joint due to reflowing the conductive connection 128. The underfill material 129 may be formed of any suitable underfill material, such as a molding compound, epoxy, or the like. The underfill material 129 may be formed by a capillary flow process after the second and third integrated circuit dies 50B, 50C are attached to the front-side interconnect structure 160, or may be formed by a suitable deposition method before the second and third integrated circuit dies 50B, 50C are attached to the front-side interconnect structure 160. The underfill material 129 may be applied in liquid or semi-liquid form and subsequently cured. In some embodiments, the underfill material 129 is omitted, and the underfill material 129 is omitted in subsequent figures.

The first integrated circuit die 50A and the third integrated circuit die 50C may be electrically coupled to each other through the front-side interconnect structure 160 and the second integrated circuit die 50B. The first integrated circuit die 50A is physically and electrically coupled to the front side interconnect structure 160 on the first interface die 111A by hybrid bonding between the die connectors 66 and the bond pads 168. The second integrated circuit die 50B is physically and electrically coupled to the front side interconnect structures 160 on the first interface die 111A and the second interface die 111B by solder bonding between the die connectors 66 and the bond pads 126. The third integrated circuit die 50C is physically and electrically coupled to the front side interconnect structure 160 on the second interface die 111B by solder bonding between the die connectors 66 and the bond pads 126. In some embodiments, the first integrated circuit die 50A may be a logic die, the second integrated circuit die 50B may be a bridge die, and the third integrated circuit die 50C may be a memory die. The first integrated circuit die 50A has a relatively smaller tube pitch and higher circuit density of the die connectors 66, while the second and third integrated circuit dies 50B, 50C have a relatively larger pitch and lower circuit density of the die connectors 66. Advantages such as finer bump pitch, higher bandwidth, and improved device performance are realized by bonding the first integrated circuit die 50A to the front-side interconnect structure 160 by hybrid bonding. Bonding the second and third integrated circuit dies 50B, 50C to the front-side interconnect structure 160 by solder bonding reduces cost.

In fig. 25, a second encapsulant 133 is formed over the first interface die 111A, the second interface die 111B, and the first encapsulant 131 and around the first integrated circuit die 50A, the second integrated circuit die 50B, and the third integrated circuit die 50C. The second encapsulant 133 may be formed of the same or similar materials as the encapsulant 130 described above with respect to fig. 8 and formed using the same or similar process as the encapsulant 130 described above with respect to fig. 8. The second encapsulant 133 may be thinned to expose the back sides of the first, second, and third integrated circuit dies 50A, 50B, 50C.

In fig. 26, the carrier substrate 100 is removed; thinning the back sides of the interface substrate 110 and the first encapsulant 131; forming a backside interconnect structure 170 on the backside of the interface substrate 110 and the first package 131; and optionally forming a heat sink layer 159 over the encapsulant 130, the first integrated circuit die 50A, and the second integrated circuit die 50B. The heat spreader 159, encapsulant 130, first integrated circuit die 50A, second integrated circuit die 50B, third integrated circuit die 50C, first interface die 111A, and second interface die 111B form a fourth package assembly 500. Carrier substrate lift-off is performed to separate the carrier substrate 100 from the first interface die 111A, the second interface die 111B, and the first encapsulant 131. In some embodiments, the stripping includes projecting light, such as laser or UV light, onto the release layer 102 such that the release layer 102 breaks down under the heat of the light and the carrier substrate 100 may be removed. As shown in fig. 26, the surfaces of the first interface die 111A, the second interface die 111B, and the first encapsulant 131 may be exposed after removing the carrier substrate 100 and the release layer 102.

The interface substrate 110 and the first sealant 131 may be thinned by a planarization process applied to the interface substrate 110 and the first sealant 131 to expose the conductive via 114. After exposing the conductive via 114, the conductive via 114 extends through the interface substrate 110 and may be referred to as a TSV. Planarization may remove the portion of interface substrate 110 opposite dielectric layer 112, thereby exposing conductive via 114. Planarization may be achieved by any suitable process, such as CMP, a grinding process, an etch back process, or the like, or a combination thereof. After planarization, the conductive vias 114 may extend completely through the interface substrate 110 and provide interconnection between opposite sides of the interface substrate 110.

The inclusion of the first integrated circuit die 50A that is hybrid bonded to the front side interconnect structure 160 over the first interface die 111A and the second and third integrated circuit dies 50B, 50C that are solder bonded to the front side interconnect structure 160 over the first and second interface dies 111A, 111B allows for the benefits of hybrid bonding and solder bonding. For example, hybrid bonding of the first integrated circuit die 50A allows die with small pitch to be bonded to the front side interconnect structure 160, providing higher bandwidth, and providing improved device performance. Solder bonding the second and third integrated circuit dies 50B, 50C reduces cost while still providing a sufficiently small bonding pitch.

Embodiments may realize advantages. Bonding the first integrated circuit die 50A to the interface die 111 by hybrid bonding allows die with small pitches to be bonded to the interface die 111, provides higher bandwidth, and provides improved device performance. Bonding the second integrated circuit die 50B and/or the third integrated circuit die 50C to the interface die 111 by solder bonding reduces cost while still providing a sufficiently small bonding pitch.

The bonding process described above has been described as being at the die level, wherein after the integrated circuit die 50 is bonded to the interface die 111, the integrated circuit die 50 bonded to the interface die 111 is singulated into different dies. Alternatively, bonding may be performed at the die-to-wafer level or wafer-to-wafer level, and a subsequent singulation process may be performed.

According to an embodiment, a package includes: a first interposer, the first interposer comprising a first redistribution structure; a first die bonded to the first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; a second die bonded to the first surface of the first redistribution structure with a first solder bond; an encapsulant around the first die and the second die; and a plurality of conductive connections on a second side of the first redistribution structure opposite the first die and the second die. In an embodiment, the first die comprises a logic die and the second die comprises a memory die. In an embodiment, the package further comprises: a second interposer adjacent to the first interposer, the second interposer including a second redistribution structure, the second die being bonded to the first surface of the second redistribution structure with a second solder bond. In an embodiment, the package further comprises: a third die bonded to the first surface of the second redistribution structure with a third solder bond. In an embodiment, the package further comprises: and a second encapsulant extending from the first interposer to the second interposer. In an embodiment, the top surface of the encapsulant, the top surface of the first die, and the top surface of the second die are flush with one another. In an embodiment, the package further comprises: an under bump metal on the first surface of the first redistribution structure, a second die bonded to the first redistribution structure by a first solder bond on the under bump metal, and a surface of the under bump metal being flush with a surface of the first die.

According to another embodiment, a semiconductor package includes: a first interface die; a second interface die adjacent to the first interface die; a first encapsulant extending from the first interface die to the second interface die; a first integrated circuit die bonded to the first interface die by a dielectric-to-dielectric bond and a metal-to-metal bond; and a second integrated circuit die bonded to the second interface die by the first solder bond. In an embodiment, the second integrated circuit die is further bonded to the first interface die by a second solder bond. In an embodiment, the semiconductor package further includes: a third integrated circuit die bonded to the second interface die by a third solder bond. In an embodiment, the first integrated circuit die is a logic die, the second integrated circuit die is a bridge die, and the third integrated circuit die is a memory die. In an embodiment, the first interface die includes a first interconnect structure, the first integrated circuit die is bonded to a first surface of the first interconnect structure, the second interface die includes a second interconnect structure, the second integrated circuit die is bonded to a second surface of the second interconnect structure, and the first surface and the second surface are flush. In an embodiment, the semiconductor package further includes: and a second encapsulant around the first and second integrated circuit dies, the second encapsulant physically contacting the first and second integrated circuit dies, the first and second interface dies.

According to yet another embodiment, a method comprises: providing a first interposer comprising a first interconnect structure on a first interposer substrate; bonding the first die to the first interconnect structure, the bonding the first die including directly bonding the first insulating layer of the first die to the bonding layer of the first interconnect structure and directly bonding the first die connector of the first die to the first bonding pad of the first interconnect structure; bonding the second die to the first interconnect structure, the bonding the second die including solder bonding a second die connector of the second die to a second bond pad of the first interconnect structure; and encapsulating the first die and the second die in a molding compound. In an embodiment, the method further comprises: forming a first under bump metal on the second bond pad; forming a conductive connection on the first under bump metal; and reflowing the conductive connection to join the second die to the first interconnect structure. In an embodiment, the method further comprises: flattening the molding compound, the first die and the second die. In an embodiment, the method further comprises: an underfill material is formed between the second die and the first interconnect structure, the underfill material surrounding the solder joints formed between the second die and the first interconnect structure. In an embodiment, the molding compound is formed around a solder joint formed between the second die and the first interconnect structure. In an embodiment, the method further comprises: a second interposer is provided adjacent to the first interposer, the second interposer including a second interconnect structure on a second interposer substrate, the second die being bonded to the first interconnect structure and the second die being bonded to the second interconnect structure by solder bonding. In an embodiment, the method further comprises: bonding the third die to the second interconnect structure, the bonding the third die including solder bonding a third die connector of the third die to a third bond pad of the second interconnect structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art will appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.

Claims

1. A package, comprising:

a first interposer, wherein the first interposer comprises a first redistribution structure;

a first die bonded to the first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond;

a second die bonded to the first surface of the first redistribution structure with a first solder bond;

an encapsulant around the first die and the second die; and

a plurality of conductive connections on a second side of the first redistribution structure opposite the first die and the second die.

2. The package of claim 1, wherein the first die comprises a logic die, and wherein the second die comprises a memory die.

3. The package of claim 1, further comprising: a second interposer adjacent to the first interposer, wherein the second interposer includes a second redistribution structure, wherein the second die is bonded to the first surface of the second redistribution structure with a second solder bond.

4. The package of claim 3, further comprising: a third die bonded to the first surface of the second redistribution structure with a third solder bond.

5. The package of claim 3, further comprising: a second encapsulant extends from the first interposer to the second interposer.

6. The package of claim 1, wherein the top surface of the encapsulant, the top surface of the first die, and the top surface of the second die are flush with one another.

7. The package of claim 1, further comprising: an under bump metal on the first surface of the first redistribution structure, wherein the second die is bonded to the first redistribution structure by the first solder bond on the under bump metal, and wherein a surface of the under bump metal is flush with a surface of the first die.

8. A semiconductor package, comprising:

a first interface die;

a second interface die adjacent to the first interface die;

a first encapsulant extending from the first interface die to the second interface die;

a first integrated circuit die bonded to the first interface die by a dielectric-to-dielectric bond and a metal-to-metal bond; and

a second integrated circuit die bonded to the second interface die by a first solder bond.

9. The semiconductor package of claim 8, wherein the second integrated circuit die is further bonded to the first interface die by a second solder bond.

10. A method of forming a semiconductor package, comprising:

providing a first interposer comprising a first interconnect structure on a first interposer substrate;

bonding a first die to the first interconnect structure, wherein bonding the first die comprises directly bonding a first insulating layer of the first die to a bonding layer of the first interconnect structure and directly bonding a first die connector of the first die to a first bonding pad of the first interconnect structure;

bonding a second die to the first interconnect structure, wherein bonding the second die comprises solder bonding a second die connector of the second die to a second bond pad of the first interconnect structure; and

The first die and the second die are encapsulated in a molding compound.