CN117650111A - Three-dimensional stacked embedded micro-channel active heat dissipation packaging structure and method - Google Patents

Three-dimensional stacked embedded micro-channel active heat dissipation packaging structure and method Download PDF

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Publication number
CN117650111A
CN117650111A CN202311537708.6A CN202311537708A CN117650111A CN 117650111 A CN117650111 A CN 117650111A CN 202311537708 A CN202311537708 A CN 202311537708A CN 117650111 A CN117650111 A CN 117650111A
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chip
micro
channel
heterogeneous
silicon wafer
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CN202311537708.6A
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Inventor
周超杰
王刚
刘书利
李奇哲
夏晨辉
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CETC 58 Research Institute
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CETC 58 Research Institute
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Priority to CN202311537708.6A priority Critical patent/CN117650111A/en
Publication of CN117650111A publication Critical patent/CN117650111A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Geometry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention relates to the technical field of integrated circuit packaging, in particular to a three-dimensional stacked embedded micro-channel active heat dissipation packaging structure and method. The device comprises a silicon wafer, a rewiring layer I, a resin plastic package body and a rewiring layer II which are sequentially arranged from bottom to top; two heterogeneous chips I are embedded on the silicon wafer, and a micro-channel unit is distributed between the two heterogeneous chips I; the second heterogeneous chip and the TSV switching chip are embedded on the resin plastic package body, and two second heterogeneous chips are distributed between the two TSV switching chips; the heterogeneous chip I, the TSV switching chip and the heterogeneous chip II are interconnected through the rewiring layer I; and interconnection is realized through the rewiring layer II and the copper column of the TSV switching chip, and the UBM of the rewiring layer II is correspondingly provided with a ball. The invention aims to solve the problem of low heat dissipation efficiency of the existing three-dimensional package.

Description

Three-dimensional stacked embedded micro-channel active heat dissipation packaging structure and method
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to a three-dimensional stacked embedded micro-channel active heat dissipation packaging structure and method.
Background
With the development of microelectronics and microelectromechanical systems (MEMS) technology, in particular, the emergence of new interconnect technologies such as Flip Chip (FC) and multi-chip modules (MCM), chip integration and performance are continuously increasing. The rapid development of chip miniaturization and high integration presents a great challenge to the efficient heat dissipation of electronic chips. In particular, in three-dimensional packaging systems, thermal management issues for the package are becoming more and more important because: (1) A plurality of chips are often integrated in the three-dimensional packaging system, the heating value is large, the packaging area is not obviously increased, and the chips positioned in the three-dimensional lamination are more difficult to dissipate heat; (2) Under high power density, because of the difference of thermal expansion coefficients of laminated materials in the three-dimensional packaging structure, the large wall surface temperature rise can generate thermo-mechanical stress at interfaces of different materials, and the reliability of the system is seriously affected;
in three-dimensional stacked chips, heat flow is mainly transmitted through the vertical direction. The common three-dimensional packaging heat dissipation method is to attach a cold plate and a heat sink to the back of a packaging structure and transfer heat to a system for environmental control or air, but the heat dissipation structure is not in direct contact with a chip, and a plastic packaging material and a multi-layer chip are arranged between the heat dissipation structure and the chip. The micro-flow channel active heat dissipation technology is that the micro-flow channel is integrated in the package body and directly contacts with the front surface of the chip, heat generated by the chip in the package body is taken away through fluid flow, the heat transfer efficiency is far greater than that of heat sink type heat dissipation, and the electronic device can be ensured to work at a specified temperature.
Disclosure of Invention
The invention aims to provide a three-dimensional stacked embedded micro-channel active heat dissipation packaging structure and method, which are used for solving the problem of low heat dissipation efficiency of the existing three-dimensional packaging.
In order to solve the technical problems, the invention provides a three-dimensional stacked embedded micro-channel active heat dissipation packaging structure, which comprises a silicon wafer, a rewiring layer I, a resin plastic package body and a rewiring layer II which are sequentially arranged from bottom to top; two heterogeneous chips I are embedded on the silicon wafer, and a micro-channel unit is distributed between the two heterogeneous chips I; the second heterogeneous chip and the TSV switching chip are embedded on the resin plastic package body, and two second heterogeneous chips are distributed between the two TSV switching chips; the heterogeneous chip I, the TSV switching chip and the heterogeneous chip II are interconnected through the rewiring layer I; and interconnection is realized through the rewiring layer II and the copper column of the TSV switching chip, and the UBM of the rewiring layer II is correspondingly provided with a ball.
Preferably, the micro flow channel unit includes: the micro-channel groove, the copper micro-channel cover plate and the micro-channel inlet and outlet channels; the micro-channel groove is etched on the silicon wafer, the copper micro-channel cover plate is buckled on the micro-channel groove to form a sealed micro-channel, and the micro-channel further comprises a communicated micro-channel inlet and outlet channel which extends and is exposed at the bottom of the silicon wafer.
Preferably, the surface of the micro-channel groove further comprises a sputtered copper layer, and the copper micro-channel cover plate and the copper layer on the surface of the micro-channel groove are subjected to copper-copper bonding so as to realize micro-channel sealing.
Preferably, a chip groove is etched on the surface of the silicon wafer, the heterogeneous chip I is embedded in the chip groove, and a filled conductive adhesive layer is further included between the chip groove and the heterogeneous chip I, so that the silicon-based fan-out wafer is formed.
Preferably, the TSV adapter chip and the heterogeneous chip two further include bumps of long balls, the heterogeneous chip two after the long balls and the TSV adapter chip are flipped onto the rewiring layer one through a reflow soldering or hot-pressing process, and the flipped TSV adapter chip and the heterogeneous chip are filled through underfill.
Preferably, the inverted heterogeneous chip II and the TSV transfer chip are encapsulated through resin molding compound, and cured and reconstructed to form the resin-based wafer.
The invention also provides a three-dimensional stacked embedded micro-channel active heat dissipation packaging method, which comprises the following steps:
step S1: etching a micro-channel groove and a micro-channel inlet and outlet channel on a silicon wafer, and sputtering a copper layer;
step S2: copper-copper bonding is carried out on the copper micro-channel cover plate and a copper layer on the micro-channel groove on the silicon wafer, so that micro-channel sealing is realized, and a micro-channel unit is completed;
step S3: etching a chip groove on a silicon wafer, and fixing the heterogeneous chip I in the chip groove of the silicon wafer substrate through heat conducting glue;
step S4: after the heterogeneous chip I is fixed in a chip groove, sequentially realizing RDL and UBM multilayer interconnection metal rewiring by using a PI adhesive and wafer-level multilayer rewiring process;
step S5: flip-chip bonding the TSV switching chip and the heterogeneous chip II to a rewiring layer of the silicon wafer, and filling gaps among bumps at the flip-chip bonding position with underfill;
step S6: encapsulating the inverted heterogeneous chip II and the TSV switching chip by using a wafer-level plastic packaging process and using a resin plastic packaging material, and solidifying the two chips to form a resin-based wafer;
step S7: thinning the resin-based wafer, leaking out copper columns of the TSV switching chip, and forming multilayer interconnection rewiring on the resin-based wafer by using a wafer-level rewiring process;
step S8: thinning the silicon wafer and leaking out the inlet and outlet channels of the micro-channel;
step S9: ball implantation is carried out at UBM of the reconstructed multilayer silicon wafer by utilizing a wafer-level ball implantation process; and scribing the three-dimensional stacked silicon wafer to form a final packaging body.
Compared with the prior art, the invention has the following beneficial effects:
1. the resin-based substrate chip embedded structure and the micro-channel copper cover plate chip bonding structure are utilized to enable the heat dissipation micro-channel copper cover plate to be in direct contact with the front surface of the functional chip, so that a direct heat dissipation channel is formed, the thermal resistance is greatly reduced, and the heat dissipation is faster.
2. The micro-channel structure with the size of submicron level is directly embedded in the three-dimensional integrated package, and the coolant flows in from the inlet to take away the heat productivity of the chip in the package, so that the micro-channel structure is a direct and efficient substrate level active heat dissipation mode, and the multi-dimensional and multi-scale heat management of the three-dimensional package system is realized.
3. The embedded silicon-based fan-out technology and the resin-based wafer reconstruction technology are utilized to realize three-dimensional heterogeneous integration of the multiple chips, and the upper part of the silicon-based chip is directly connected with the TSV to establish a heat channel, so that the heat dissipation efficiency is further improved.
Drawings
FIG. 1 is a schematic diagram of a sputtered copper layer after etching a micro-fluidic channel on a silicon wafer according to the present invention.
FIG. 2 is a schematic diagram of bonding a silicon wafer micro-fluidic channel with a copper cover plate according to the present invention.
FIG. 3 is a schematic diagram of a silicon wafer etched die slot according to the present invention.
Fig. 4 is a schematic diagram of a fan-out chip package for a silicon wafer according to the present invention.
Fig. 5 is a schematic diagram of a silicon wafer rewiring in accordance with the present invention.
Fig. 6 is a schematic diagram of a silicon wafer flip-chip in accordance with the present invention.
Fig. 7 is a schematic diagram of the underfill after flip-chip mounting of the silicon wafer according to the present invention.
Fig. 8 is a schematic view of wafer level injection molding of the present invention.
Fig. 9 is a schematic diagram of a wafer level thinned leaky TSV copper pillar in accordance with the present invention.
Fig. 10 is a schematic diagram of a wafer level rewiring in accordance with the present invention.
FIG. 11 is a schematic view of a thinned silicon wafer exposing the inlet and outlet of the micro flow channel according to the present invention.
FIG. 12 is a schematic view of a wafer level ball implant of the present invention.
In the figure: 111-silicon wafer, 112-micro flow channel groove, 113-copper micro flow channel cover plate, 114-heterogeneous chip I, 115-rewiring layer I, 116-TSV switching chip, 117-heterogeneous chip II, 118-underfill, 119-resin plastic package body, 120-rewiring layer II and 121-ball mounting.
Detailed Description
The invention is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
As shown in fig. 1-12, an embodiment of the present invention provides a three-dimensional stacked embedded micro-fluidic channel active heat dissipation packaging method and structure, the method includes:
after etching the micro-channel groove 112 on the silicon wafer 111, sputtering a layer of metal copper on the surface of the micro-channel groove through a sputtering process;
copper-copper bonding of the copper micro-channel cover plate and the micro-channel groove is performed on the silicon wafer 111;
etching a chip groove 114 on a silicon wafer 111, fixing a heterogeneous chip 114 (namely Die-1 and Die-2) in the chip groove of the silicon wafer substrate through heat conducting glue, and sequentially realizing RDL and UBM multilayer interconnection metal rewiring (namely a rewiring layer one 115) by using PI glue and a wafer-level multilayer rewiring process, wherein the wafer-level multilayer rewiring process is a wiring process with a passivation layer and a metal layer overlapped for a plurality of times;
the second heterogeneous chip (namely Die-3 and Die-4) after the long ball and the TSV switching chip 116 are inverted to the first rewiring layer 115 on the silicon wafer 111 through a reflow soldering or hot-pressing process, the inverted chip is subjected to underfilling and underfilling glue 118, gaps among the bumps of the inverted chip are filled by the underfilling glue 118, and the underfilling mode comprises a press-drying film process and a dispensing process; the substrate materials of the first heterogeneous chip and the second heterogeneous chip comprise Si, gaAs, gaN or SiC; the long bump material of the heterogeneous chip II and the TSV transfer chip comprises Cu, cuSn, cuNiSn, cuNiSnAg, snPb or SnAgCu.
The front surface of the silicon wafer is subjected to plastic packaging, a plastic packaging material is used for packaging the flip chip to form a resin plastic packaging body 119, then the resin plastic packaging body 119 is thinned, after the copper column of the TSV switching chip is exposed, RDL and UBM multilayer interconnection metal rewiring (namely a rewiring layer II 120) is sequentially realized by using a PI adhesive and wafer-level multilayer rewiring technology; the number of the rewiring layer I and the rewiring layer II is at least 1 metal layer; the thickness of the passivation layer is larger than that of the formed metal layer, and the passivation layer coats the metal layer; the thickness of the metal layer is not less than 1 mu m, and the thickness of the passivation layer is not less than 3 mu m.
Thinning the back surface of the silicon wafer 111 to leak out an inlet and outlet channel of the micro flow channel groove 112;
finally, the ball 121 is implanted at the UBM of the reconstructed multi-layer silicon wafer by using a wafer level ball implantation process, and then the three-dimensional integrated silicon wafer is diced to form a final package. The ball implantation process comprises wafer-level ball implantation, single-chip ball implantation and solder paste printing; the solder ball comprises SnPb and SnAgCu.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (7)

1. The three-dimensional stacked embedded micro-channel active heat dissipation packaging structure is characterized by comprising a silicon wafer, a first rewiring layer, a resin plastic package body and a second rewiring layer which are sequentially arranged from bottom to top; two heterogeneous chips I are embedded on the silicon wafer, and a micro-channel unit is distributed between the two heterogeneous chips I; the second heterogeneous chip and the TSV switching chip are embedded on the resin plastic package body, and two second heterogeneous chips are distributed between the two TSV switching chips; the heterogeneous chip I, the TSV switching chip and the heterogeneous chip II are interconnected through the rewiring layer I; and interconnection is realized through the rewiring layer II and the copper column of the TSV switching chip, and the UBM of the rewiring layer II is correspondingly provided with a ball.
2. The three-dimensional stacked embedded micro-fluidic channel active heat dissipation packaging structure as defined in claim 1, wherein the micro-fluidic channel unit comprises: the micro-channel groove, the copper micro-channel cover plate and the micro-channel inlet and outlet channels; the micro-channel groove is etched on the silicon wafer, the copper micro-channel cover plate is buckled on the micro-channel groove to form a sealed micro-channel, and the micro-channel further comprises a communicated micro-channel inlet and outlet channel which extends and is exposed at the bottom of the silicon wafer.
3. The three-dimensional stacked embedded micro-channel active heat dissipation packaging structure according to claim 2, wherein the surface of the micro-channel groove further comprises a sputtered copper layer, and the copper micro-channel cover plate and the copper layer on the surface of the micro-channel groove are subjected to copper-copper bonding to realize micro-channel sealing.
4. The three-dimensional stacked embedded micro-channel active heat dissipation packaging structure as claimed in claim 1, wherein a chip groove is etched on the surface of the silicon wafer, the heterogeneous chip I is embedded in the chip groove, and a filled conductive adhesive layer is further included between the chip groove and the heterogeneous chip I, so that the silicon-based fan-out wafer is formed.
5. The three-dimensional stacked embedded micro-channel active heat dissipation packaging structure according to claim 1, wherein the TSV switching chip and the heterogeneous chip II further comprise long ball bumps, the heterogeneous chip II and the TSV switching chip after the long balls are inverted onto the rewiring layer I through a reflow soldering or hot-pressing process, and the inverted TSV switching chip and the heterogeneous chip are filled through underfill.
6. The three-dimensional stacked embedded micro-fluidic channel active heat dissipation packaging structure according to claim 1, wherein the inverted heterogeneous chip II and the TSV transfer chip are encapsulated by a resin molding compound, and cured and reconstructed to form a resin-based wafer.
7. The three-dimensional stacked embedded micro-channel active heat dissipation packaging method is characterized by comprising the following steps of:
step S1: etching a micro-channel groove and a micro-channel inlet and outlet channel on a silicon wafer, and sputtering a copper layer;
step S2: copper-copper bonding is carried out on the copper micro-channel cover plate and a copper layer on the micro-channel groove on the silicon wafer, so that micro-channel sealing is realized, and a micro-channel unit is completed;
step S3: etching a chip groove on a silicon wafer, and fixing the heterogeneous chip I in the chip groove of the silicon wafer substrate through heat conducting glue;
step S4: after the heterogeneous chip I is fixed in a chip groove, sequentially realizing RDL and UBM multilayer interconnection metal rewiring by using a PI adhesive and wafer-level multilayer rewiring process;
step S5: flip-chip bonding the TSV switching chip and the heterogeneous chip II to a rewiring layer of the silicon wafer, and filling gaps among bumps at the flip-chip bonding position with underfill;
step S6: encapsulating the inverted heterogeneous chip II and the TSV switching chip by using a wafer-level plastic packaging process and using a resin plastic packaging material, and solidifying the two chips to form a resin-based wafer;
step S7: thinning the resin-based wafer, leaking out copper columns of the TSV switching chip, and forming multilayer interconnection rewiring on the resin-based wafer by using a wafer-level rewiring process;
step S8: thinning the silicon wafer and leaking out the inlet and outlet channels of the micro-channel;
step S9: ball implantation is carried out at UBM of the reconstructed multilayer silicon wafer by utilizing a wafer-level ball implantation process; and scribing the three-dimensional stacked silicon wafer to form a final packaging body.
CN202311537708.6A 2023-11-17 2023-11-17 Three-dimensional stacked embedded micro-channel active heat dissipation packaging structure and method Pending CN117650111A (en)

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CN202311537708.6A CN117650111A (en) 2023-11-17 2023-11-17 Three-dimensional stacked embedded micro-channel active heat dissipation packaging structure and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311537708.6A CN117650111A (en) 2023-11-17 2023-11-17 Three-dimensional stacked embedded micro-channel active heat dissipation packaging structure and method

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CN117650111A true CN117650111A (en) 2024-03-05

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