CN115101516A - 3D packaging structure of heterogeneous multi-chip and manufacturing method thereof - Google Patents

3D packaging structure of heterogeneous multi-chip and manufacturing method thereof Download PDF

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Publication number
CN115101516A
CN115101516A CN202210665018.8A CN202210665018A CN115101516A CN 115101516 A CN115101516 A CN 115101516A CN 202210665018 A CN202210665018 A CN 202210665018A CN 115101516 A CN115101516 A CN 115101516A
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layer
heterogeneous
chip
rewiring
rewiring layer
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李奇哲
夏晨辉
叶刚
周超杰
王刚
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Wuxi Zhongwei High Tech Electronic Co ltd
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Wuxi Zhongwei High Tech Electronic Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60277—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the use of conductive adhesives
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

The invention relates to the technical field of integrated circuit packaging, and particularly discloses a 3D packaging structure of heterogeneous multi-chips, which comprises: the chip packaging structure comprises a first rewiring layer and a plastic packaging material layer positioned on the first rewiring layer, wherein a plurality of groups of heterogeneous chip structures are arranged at intervals in the plastic packaging material layer, a through hole structure is arranged between every two adjacent groups of heterogeneous chip structures, each group of heterogeneous chip structures comprises a plurality of stacked heterogeneous single chips, and a bonding layer is arranged between every two adjacent heterogeneous single chips; a second rewiring layer is arranged on the surface of the plastic packaging material layer, which deviates from the first rewiring layer; the first rewiring layer and the second rewiring layer can be used for signal interconnection of multiple heterogeneous chip structures; and the surface of the first rewiring layer departing from the plastic packaging material layer is provided with metal bumps. The invention also discloses a manufacturing method of the 3D packaging structure of the heterogeneous multi-chip. The 3D packaging structure of the heterogeneous multi-chip can meet the requirements of integration, high density and small size.

Description

3D packaging structure of heterogeneous multi-chip and manufacturing method thereof
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to a 3D packaging structure of heterogeneous multi-chips and a manufacturing method of the 3D packaging structure of the heterogeneous multi-chips.
Background
The new generation of high-density chip plastic packaging technology integrates chips with different materials, different functions and different sizes and thicknesses, and realizes complete system functions in a packaging structure with a small volume.
Based on the requirement, various three-dimensional stacking structures are proposed in the industry, such as a layer-to-layer stacking (Package on Package, abbreviated as POP) three-dimensional stacking structure or a packaging structure in which a chip is mounted after a substrate is grooved for high-density fan-out. After a POP type structure is generally heterogeneous multi-chip integration in a horizontal plane, three-dimensional stacking is realized in the vertical direction through a bonding process, the integration in the vertical direction depends on the bonding process, and hidden danger that Thermal Expansion coefficients (CET for short) are not matched exists between layers, so that the risk in the reliability direction is brought; the technology of sticking the heterogeneous multi-chip after slotting on the surface of the substrate overcomes the potential reliability problem of the POP structure, realizes the integration of the heterogeneous multi-chip integrated structure, but has complex process flow, and when the requirement of the system integration level is higher, the requirement on the size of the substrate is larger, and the size of the final packaging structure can not meet the requirement of miniaturization.
Therefore, how to provide a package structure that can not only realize heterogeneous multi-chip integration, but also satisfy high density and small size has become a technical problem to be solved by those skilled in the art.
Disclosure of Invention
The invention provides a 3D (three-dimensional) packaging structure of heterogeneous multi-chips and a manufacturing method of the 3D packaging structure of the heterogeneous multi-chips, and solves the problem that the related technology lacks an integrated and high-density small-size packaging structure.
As a first aspect of the present invention, there is provided a 3D package structure of heterogeneous multichip, including:
a first redistribution layer and a plastic encapsulation layer on the first redistribution layer,
a plurality of groups of heterogeneous chip structures are arranged in the plastic packaging material layer at intervals, a through hole structure is arranged between every two adjacent groups of heterogeneous chip structures, each group of heterogeneous chip structures comprises a plurality of stacked heterogeneous single chips, and a bonding layer is arranged between every two adjacent heterogeneous single chips;
a second rewiring layer is arranged on the surface, away from the first rewiring layer, of the plastic packaging material layer, and a passivation layer is arranged on the surface, away from the plastic packaging material layer, of the second rewiring layer;
the first rewiring layer and the second rewiring layer can be used for signal interconnection of a plurality of heterogeneous chip structures;
the through hole structure is used for communicating the first rewiring layer and the second rewiring layer;
and arranging a metal bump on the surface of the first rewiring layer deviating from the plastic packaging material layer, wherein the metal bump can be in signal interconnection with the first rewiring layer.
Further, the interval sets up two sets of different structure chip structures in the plastic envelope material layer, and every group different structure chip structure all includes two different structure single-chips that pile up the setting, sets up the tie coat between two different structure single-chips that pile up the setting.
Further, the height of the through hole structure is not larger than the thickness of the plastic packaging material layer.
Further, the material for making the bonding layer comprises any one of heat-conducting glue, alloy solder sheet and DAF film material.
Further, the manufacturing material of the passivation layer comprises any one of ABF, CBF and epoxy resin dry film.
Further, the first rewiring layer and the second rewiring layer are made of materials including polyimide and copper.
As another aspect of the present invention, a method for manufacturing a 3D package structure of heterogeneous multi-chips is provided, where the method includes:
providing a carrier plate, and attaching a temporary bonding film on the carrier plate to form a temporary bonding carrier plate;
mounting a plurality of prepared groups of heterogeneous chip structures on the temporary bonding carrier plate, and arranging a through hole structure between every two connected groups of heterogeneous chip structures, wherein each group of heterogeneous chip structures comprises a plurality of stacked heterogeneous single chips, and an adhesive layer is arranged between every two adjacent heterogeneous single chips;
encapsulating the mounted multi-group heterogeneous chip structure to form a plastic packaging material layer;
performing a rewiring process on the plastic packaging material layer to form a second rewiring layer;
covering a passivation layer on the second rewiring layer;
removing the temporary bonding carrier plate, and forming a first rewiring layer on the surface of the plastic packaging material layer, which is far away from the second rewiring layer, wherein the second rewiring layer and the first rewiring layer are in signal interconnection through the through hole structure, and the first rewiring layer and the second rewiring layer can perform signal interconnection on multiple groups of heterogeneous chip structures;
and forming a metal bump on the surface of the first rewiring layer departing from the plastic packaging material layer, wherein the metal bump can be in signal interconnection with the first rewiring layer.
Further, installing a plurality of prepared heterogeneous chip structures on the temporary bonding carrier plate, and arranging a through hole structure between every two connected heterogeneous chip structures, including:
preparing a chip structure with salient points by respectively adopting different process paths according to different incoming material forms of the heterogeneous chip structure;
thinning and scribing the chip structure with the salient points to obtain a bottom layer heterogeneous single-chip structure and a top layer heterogeneous single-chip structure;
mounting the bottom layer heterogeneous single-chip structure and the through hole structure on the temporary bonding carrier plate according to mounting coordinates;
arranging an adhesive layer on the surface of the bottom layer heterogeneous single-chip structure, which is far away from the temporary bonding carrier plate;
and correspondingly attaching the top-layer heterogeneous single-chip structure on the bottom-layer heterogeneous single-chip structure according to the installation coordinates, and bonding the top-layer heterogeneous single-chip structure with the bottom-layer heterogeneous single-chip structure through the bonding layer.
Further, according to different incoming material forms of the heterogeneous chip structure, different process paths are respectively adopted to prepare the chip structure with the salient points, and the method comprises the following steps:
when the incoming material form of the heterogeneous chip structure is a single chip, performing plastic packaging on multiple single chips to form wafer reconstruction;
and performing yellow light treatment and wet etching treatment on the wafer reconstructed structure, and then performing bump growth to obtain the chip structure with the bumps.
Further, preparing the chip structure with the bumps by respectively adopting different process paths according to different incoming material forms of the heterogeneous chip structure comprises the following steps:
and when the heterogeneous chip structure is in a wafer incoming form, performing yellow light treatment and wet etching treatment on the wafer, and then performing bump growth to obtain the chip structure with the bumps.
The 3D packaging structure of the heterogeneous multi-chip is different from a conventional POP stacking structure, the process of the three-dimensional integrated 3D packaging structure is simpler, multiple flip-chip welding processes required for realizing three-dimensional stacking in the vertical direction are reduced, meanwhile, the reliability is more dominant, and the stress imbalance risk caused by CET mismatching is effectively reduced through the integrated structure. In addition, in the three-dimensional integrated 3D packaging structure, a conducting structure connected with an internal signal is reserved at the top, and secondary integrated packaging can be carried out with other single chip structures or high-density integrated packaging structures, so that the follow-up packaging integration process is facilitated.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic cross-sectional view of a 3D package structure of heterogeneous multi-chips according to the present invention.
Fig. 2 is a schematic view of a temporary bonded carrier according to the present invention.
Fig. 3 is a schematic diagram of a wafer reconstruction method for preparing high bumps by using the heterogeneous incoming material chip provided by the invention.
FIG. 4 is a schematic diagram of a thinning scribe for growing a high bump chip according to the present invention.
FIG. 5 is a schematic view of the bottom layer heterogeneous multichip and the chip mounting with the vertical via structure.
Fig. 6 is a schematic diagram of stacking an upper heterogeneous multi-chip with an adhesive adhered to the back of a bottom heterogeneous chip according to the present invention.
Fig. 7 is a schematic diagram of the integral plastic package of the high-bump heterogeneous multi-chip and bottom-layer heterogeneous chip stacked body provided by the invention.
Fig. 8 is a schematic diagram of a chip bump and a copper pillar with an upper and lower vertical through hole structure leaked from the back of the plastic package body in a thinned manner.
FIG. 9 is a schematic diagram of wafer-level redistribution traces on the back side of the plastic package according to the present invention.
FIG. 10 is a schematic diagram of wafer level rewiring on the front side of a passivation protected backside rewiring layer according to the present invention.
Fig. 11 is a schematic diagram of the preparation of solder balls according to the present invention.
Fig. 12 is a specific flowchart of a method for manufacturing a 3D package structure of heterogeneous multi-chips according to the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make those skilled in the art better understand the technical solutions of the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Moreover, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In this embodiment, a 3D package structure of heterogeneous multi-chips is provided, and fig. 1 is a cross-sectional view of the 3D package structure of heterogeneous multi-chips according to an embodiment of the present invention, as shown in fig. 1, including:
a first redistribution layer 113 and a plastic encapsulation layer 103 on the first redistribution layer 113,
a plurality of groups of heterogeneous chip structures are arranged in the plastic packaging layer 103 at intervals, a through hole structure 110 is arranged between every two adjacent groups of heterogeneous chip structures, each group of heterogeneous chip structures comprises a plurality of stacked heterogeneous single chips, and a bonding layer 111 is arranged between every two adjacent heterogeneous single chips;
a second rewiring layer 112 is arranged on the surface, away from the first rewiring layer 113, of the plastic package layer 103, and a passivation layer 102 is arranged on the surface, away from the plastic package layer 103, of the second rewiring layer 112;
the first redistribution layer 113 and the second redistribution layer 112 can perform signal interconnection on a plurality of heterogeneous chip structures;
the via structure 110 is used to connect the first redistribution layer 113 and the second redistribution layer 112;
the surface of the first redistribution layer 113 away from the plastic package layer 103 is provided with a metal bump 114, and the metal bump 114 can be in signal interconnection with the first redistribution layer 113.
In the embodiment of the invention, the three-dimensional stacked structure of the heterogeneous multi-chip structure is embedded in the groove of the substrate material, and in the three-dimensional integrated 3D packaging structure, after the multi-chip at the bottom and the multi-chip at the upper layer are bonded into a whole through the bonding layer, the through hole structure which is vertical up and down and the stacked multi-chip are integrally plastic-packaged into a whole, and then signal interconnection is realized through a wafer-level rewiring process, so that higher integration level is realized in the horizontal and vertical directions, and the volume of an integrated microsystem is further reduced.
Therefore, the 3D packaging structure of the heterogeneous multi-chip provided by the embodiment of the invention is different from a conventional POP stacking structure, the process of the three-dimensional integrated 3D packaging structure is simpler, multiple flip-chip welding processes required for realizing three-dimensional stacking in the vertical direction are reduced, meanwhile, the reliability is more dominant, and the stress imbalance risk caused by CET mismatching is effectively reduced by the integrated structure. In addition, in the three-dimensional integrated 3D packaging structure, a conducting structure connected with an internal signal is reserved at the top, and secondary integrated packaging can be carried out with other single chip structures or high-density integrated packaging structures, so that the follow-up packaging integration process is facilitated.
As a specific embodiment, two sets of heterogeneous chip structures are disposed at intervals in the plastic package layer 103, and each set of the heterogeneous chip structures includes two heterogeneous single chips stacked together, and the bonding layer 111 is disposed between the two heterogeneous single chips stacked together.
As shown in fig. 1, one of the sets of heterogeneous chip structures includes a first heterogeneous single chip 108 located on the bottom layer and a second heterogeneous single chip 106 located on the top layer, the other set of heterogeneous single chip structure includes a third heterogeneous single chip 109 located on the bottom layer and a fourth heterogeneous single chip 107 located on the top layer, and the first heterogeneous single chip 108 and the second heterogeneous single chip 106, and the third heterogeneous single chip 109 and the fourth heterogeneous single chip 107 are connected by an adhesive layer 111.
It should be noted that both the second heterogeneous single chip 106 and the fourth heterogeneous single chip 107 have high bumps. Specifically, a second heterogeneous single chip 106 and a fourth heterogeneous single chip 107 with high bumps are respectively bonded to the back surfaces of a first heterogeneous single chip 108 and a third heterogeneous single chip 109 through bonding layers 111, a plurality of heterogeneous single chips and a through hole structure 110 vertical to the upper and lower sides are integrally subjected to plastic package through a plastic package material to form a plastic package material layer 103, the bumps of the second heterogeneous single chip 106 and the fourth heterogeneous single chip 107 and copper columns of the through hole structure 110 vertical to the upper and lower sides are exposed after thinning, signal interconnection between the second heterogeneous single chip 106 and the fourth heterogeneous single chip 107 and the through hole structure 110 is realized through a wafer-level second re-wiring layer 112, single-layer horizontal heterogeneous multi-chip packaging is completed, and a passivation layer 102 covers the surface of the second re-wiring layer 112 to protect the second heterogeneous single chip and the fourth heterogeneous single chip; signal interconnection of the second heterogeneous single chip 106, the fourth heterogeneous single chip 107, the first heterogeneous single chip 108 and the third heterogeneous single chip 109 and the through hole structure 110 is realized through the first rewiring layer 113 at the wafer level, and high-density three-dimensional integrated 3D packaging is completed; the metal bumps 114 are formed on the surface of the first redistribution layer 113 facing away from the plastic package layer 103.
In the embodiment of the present invention, the height of the via structure 110 is not greater than the thickness of the plastic package layer 103.
It should be understood that the incoming material chip for manufacturing the second heterogeneous single chip 106 and the fourth heterogeneous single chip 107 with the high bumps may be a single chip, or may be in a wafer form, and after the incoming material single chip is reconfigured by plastically packaging the single chip, the incoming material single chip is subjected to yellow light, wet process, thinning and scribing to form a single Pad and grow the second heterogeneous single chip 106 and the fourth heterogeneous single chip 107 with the high bumps; when the supplied material is a wafer, the wafer is subjected to yellow light, wet process, thinning and scribing to form a second heterogeneous single chip 106 and a fourth heterogeneous single chip 107 with a single Pad growing high salient point, wherein the passivation layer material 102 in the yellow light process can be ABF, CBF and epoxy resin dry film, and the high salient point material in the wet process can be tin-lead, tin-silver and tin-silver-copper.
That is, in the embodiment of the present invention, the material for manufacturing the passivation layer 102 includes any one of ABF, CBF and a dry film of epoxy resin.
Specifically, the material for manufacturing the adhesive layer 111 includes any one of a thermally conductive paste, an alloy solder sheet, and a DAF film material.
In the embodiment of the present invention, the material for manufacturing the first redistribution layer 113 and the second redistribution layer 112 includes polyimide and copper.
Specifically, the back surface of the second heterogeneous single chip 106 is connected with the back of the first heterogeneous single chip 108 through an adhesive layer 111, the back surface of the fourth heterogeneous single chip 107 is connected with the back of the third heterogeneous single chip 109 through the adhesive layer 111, and the material of the adhesive layer 111 can be low-temperature heat-conducting glue, an alloy solder sheet, or a DAF film material; the thickness of the adhesive layer should ensure that the thickness of the second heterogeneous single chip 106, the adhesive layer 111 and the first heterogeneous single chip 108 is generally close to the height of the vertical through hole structure 110, and the thickness of the fourth heterogeneous single chip 107, the adhesive layer 111 and the third heterogeneous single chip 109 is generally close to the height of the vertical through hole structure 110.
Specifically, the metal bumps 114 are formed by a wafer-level ball-mounting or single-chip-screen ball-mounting process, and are kept in signal interconnection with the first redistribution layer 113, and the material includes tin-lead, tin-silver, and tin-silver-copper.
As another embodiment of the present invention, a method for manufacturing a 3D package structure of heterogeneous multi-chips is provided, where as shown in fig. 2 to 11, the method includes:
step S100, as shown in fig. 2, providing a carrier 100, and attaching a temporary bonding film 101 on the carrier 100 to form a temporary bonding carrier;
step S200, as shown in fig. 6, mounting a plurality of prepared heterogeneous chip structures on the temporary bonding carrier plate, and providing a through hole structure 110 between each two connected heterogeneous chip structures, where each heterogeneous chip structure includes a plurality of stacked heterogeneous single chips, and a bonding layer 111 is provided between each two adjacent heterogeneous single chips;
step 300, as shown in fig. 7, encapsulating the mounted multi-group heterogeneous chip structure to form a plastic package layer 103;
step S400, as shown in fig. 9, performing a rewiring process on the plastic package layer 103 to form a second rewiring layer 112;
step S500, as shown in fig. 11, covering a passivation layer 102 on the second redistribution layer 112;
step S600, as shown in fig. 10, removing the temporary bonding carrier, and forming a first redistribution layer 113 on a surface of the plastic package layer 103 away from the second redistribution layer 112, where the second redistribution layer 112 and the first redistribution layer 113 are interconnected through the via structure, and both the first redistribution layer 113 and the second redistribution layer can interconnect multiple groups of heterogeneous chip structures;
step S700, as shown in fig. 11, forming a metal bump 114 on a surface of the first redistribution layer 113 away from the plastic package layer 103, where the metal bump 114 can be in signal interconnection with the first redistribution layer 113.
According to the method for manufacturing the 3D packaging structure of the heterogeneous multi-chip, provided by the embodiment of the invention, after high bumps are grown on a supplied chip, the supplied chip is bonded with a bottom chip attached to a temporary bonding film through a bonding layer, and the total height of the bonded chip is ensured to be close to the height of an upper vertical through hole structure and a lower vertical through hole structure by controlling the thickness of a bonding body; then, a wafer-level plastic packaging manufacturing process is used for completing the reconstruction of wafer-level wafers with heterogeneous multi-chips and upper and lower vertical through hole structures; and (3) carrying out wafer-level rewiring process on the front surface and the back surface to complete signal interconnection among heterogeneous multi-chips in the plastic package, thereby realizing high-density three-dimensional integrated 3D packaging. The manufacturing method can effectively reduce the steps of a heterogeneous multi-chip high-density three-dimensional integrated packaging process, improves the system integration level, and is a potential solution for reducing the stress imbalance problem caused by CET mismatching of a system.
Specifically, installing a plurality of prepared heterogeneous chip structures on the temporary bonding carrier plate, and setting a through hole structure between every two connected heterogeneous chip structures, the method includes:
preparing a chip structure with salient points by respectively adopting different process paths according to different incoming material forms of the heterogeneous chip structure;
thinning and scribing the chip structure with the salient points to obtain a bottom layer heterogeneous single-chip structure and a top layer heterogeneous single-chip structure;
mounting the bottom layer heterogeneous single-chip structure and the through hole structure on the temporary bonding carrier plate according to mounting coordinates;
arranging a bonding layer on the surface of the bottom layer heterogeneous single-chip structure, which is far away from the temporary bonding carrier plate;
and correspondingly attaching the top-layer heterogeneous single-chip structure on the bottom-layer heterogeneous single-chip structure according to the installation coordinates, and bonding the top-layer heterogeneous single-chip structure with the bottom-layer heterogeneous single-chip structure through the bonding layer.
Specifically, the method for preparing a chip structure with bumps by respectively adopting different process paths according to different incoming material forms of the heterogeneous chip structure comprises the following steps:
when the incoming material form of the heterogeneous chip structure is a single chip, carrying out plastic package on multiple single chips to form wafer reconstruction;
and performing yellow light treatment and wet etching treatment on the wafer reconstructed structure, and then performing bump growth to obtain the chip structure with the bumps.
Specifically, the method for preparing a chip structure with bumps by respectively adopting different process paths according to different incoming material forms of the heterogeneous chip structure comprises the following steps:
and when the heterogeneous chip structure is in a wafer incoming form, performing yellow light treatment and wet etching treatment on the wafer, and then performing bump growth to obtain the chip structure with the bumps.
A detailed implementation process of the method for manufacturing a 3D package structure with heterogeneous multiple chips according to the embodiment of the present invention is described below with reference to fig. 2 to 12.
Step S11, providing a carrier (glass wafer, steel plate) 100 with the thickness of 700 μm, a temporary bonding film 101, heterogeneous multi-chips and resin plastic package materials, and attaching the temporary bonding film on the carrier to form a temporary bonding carrier for packaging;
it should be understood that the carrier (glass wafer, steel plate), heterogeneous chip, temporary bonding film, resin molding compound, and the temporary bonding carrier for packaging is formed after the temporary bonding film is attached on the glass wafer; the thicknesses of the glass wafer and the steel plate are not less than 300 mu m, and the adhesion force of the temporary bonding film is more than 0.196N/20 mm.
S12, preparing an isomeric single chip with high bumps by adopting different process paths according to different chip feeding forms; the incoming material single chips 104 and 105 can be used for completing the preparation of the high bump growing chips 106 and 107 by a Pad through yellow light and a wet method after the wafer reconstruction is realized by adopting a plastic package mode on various single chips; when the supplied materials are wafers, the preparation of the chips 106 and 107 with the high bumps grown by Pad is finished after yellow light and wet process;
step S13, thinning and scribing the chips 106 and 107 which finish the high bump growth of the Pad to form a single chip;
step S14, mounting the heterogeneous single chips 108 and 109 and the upper and lower vertical through hole body structures 110 on the temporary carrier plate according to coordinates in a Face Down mode;
step S15, after the adhesive body 111 is attached to the back of the bottom layer heterogeneous single chip 108 and 109, the upper layer heterogeneous single chip 106 and 107 are respectively attached to the back of the lower layer single chip 108 and 109 according to the coordinates in a Face Up mode, and the connection is completed through the adhesive layer 111;
step S16, encapsulating the mounted heterogeneous multi-chips by using a resin plastic package material by using a wafer-level plastic package process, and forming a reconstructed resin wafer after curing;
step S17, performing temporary bonding protection on the chip of which the middle and lower layers of the resin wafer adopt a Face Down chip mounting mode, attaching a temporary bonding film 101, thinning the reverse side of the resin wafer, and leaking bumps of the upper and lower chips and copper columns of the upper and lower vertical through hole structures;
step S18, performing a wafer-level rewiring process on the thinned reconstructed wafer with the exposed bumps and the copper pillars to complete preparation of the rewiring layer structure 112, and realizing signal interconnection between various upper heterogeneous chips (106 and 107) and the upper and lower vertical through hole structures 110 through the second rewiring layer 112 to complete packaging of heterogeneous multiple chips in a single-layer horizontal direction;
step S19, after the passivation layer 102 is covered on the surface where the second rewiring layer 112 is completed, a wafer-level rewiring process is performed on the middle and reverse sides of the resin wafer, so as to complete the preparation of the first rewiring layer 113, and signal interconnection between the heterogeneous multi-chips (106, 107, 108, 109) and the upper and lower vertical through-hole structures 110 is realized through the first rewiring layer 113, thereby completing the high-density three-dimensional integrated 3D package.
It should be noted that the first redistribution layer 113 and the second redistribution layer 112 are a wiring process in which a metal layer and a passivation layer are overlapped for multiple times; the minimum number of rewiring layers is 1 metal layer; the thickness of the passivation layer is larger than that of the formed metal layer, and the passivation layer wraps the metal layer; the thickness of the metal layer is not less than 1 μm, and the thickness of the passivation layer is not less than 3 μm.
Step S20, a wafer level ball mounting process is used to fabricate a plurality of metal bumps 114 on the surface of the rewiring layer, so as to achieve signal interconnection between the bumps and the wiring layer structure.
In summary, according to the manufacturing method of the 3D package structure of the heterogeneous multi-chip provided by the embodiment of the present invention, the three-dimensional stacked structure of the heterogeneous multi-chip structure is embedded in the groove of the substrate material, in the three-dimensional integrated 3D package structure, after the multi-chip at the bottom and the multi-chip at the upper layer are bonded into a whole through the bonding body, the upper and lower vertical through hole structures and the stacked multi-chip are integrally plastic-sealed into a whole, and then signal interconnection is realized through a wafer-level rewiring process, so that higher integration is achieved in both the horizontal and vertical directions, and the volume of the integrated micro-system is further reduced. Different from the conventional POP stacking structure, the three-dimensional integrated 3D packaging structure is simpler in process, the multiple flip-chip welding processes required for realizing three-dimensional stacking in the vertical direction are reduced, meanwhile, the reliability of the three-dimensional integrated 3D packaging structure is more dominant, and the stress unbalance risk caused by mismatch of CET is effectively reduced by the integrated structure. In the three-dimensional integrated 3D packaging structure, the conducting structure connected with an internal signal is reserved at the top, and secondary integrated packaging can be carried out with other single chip structures or high-density integrated packaging structures, so that the follow-up packaging integration process is facilitated.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims (10)

1. A3D packaging structure of heterogeneous multichip is characterized by comprising:
a first redistribution layer and a plastic encapsulation layer on the first redistribution layer,
a plurality of groups of heterogeneous chip structures are arranged in the plastic packaging material layer at intervals, a through hole structure is arranged between every two adjacent groups of heterogeneous chip structures, each group of heterogeneous chip structures comprises a plurality of stacked heterogeneous single chips, and a bonding layer is arranged between every two adjacent heterogeneous single chips;
a second rewiring layer is arranged on the surface, away from the first rewiring layer, of the plastic packaging material layer, and a passivation layer is arranged on the surface, away from the plastic packaging material layer, of the second rewiring layer;
the first rewiring layer and the second rewiring layer can be used for signal interconnection of a plurality of heterogeneous chip structures;
the through hole structure is used for communicating the first rewiring layer and the second rewiring layer;
and arranging a metal bump on the surface of the first rewiring layer, which is deviated from the plastic packaging material layer, wherein the metal bump can be in signal interconnection with the first rewiring layer.
2. The 3D packaging structure according to claim 1, wherein two sets of heterogeneous chip structures are disposed at intervals in the molding compound layer, and each set of heterogeneous chip structures includes two heterogeneous single chips stacked together, and an adhesive layer is disposed between the two heterogeneous single chips stacked together.
3. The 3D package structure of claim 1, wherein a height of the via structure is not greater than a thickness of the plastic encapsulant layer.
4. The 3D packaging structure of claim 1, wherein a material of the adhesive layer comprises any one of a thermally conductive adhesive, an alloy solder sheet, and a DAF film material.
5. The 3D packaging structure according to claim 1, wherein a material of the passivation layer includes any one of ABF, CBF and epoxy dry film.
6. The 3D package structure of claim 1, wherein the first and second redistribution layers are made of a material comprising polyimide and copper.
7. A manufacturing method of a 3D packaging structure of heterogeneous multi-chips is characterized by comprising the following steps:
providing a carrier plate, and attaching a temporary bonding film on the carrier plate to form a temporary bonding carrier plate;
mounting a plurality of prepared groups of heterogeneous chip structures on the temporary bonding carrier plate, and arranging a through hole structure between every two connected groups of heterogeneous chip structures, wherein each group of heterogeneous chip structures comprises a plurality of stacked heterogeneous single chips, and an adhesive layer is arranged between every two adjacent heterogeneous single chips;
encapsulating the mounted multi-group heterogeneous chip structure to form a plastic packaging material layer;
performing a rewiring process on the plastic packaging material layer to form a second rewiring layer;
covering a passivation layer on the second rewiring layer;
removing the temporary bonding carrier plate, and forming a first rewiring layer on the surface of the plastic packaging material layer departing from the second rewiring layer, wherein the second rewiring layer and the first rewiring layer are connected with each other through the through hole structure in a signal mode, and the first rewiring layer and the second rewiring layer can be used for connecting multiple groups of heterogeneous chip structures in a signal mode;
and forming a metal bump on the surface of the first rewiring layer, which is away from the plastic packaging material layer, wherein the metal bump can be in signal interconnection with the first rewiring layer.
8. The method of claim 7, wherein mounting the prepared plurality of sets of heterogeneous chip structures on the temporary bonding carrier, and providing a through hole structure between each two connected sets of heterogeneous chip structures comprises:
preparing a chip structure with bumps by respectively adopting different process paths according to different incoming material forms of the heterogeneous chip structure;
thinning and scribing the chip structure with the salient points to obtain a bottom layer heterogeneous single-chip structure and a top layer heterogeneous single-chip structure;
mounting the bottom layer heterogeneous single-chip structure and the through hole structure on the temporary bonding carrier plate according to mounting coordinates;
arranging a bonding layer on the surface of the bottom layer heterogeneous single-chip structure, which is far away from the temporary bonding carrier plate;
and correspondingly attaching the top-layer heterogeneous single-chip structure to the bottom-layer heterogeneous single-chip structure according to the installation coordinates, and bonding the top-layer heterogeneous single-chip structure and the bottom-layer heterogeneous single-chip structure through the bonding layer.
9. The method of claim 8, wherein preparing the chip structure with bumps by using different process paths according to different incoming material forms of the heterogeneous chip structure comprises:
when the incoming material form of the heterogeneous chip structure is a single chip, carrying out plastic package on multiple single chips to form wafer reconstruction;
and performing yellow light treatment and wet etching treatment on the wafer reconstructed structure, and then performing bump growth to obtain the chip structure with the bumps.
10. The method of claim 8, wherein the step of preparing the chip structure with bumps by using different process paths according to different incoming material forms of the heterogeneous chip structure comprises:
and when the heterogeneous chip structure is in a wafer incoming form, performing yellow light treatment and wet etching treatment on the wafer, and then performing bump growth to obtain the chip structure with the bumps.
CN202210665018.8A 2022-06-14 2022-06-14 3D packaging structure of heterogeneous multi-chip and manufacturing method thereof Pending CN115101516A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116779496A (en) * 2023-08-21 2023-09-19 成都汉芯国科集成技术有限公司 3D packaging system and packaging method suitable for heterogeneous integrated multiple chips

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116779496A (en) * 2023-08-21 2023-09-19 成都汉芯国科集成技术有限公司 3D packaging system and packaging method suitable for heterogeneous integrated multiple chips
CN116779496B (en) * 2023-08-21 2023-12-26 成都汉芯国科集成技术有限公司 3D packaging system and packaging method suitable for heterogeneous integrated multiple chips

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