CN217691175U - 3D packaging structure of heterogeneous multi-chip - Google Patents

Abstract

The utility model relates to an integrated circuit encapsulates technical field, specifically discloses a 3D packaging structure of different structure multicore piece, wherein, include: the chip packaging structure comprises a first rewiring layer and a plastic packaging material layer positioned on the first rewiring layer, wherein a plurality of groups of heterogeneous chip structures are arranged at intervals in the plastic packaging material layer, a through hole structure is arranged between every two adjacent groups of heterogeneous chip structures, each group of heterogeneous chip structures comprises a plurality of stacked heterogeneous single chips, and a bonding layer is arranged between every two adjacent heterogeneous single chips; a second rewiring layer is arranged on the surface, away from the first rewiring layer, of the plastic packaging material layer; the first rewiring layer and the second rewiring layer can be used for signal interconnection of multiple heterogeneous chip structures; and the surface of the first rewiring layer departing from the plastic packaging material layer is provided with metal bumps. The utility model provides a 3D packaging structure of different structure multicore piece can satisfy integrate and the small-size requirement of high density.

Description

3D packaging structure of heterogeneous multi-chip

Technical Field

The utility model relates to an integrated circuit encapsulates technical field, especially relates to a 3D packaging structure of different structure multicore piece.

Background

The new generation of high density chip plastic packaging technology integrates chips of different materials, different functions and different sizes and thicknesses, and realizes complete system functions in a packaging structure with a tiny volume.

Based on the requirement, various three-dimensional stacking structures are proposed in the industry, such as a layer-to-layer stacking (Package on Package, abbreviated as POP) three-dimensional stacking structure or a packaging structure in which a chip is mounted after a substrate is grooved for high-density fan-out. After a POP type structure is usually heterogeneous multi-chip integration in a horizontal plane, three-dimensional stacking is realized in the vertical direction through a bonding process, the integration in the vertical direction depends on the bonding process, and hidden danger that Thermal Expansion Coefficients (CET) are not matched exists between layers, so that the risk of the reliability direction is brought; the technology of mounting the heterogeneous multi-chip after slotting on the surface of the substrate overcomes the potential reliability problem of the POP structure, realizes the integration of the heterogeneous multi-chip integrated structure, has complex process flow, has large requirement on the size of the substrate when the requirement on the system integration level is high, and can not meet the requirement on miniaturization of the final packaging structure.

Therefore, how to provide a package structure that can not only realize heterogeneous multi-chip integration, but also satisfy high density and small size has become a technical problem to be solved by those skilled in the art.

Disclosure of Invention

The utility model provides a 3D packaging structure of different structure multicore piece solves the lack of existence among the correlation technique and integrates and the small-size packaging structure's of high density problem.

As an aspect of the utility model provides a 3D packaging structure of different structure multicore piece, wherein, include:

a first redistribution layer and a plastic encapsulation layer on the first redistribution layer,

a plurality of groups of heterogeneous chip structures are arranged in the plastic packaging material layer at intervals, a through hole structure is arranged between every two adjacent groups of heterogeneous chip structures, each group of heterogeneous chip structures comprises a plurality of stacked heterogeneous single chips, and a bonding layer is arranged between every two adjacent heterogeneous single chips;

a second rewiring layer is arranged on the surface, departing from the first rewiring layer, of the plastic package layer, and a passivation layer is arranged on the surface, departing from the plastic package layer, of the second rewiring layer;

the first rewiring layer and the second rewiring layer can be used for signal interconnection of a plurality of groups of heterogeneous chip structures;

the through hole structure is used for communicating the first rewiring layer and the second rewiring layer;

and arranging a metal bump on the surface of the first rewiring layer, which is deviated from the plastic packaging material layer, wherein the metal bump can be in signal interconnection with the first rewiring layer.

Further, the interval sets up two sets of different structure chip structures in the plastic envelope material layer, and every group different structure chip structure all includes two different structure single-chips that pile up the setting, sets up the tie coat between two different structure single-chips that pile up the setting.

Further, the height of the through hole structure is not larger than the thickness of the plastic packaging material layer.

Further, the material for making the bonding layer comprises any one of heat-conducting glue, alloy solder sheet and DAF film material.

Further, the manufacturing material of the passivation layer comprises any one of ABF, CBF and epoxy resin dry film.

Further, the first rewiring layer and the second rewiring layer are made of materials including polyimide and copper.

The utility model provides a 3D packaging structure of heterogeneous multicore piece is different from conventional POP stacked structure, and three-dimensional integrated 3D packaging structure technology is simpler, has reduced three-dimensional many times flip-chip welding process that piles up the realization and need go on the vertical direction, simultaneously, more dominates in the aspect of its reliability, and the structure of integration has effectively reduced the stress unbalance risk that CET mismatch brought. In addition, in the three-dimensional integrated 3D packaging structure, a conducting structure connected with an internal signal is reserved at the top, and secondary integrated packaging can be carried out with other single chip structures or high-density integrated packaging structures, so that the follow-up packaging integration process is facilitated.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:

fig. 1 is a schematic cross-sectional view of a 3D package structure of heterogeneous multi-chips according to the present invention.

Fig. 2 is a schematic view of a temporary bonding carrier plate according to the present invention.

Fig. 3 is a schematic diagram of the incoming material heterogeneous chip adopting a wafer reconstruction mode to prepare high bumps.

Figure 4 is the utility model provides a growth high bump chip attenuate scribing sketch map.

Fig. 5 is the utility model provides a heterogeneous multicore piece of bottom and upper and lower perpendicular through-hole structure mounting schematic diagram.

Fig. 6 is the utility model provides a paste the bonding body at the heterogeneous chip back in bottom and pile up the schematic diagram with the heterogeneous multicore piece in upper strata.

Fig. 7 is the utility model provides a to the whole plastic envelope schematic diagram of the heterogeneous multicore piece of high salient point and the heterogeneous chip stack body of bottom.

Fig. 8 is the utility model provides a chip bump and upper and lower perpendicular through-hole structure copper post schematic diagram are spilt to plastic-sealed body back attenuate.

Fig. 9 is a schematic diagram of wafer-level rewiring on the back surface of the plastic package according to the present invention.

Fig. 10 is a schematic diagram of passivation protection of the front wafer level rewiring layer at the rear side of the rewiring layer.

Fig. 11 is a schematic view of the solder ball preparation provided by the present invention.

Fig. 12 is a specific flowchart of a method for manufacturing a 3D package structure with heterogeneous multiple chips according to the present invention.

Detailed Description

It should be noted that the embodiments and features of the embodiments of the present invention may be combined with each other without conflict. The present invention will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

In order to make the technical solution of the present invention better understood, the technical solution of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts shall belong to the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances for purposes of describing the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In this embodiment, a 3D package structure of heterogeneous multichip is provided, fig. 1 is a cross-sectional view of the 3D package structure of heterogeneous multichip provided by the embodiment of the present invention, as shown in fig. 1, including:

a first redistribution layer 113 and a plastic encapsulation layer 103 on the first redistribution layer 113,

a plurality of groups of heterogeneous chip structures are arranged in the plastic packaging layer 103 at intervals, a through hole structure 110 is arranged between every two adjacent groups of heterogeneous chip structures, each group of heterogeneous chip structures comprises a plurality of stacked heterogeneous single chips, and a bonding layer 111 is arranged between every two adjacent heterogeneous single chips;

a second rewiring layer 112 is arranged on the surface, away from the first rewiring layer 113, of the plastic package layer 103, and a passivation layer 102 is arranged on the surface, away from the plastic package layer 103, of the second rewiring layer 112;

the first redistribution layer 113 and the second redistribution layer 112 can perform signal interconnection on a plurality of heterogeneous chip structures;

the via structure 110 is used to connect the first redistribution layer 113 and the second redistribution layer 112;

a metal bump 114 is arranged on the surface of the first redistribution layer 113 away from the plastic package material layer 103, and the metal bump 114 can be in signal interconnection with the first redistribution layer 113.

The embodiment of the utility model provides an in, this 3D packaging structure of heterogeneous multicore piece is through the three-dimensional stacked structure who imbeds heterogeneous multicore piece structure at the base material fluting, among this three-dimensional integrated 3D packaging structure, the multicore piece of bottom and the multicore piece on upper strata pass through the tie coat and bond as an organic whole back, with upper and lower vertically through-hole structure and pile up the whole plastic envelope of multicore piece as an organic whole back, realize the signal interconnection through wafer level rewiring technology, all have higher integrated level like this at level and vertical direction, and then reduce integrated microsystem's volume.

Therefore, the embodiment of the utility model provides a 3D packaging structure of different structure multicore piece is different from conventional POP stacked structure, and three-dimensional integrated 3D packaging structure technology is simpler, has reduced three-dimensional stacking realization in the vertical direction and has gone on many times flip-chip bonding technology, and simultaneously, more the domination in the aspect of its reliability, the structure of integration has effectively reduced the stress unbalance risk that CET mismatch brought. In addition, in the three-dimensional integrated 3D packaging structure, a conducting structure connected with an internal signal is reserved at the top, and secondary integrated packaging can be carried out with other single chip structures or high-density integrated packaging structures, so that the follow-up packaging integration process is facilitated.

As a specific embodiment, two sets of heterogeneous chip structures are disposed at intervals in the plastic package layer 103, and each set of the heterogeneous chip structures includes two heterogeneous single chips stacked together, and the bonding layer 111 is disposed between the two heterogeneous single chips stacked together.

As shown in fig. 1, one of the sets of heterogeneous chip structures includes a first heterogeneous single chip 108 located on the bottom layer and a second heterogeneous single chip 106 located on the top layer, the other set of heterogeneous single chip structure includes a third heterogeneous single chip 109 located on the bottom layer and a fourth heterogeneous single chip 107 located on the top layer, and the first heterogeneous single chip 108 and the second heterogeneous single chip 106, and the third heterogeneous single chip 109 and the fourth heterogeneous single chip 107 are connected by an adhesive layer 111.

It should be noted that both the second heterogeneous single chip 106 and the fourth heterogeneous single chip 107 have high bumps. Specifically, a second heterogeneous single chip 106 and a fourth heterogeneous single chip 107 with high bumps are respectively bonded to the back surfaces of a first heterogeneous single chip 108 and a third heterogeneous single chip 109 through bonding layers 111, a plurality of heterogeneous single chips and a through hole structure 110 vertical to the upper and lower sides are integrally subjected to plastic package through a plastic package material to form a plastic package material layer 103, the bumps of the second heterogeneous single chip 106 and the fourth heterogeneous single chip 107 and copper columns of the through hole structure 110 vertical to the upper and lower sides are exposed after thinning, signal interconnection between the second heterogeneous single chip 106 and the fourth heterogeneous single chip 107 and the through hole structure 110 is realized through a wafer-level second re-wiring layer 112, single-layer horizontal heterogeneous multi-chip packaging is completed, and a passivation layer 102 covers the surface of the second re-wiring layer 112 to protect the second heterogeneous single chip and the fourth heterogeneous single chip; signal interconnection of the second heterogeneous single chip 106, the fourth heterogeneous single chip 107, the first heterogeneous single chip 108 and the third heterogeneous single chip 109 and the through hole structure 110 is realized through the first rewiring layer 113 at the wafer level, and high-density three-dimensional integrated 3D packaging is completed; the metal bumps 114 are formed on the surface of the first redistribution layer 113 facing away from the plastic package layer 103.

In the embodiment of the present invention, the height of the through hole structure 110 is not greater than the thickness of the plastic package material layer 103.

It should be understood that the incoming material chip for manufacturing the second heterogeneous single chip 106 and the fourth heterogeneous single chip 107 with the high bumps may be a single chip, or may be in a wafer form, and after the incoming material single chip is reconfigured by plastically packaging the single chip, the incoming material single chip is subjected to yellow light, wet process, thinning and scribing to form the second heterogeneous single chip 106 and the fourth heterogeneous single chip 107 with the high bumps for a single Pad; when the supplied materials are wafers, the wafers are subjected to yellow light, wet process, thinning and scribing to form a second heterogeneous single chip 106 and a fourth heterogeneous single chip 107 with a single Pad growing high salient point, wherein the passivation layer material 102 in the yellow light process can be ABF, CBF and epoxy resin dry films, and the high salient point material in the wet process can be tin-lead, tin-silver and tin-silver-copper.

That is, in the embodiment of the present invention, the material of the passivation layer 102 includes any one of ABF, CBF and epoxy dry film.

Specifically, the material of the adhesive layer 111 includes any one of a heat conductive paste, an alloy solder sheet, and a DAF film material.

In an embodiment of the present invention, the material for manufacturing the first redistribution layer 113 and the second redistribution layer 112 includes polyimide and copper.

Specifically, the back surface of the second heterogeneous single chip 106 is connected to the back of the first heterogeneous single chip 108 through an adhesive layer 111, the back surface of the fourth heterogeneous single chip 107 is connected to the back of the third heterogeneous single chip 109 through the adhesive layer 111, and the material of the adhesive layer 111 may be low-temperature heat-conducting glue, an alloy solder sheet, or a DAF film material; the thickness of the adhesive layer should ensure that the thickness of the second heterogeneous single chip 106, the adhesive layer 111 and the first heterogeneous single chip 108 is generally close to the height of the vertical through hole structure 110, and the thickness of the fourth heterogeneous single chip 107, the adhesive layer 111 and the third heterogeneous single chip 109 is generally close to the height of the vertical through hole structure 110.

Specifically, the metal bumps 114 are formed by a wafer-level ball-mounting or single-chip-screen ball-mounting process, and are kept in signal interconnection with the first redistribution layer 113, and the material includes tin-lead, tin-silver, and tin-silver-copper.

As another embodiment of the present invention, a method for manufacturing a 3D package structure with heterogeneous multiple chips is provided, wherein as shown in fig. 2 to 11, the method includes:

step S100, as shown in fig. 2, providing a carrier 100, and attaching a temporary bonding film 101 on the carrier 100 to form a temporary bonding carrier;

step S200, as shown in fig. 6, mounting a plurality of prepared heterogeneous chip structures on the temporary bonding carrier plate, and providing a through hole structure 110 between each two connected heterogeneous chip structures, where each heterogeneous chip structure includes a plurality of stacked heterogeneous single chips, and a bonding layer 111 is provided between each two adjacent heterogeneous single chips;

step 300, as shown in fig. 7, encapsulating the mounted multi-group heterogeneous chip structure to form a plastic package layer 103;

step S400, as shown in fig. 9, performing a rewiring process on the plastic package layer 103 to form a second rewiring layer 112;

step S500, as shown in fig. 11, covering a passivation layer 102 on the second redistribution layer 112;

step S600, as shown in fig. 10, removing the temporary bonding carrier, and forming a first redistribution layer 113 on a surface of the plastic package layer 103 away from the second redistribution layer 112, where the second redistribution layer 112 and the first redistribution layer 113 are interconnected through the via structure, and both the first redistribution layer 113 and the second redistribution layer can interconnect multiple groups of heterogeneous chip structures;

step S700, as shown in fig. 11, forming a metal bump 114 on a surface of the first redistribution layer 113 away from the plastic package layer 103, where the metal bump 114 can be in signal interconnection with the first redistribution layer 113.

The embodiment of the utility model provides a 3D packaging structure's of different structure multicore piece preparation method, through to the supplied materials chip growth high bump after, accomplish the bonding through the adhesive linkage and the bottom chip of dress on the interim bonding film to through the thickness of control bonding body, guarantee that the chip overall height after the bonding is close to the height of vertical through-hole structure from top to bottom; then, a wafer-level plastic packaging manufacturing process is used for completing the reconstruction of the wafer-level wafer with the heterogeneous multi-chip structure and the vertical through hole structure; and (3) carrying out wafer-level rewiring process on the front surface and the back surface to complete signal interconnection among heterogeneous multi-chips in the plastic package, thereby realizing high-density three-dimensional integrated 3D packaging. The manufacturing method can effectively reduce the steps of a heterogeneous multi-chip high-density three-dimensional integrated packaging process, improves the system integration level, and is a potential solution for reducing the stress imbalance problem caused by the mismatch of the CET of the system.

Specifically, installing a plurality of prepared heterogeneous chip structures on the temporary bonding carrier plate, and setting a through hole structure between each two connected heterogeneous chip structures, includes:

preparing a chip structure with salient points by respectively adopting different process paths according to different incoming material forms of the heterogeneous chip structure;

thinning and scribing the chip structure with the salient points to obtain a bottom layer heterogeneous single-chip structure and a top layer heterogeneous single-chip structure;

mounting the bottom layer heterogeneous single-chip structure and the through hole structure on the temporary bonding carrier plate according to mounting coordinates;

arranging an adhesive layer on the surface of the bottom layer heterogeneous single-chip structure, which is far away from the temporary bonding carrier plate;

and correspondingly attaching the top-layer heterogeneous single-chip structure to the bottom-layer heterogeneous single-chip structure according to the installation coordinates, and bonding the top-layer heterogeneous single-chip structure and the bottom-layer heterogeneous single-chip structure through the bonding layer.

Specifically, the method for preparing a chip structure with bumps by respectively adopting different process paths according to different incoming material forms of the heterogeneous chip structure comprises the following steps:

when the incoming material form of the heterogeneous chip structure is a single chip, carrying out plastic package on multiple single chips to form wafer reconstruction;

and performing yellow light treatment and wet etching treatment on the wafer reconstructed structure, and then performing bump growth to obtain the chip structure with the bumps.

Specifically, the method for preparing a chip structure with bumps by respectively adopting different process paths according to different incoming material forms of the heterogeneous chip structure comprises the following steps:

and when the incoming material form of the heterogeneous chip structure is a wafer, growing the salient points after performing yellow light treatment and wet etching treatment on the wafer to obtain the chip structure with the salient points.

The following describes in detail a specific implementation process of the method for manufacturing a 3D package structure with heterogeneous multiple chips according to an embodiment of the present invention with reference to fig. 2 to 12.

S11, providing a carrier plate (glass wafer, steel plate) 100 with the thickness of 700 mu m, a temporary bonding film 101, heterogeneous multi-chips and a resin plastic package material, and attaching the temporary bonding film on the carrier plate to form a temporary bonding carrier plate for packaging;

it should be understood that the carrier (glass wafer, steel plate), heterogeneous chip, temporary bonding film, resin molding compound, after attaching the temporary bonding film on the glass wafer, form a temporary bonding carrier for packaging; the thicknesses of the glass wafer and the steel plate are not less than 300 mu m, and the adhesion force of the temporary bonding film is more than 0.196N/20mm.

S12, preparing an isomeric single chip with high bumps by adopting different process paths according to different chip incoming material forms; the incoming material single chips 104 and 105 can be prepared by completing the preparation of the high bump growing chips 106 and 107 by a Pad through yellow light and a wet method after the wafer reconstruction is realized by adopting a plastic package mode for various single chips; when the supplied materials are wafers, the preparation of the chips 106 and 107 with the Pad growth high salient points is finished after yellow light and wet process;

s13, thinning and scribing the chips 106 and 107 which finish the Pad growth high salient points to form a single chip;

s14, mounting the heterogeneous single chips 108 and 109 and the upper and lower vertical through hole body structures 110 on the temporary carrier plate according to coordinates in a Face Down mode;

step S15, after the adhesive body 111 is attached to the back surfaces of the bottom layer heterogeneous single chips 108 and 109, the upper layer heterogeneous single chips 106 and 107 are respectively attached to the back surfaces of the lower layer single chips 108 and 109 according to coordinates in a Face Up mode, and connection is completed through the adhesive layer 111;

s16, encapsulating the pasted heterogeneous multi-chip by using a resin plastic package material by using a wafer-level plastic package process, and forming a reconstructed resin wafer after curing;

s17, performing temporary bonding protection on the chip with the lower layer in the resin wafer in a Face Down chip mounting mode, attaching a temporary bonding film 101, thinning the reverse side of the resin wafer, and leaking the salient points of the upper chip and the lower chip and the copper columns of the upper vertical through hole structure and the lower vertical through hole structure;

step S18, carrying out a wafer-level rewiring process on the thinned reconstructed wafer with the exposed bumps and copper columns to complete preparation of a rewiring layer structure 112, and realizing signal interconnection between various upper heterogeneous chips (106 and 107) and the upper and lower vertical through hole structures 110 through the second rewiring layer 112 to complete packaging of heterogeneous multiple chips in a single-layer horizontal direction;

step S19, after the surface of the second rewiring layer 112 is covered with the passivation layer 102, a wafer-level rewiring process is performed on the middle and reverse sides of the resin wafer, the first rewiring layer 113 is prepared, signal interconnection between the heterogeneous multi-chips (106, 107, 108 and 109) and the upper and lower vertical through hole structures 110 is achieved through the first rewiring layer 113, and high-density three-dimensional integrated 3D packaging is completed.

It should be noted that the first redistribution layer 113 and the second redistribution layer 112 are a wiring process in which a metal layer and a passivation layer are overlapped for multiple times; the minimum number of rewiring layers is 1 metal layer; the thickness of the passivation layer is larger than that of the formed metal layer, and the passivation layer wraps the metal layer; the thickness of the metal layer is not less than 1 μm, and the thickness of the passivation layer is not less than 3 μm.

Step S20, a wafer-level ball mounting process is used to fabricate a plurality of metal bumps 114 on the surface of the rewiring layer, so as to achieve signal interconnection between the bumps and the wiring layer structure.

To sum up, the embodiment of the utility model provides a manufacturing method of 3D packaging structure of different structure multicore piece, through the three-dimensional stacked structure who imbeds different structure multicore piece structure at the base material fluting, in this three-dimensional integrated 3D packaging structure, the multicore piece of bottom and the multicore piece on upper strata are through bonding body bonding back as an organic whole, will be from top to bottom perpendicular through-hole structure with pile up the whole plastic envelope of multicore piece after as an organic whole, realize the signal interconnection through wafer level rewiring technology, all have higher integrated level like this at level and vertical direction, and then reduce integrated microsystem's volume. Different from the conventional POP stacking structure, the three-dimensional integrated 3D packaging structure is simpler in process, the multiple flip-chip welding processes required for realizing three-dimensional stacking in the vertical direction are reduced, meanwhile, the reliability of the three-dimensional integrated 3D packaging structure is more dominant, and the stress unbalance risk caused by mismatch of CET is effectively reduced by the integrated structure. In the three-dimensional integrated 3D packaging structure, the top is reserved with a conducting structure connected with an internal signal, and the three-dimensional integrated 3D packaging structure can be secondarily integrated and packaged with other single chip structures or high-density integrated packaging structures, so that the subsequent packaging and integration process is facilitated.

It is to be understood that the above embodiments are merely exemplary embodiments that have been employed to illustrate the principles of the present invention, and that the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims (6)

1. A3D packaging structure of heterogeneous multichip is characterized by comprising:

a first redistribution layer and a plastic encapsulation layer on the first redistribution layer,

a plurality of groups of heterogeneous chip structures are arranged in the plastic packaging material layer at intervals, a through hole structure is arranged between every two adjacent groups of heterogeneous chip structures, each group of heterogeneous chip structures comprises a plurality of stacked heterogeneous single chips, and a bonding layer is arranged between every two adjacent heterogeneous single chips;

a second rewiring layer is arranged on the surface, away from the first rewiring layer, of the plastic packaging material layer, and a passivation layer is arranged on the surface, away from the plastic packaging material layer, of the second rewiring layer;

the first rewiring layer and the second rewiring layer can be used for signal interconnection of a plurality of groups of heterogeneous chip structures;

the through hole structure is used for communicating the first rewiring layer and the second rewiring layer;

and arranging a metal bump on the surface of the first rewiring layer deviating from the plastic packaging material layer, wherein the metal bump can be in signal interconnection with the first rewiring layer.

2. The 3D packaging structure according to claim 1, wherein two sets of heterogeneous chip structures are disposed at intervals in the molding compound layer, and each set of heterogeneous chip structures includes two heterogeneous single chips stacked together, and an adhesive layer is disposed between the two heterogeneous single chips stacked together.

3. The 3D package structure of claim 1, wherein a height of the via structure is not greater than a thickness of the plastic encapsulant layer.

4. The 3D package structure of claim 1, wherein a material of the adhesive layer comprises any one of a thermally conductive adhesive, an alloy solder sheet, and a DAF film material.

5. The 3D packaging structure according to claim 1, wherein a material of the passivation layer includes any one of ABF, CBF and epoxy dry film.

6. The 3D package structure of claim 1, wherein the first and second redistribution layers are made of a material comprising polyimide and copper.

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