CN117609133B - MIPI high-speed channel circuit with offset self-calibration function and calibration method - Google Patents

MIPI high-speed channel circuit with offset self-calibration function and calibration method Download PDF

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Publication number
CN117609133B
CN117609133B CN202410085464.0A CN202410085464A CN117609133B CN 117609133 B CN117609133 B CN 117609133B CN 202410085464 A CN202410085464 A CN 202410085464A CN 117609133 B CN117609133 B CN 117609133B
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pmos tube
current
pmos
tube
electrode
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CN117609133A (en
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刘铠
秦昌兵
张白雪
张春
陈啟宏
杨建兵
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Nanjing Guozhao Photoelectric Technology Co ltd
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Nanjing Guozhao Photoelectric Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses an MIPI high-speed channel circuit with offset self-calibration and a calibration method, comprising the following steps: the digital algorithm for calibrating the offset voltage is divided into two steps, the digital algorithm for calibrating the offset voltage is controlled by a digital code with larger weight to output a current with larger step size, the calibration range is enlarged, the current with smaller step size is controlled by a digital code with smaller weight to output a current with smaller step size, the calibration precision is improved, and the range and the precision of the offset voltage are both considered.

Description

MIPI high-speed channel circuit with offset self-calibration function and calibration method
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an MIPI high-speed channel circuit with offset self-calibration and a calibration method.
Background
The mobile industry processor interface (Mobile Industry Processor Interface, MIPI) is the currently mainstream mobile terminal interface, supporting a high-speed mode of differential transmission and a low-power mode of single-ended transmission. The high-speed channel module is a core circuit of the MIPI interface and directly determines the highest transmission rate of the interface. The high-speed channel adopts a differential input structure, and due to the influence of process errors and random errors, the MOS tube is mismatched to a certain extent, so that offset voltage exists in the differential input tube, and when the offset voltage is superposed on the common-mode voltage at one end of the differential signal, the threshold voltage required by output turnover can be changed, thereby influencing the duty ratio of the output signal. Compared with low-speed data, the rising/falling time of the high-speed data occupies a larger proportion in the data period, and after offset voltage is superimposed, the duty ratio of the high-speed output data is influenced more, so that the offset voltage is more likely to cause errors in the sampling of the high-speed data, and error codes are caused.
To reduce the error rate, offset calibration is required for the high-speed channel, and common offset elimination techniques include auto-zeroing, chopping and common mode feedback compensation. The automatic zeroing uses a switched capacitor to extract the offset voltage and offset the offset voltage at the input or output, and the extraction of the offset voltage requires an additional switching period, limiting the maximum transmission rate of the data. The chopper technology uses square wave signal coupling modulation at the input, demodulates at the output, finally filters out the offset voltage in the high frequency band, and suppresses the output ripple and requires a larger filter capacitor, which occupies extra chip area and has a larger cost. The common mode feedback compensation utilizes a low pass filter to feed back the direct current offset voltage of the output end to the input end, and a larger capacitance area is also required, and the stability of the circuit can be influenced by the introduced feedback loop.
Disclosure of Invention
The technical purpose is that: aiming at the defects that the data transmission rate is affected and the occupied area is large when the traditional calibration technology is applied to an MIPI circuit, the invention discloses an MIPI high-speed channel circuit with offset self-calibration and a calibration method, which can reduce errors caused by offset voltage in transmission and realize high-speed and high-precision transmission effect.
The technical scheme is as follows: in order to achieve the technical purpose, the invention adopts the following technical scheme:
an MIPI high-speed channel circuit with offset self-calibration, comprising:
The pre-amplifier comprises an output signal positive end O2P and an output signal negative end O2N, and is used for amplifying an input signal;
the hysteresis comparator comprises a positive input end and a negative input end, wherein the positive input end is connected with an output signal positive end O2P of the pre-amplifier, and the negative input end is connected with an output signal negative end O2N of the pre-amplifier and is used for comparing signals amplified by the pre-amplifier and outputting a single-ended signal OUT and an intermediate signal O3N, O P corresponding to transmission data;
The calibration switch is respectively connected with the hysteresis comparator and the calibration comparator and is used for controlling the input end of the calibration comparator;
The calibration comparator comprises a positive phase input end and a negative phase input end, wherein the positive phase input end receives an intermediate signal O3P, the negative phase input end receives an intermediate signal O3N, and is used for judging the polarities of the intermediate signals O3P and O3N output by the hysteresis comparator and converting a comparison result into a 1-bit digital code COMP and outputting the 1-bit digital code COMP to the offset calibration algorithm module;
The OFFSET calibration algorithm module is used for calculating a comparison result of the calibration comparator, and is used for generating two digital codes S <6:0>, L <2:0> and a selection signal SEL <1:0> of weight to control the current output of the programmable current source, and generating a calibration end signal OFFSET_EN to control the on-off of the calibration switch;
and the programmable current source is used for outputting a calibration current to the output end of the pre-amplifying stage of the pre-amplifier to compensate the offset voltage.
The invention also provides a calibration method of the MIPI high-speed channel circuit with offset self-calibration, which is applied to the MIPI high-speed channel circuit with offset self-calibration and comprises the following steps:
S1, inputting a transmission signal, and transmitting the transmission signal to a hysteresis comparator after being amplified by a pre-amplifier;
S2, comparing the signals amplified by the pre-amplifier by the hysteresis comparator, outputting the normal signals into corresponding single-ended signals during normal operation, and inputting signals only containing offset voltage to the calibration switch during offset calibration;
S3, the OFFSET calibration algorithm module sends a calibration end signal OFFSET_EN to control the conduction of a calibration switch, a signal containing OFFSET voltage is transmitted to a calibration comparator, the calibration comparator carries out polarity judgment on an input signal containing OFFSET voltage, then the comparison result is converted into a digital code COMP (1), and the digital code COMP is output to the OFFSET calibration algorithm module;
S4, outputting a corresponding selection signal SEL <1:0> and two digital codes S <6:0> and L <2:0> with two weights to a programmable current source by a maladjustment calibration algorithm module according to the magnitude of maladjustment voltage, and outputting corresponding current to the output end of a preamplification stage of the preamplifier by the programmable current source until obtaining a final proper compensation current I_CAL;
S5, outputting a calibration ending signal OFFSET_EN with the value of 0 to a calibration switch by the OFFSET calibration algorithm module, closing the calibration switch and the calibration comparator, and ending the calibration.
The beneficial effects are that: the MIPI high-speed channel circuit with offset self-calibration and the calibration method provided by the invention have the following beneficial effects:
The offset calibration algorithm module generates two digital codes S <6:0>, L <2:0> and a selection signal SEL <1:0> of two weights to adjust the output current of the programmable current source to offset voltage for compensation, the magnitude of the output current of the programmable current source and a current output port can be controlled, a periodic refreshing calibration result is not needed, no additional capacitor is introduced, high-speed data transmission of the MIPI circuit can be started after power-on calibration is finished, the speed is high, the area is small, and calibration of offset voltage can be realized under the condition that the high-speed transmission performance of MIPI is not influenced.
The offset calibration algorithm for calibrating offset voltage provided by the invention is divided into two steps, the digital code L <2:0> with larger weight is used for controlling the current with larger output step length of the programmable current source, the calibration range is enlarged, the digital code S <6:0> with smaller weight is used for controlling the current with smaller output step length of the programmable current source, the calibration precision is improved, and the range and the precision of calibrating offset voltage are both considered.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below.
FIG. 1 is a system block diagram of an MIPI high-speed channel circuit with offset self-calibration in accordance with the present invention;
FIG. 2 is a circuit diagram of a calibration comparator according to the present invention;
FIG. 3 is a circuit diagram of a programmable current source normal phase calibration current source IOUTP circuit according to the present invention;
FIG. 4 is a calibration flow chart of the offset calibration algorithm module of the present invention;
FIG. 5 is a graph showing the variation of offset calibration current according to the present invention.
Detailed Description
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, but in which the invention is not so limited.
As shown in fig. 1, an MIPI high-speed channel circuit with offset self-calibration, comprising:
The pre-amplifier comprises an output signal positive end O2P and an output signal negative end O2N, and is used for amplifying an input signal;
the hysteresis comparator comprises a positive input end and a negative input end, wherein the positive input end is connected with an output signal positive end O2P of the pre-amplifier, and the negative input end is connected with an output signal negative end O2N of the pre-amplifier and is used for comparing signals amplified by the pre-amplifier and outputting a single-ended signal OUT and an intermediate signal O3N, O P corresponding to transmission data;
The calibration switch is respectively connected with the hysteresis comparator and the calibration comparator and is used for controlling the input end of the calibration comparator;
The calibration comparator comprises a positive phase input end and a negative phase input end, wherein the positive phase input end receives an intermediate signal O3P, the negative phase input end receives an intermediate signal O3N, and is used for judging the polarities of the intermediate signals O3P and O3N output by the hysteresis comparator and converting a comparison result into a 1-bit digital code COMP and outputting the 1-bit digital code COMP to the offset calibration algorithm module;
the OFFSET calibration algorithm module is used for calculating a comparison result of the calibration comparator, generating two digital codes S <6:0>, L <2:0> and a current injection direction selection signal SEL <1:0> with weight to control current output of the programmable current source, and generating a calibration end signal OFFSET_EN to control on-off of the calibration switch;
and the programmable current source is used for outputting a calibration current to the output end of the pre-amplifying stage of the pre-amplifier to compensate the offset voltage.
As shown in fig. 1, the output end of the pre-amplifying stage includes an output positive end O1P and an output negative end O1N, the programmable current source includes a negative phase calibration current source IOUTN circuit and a positive phase calibration current source IOUTP circuit, the negative phase calibration current source IOUTN circuit and the positive phase calibration current source IOUTP circuit each include two currents, namely, a current with a larger step size and a current with a smaller step size, respectively corresponding to the digital code L <2:0> and the digital code S <6:0>, the current with a larger step size means that the current value is greatly changed compared with the previous current value, the current with a smaller step size means that the current value is very small compared with the previous current value, the negative phase calibration current source IOUTN circuit outputs the negative phase calibration current IOUTN to the output negative end O1N of the pre-amplifying stage when the selection signal SEL <1:0> is 01, and the positive phase calibration current source IOUTP circuit outputs the positive phase calibration current IOUTP to the output positive end O1P when the selection signal SEL <1:0> is 10.
The pre-amplifier comprises a pre-amplifier stage and a differential operational amplifier, wherein the pre-amplifier stage is a basic differential pair with a resistor, the differential operational amplifier is an active load differential pair in a symmetrical form and is used for amplifying an input signal, the positive end O2P of an output signal of the pre-amplifier is connected to the positive input end of a hysteresis comparator, and the negative end O2N of the output signal of the pre-amplifier is connected to the negative input end of the hysteresis comparator; the hysteresis comparator is used for comparing the signals after the pre-amplification, outputting a single-ended signal OUT corresponding to transmission data, and simultaneously outputting an intermediate signal O3N, O P which is connected to the calibration comparator through the calibration switch; the calibration switch controls the input end of the calibration comparator, and the on-off is controlled by a calibration end signal OFFSET_EN of the OFFSET calibration algorithm module; the calibration comparator judges the polarity of the input signal, then converts the comparison result into a 1-bit digital code COMP, and outputs the 1-bit digital code COMP to the offset calibration algorithm module; the OFFSET calibration algorithm module divides the comparison result COMP into two steps for operation, generates two digital codes S <6:0>, L <2:0> and current injection direction selection signals SEL <1:0> with two weights to control the output of the programmable current source, and after the calibration is completed, the OFFSET_EN with the output of 0 turns off the calibration switch and the calibration comparator to reduce the power consumption; the programmable current source is divided into two parts of currents, which respectively correspond to two digital codes S <6:0> and L <2:0>, and outputs a negative phase calibration current IOUTN to the output negative terminal O1N of the pre-amplification stage of the pre-amplifier when the selection signal SEL <1:0> is 01, or outputs a positive phase calibration current IOUTP to the output positive terminal O1P of the pre-amplification stage of the pre-amplifier when the selection signal SEL <1:0> is 10, so as to compensate offset voltage.
As shown in FIG. 2, the calibration comparator comprises a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, a PMOS tube M4, a PMOS tube M9, a PMOS tube M10, a PMOS tube M11, a PMOS tube M12, a PMOS tube M14, a PMOS tube M15, a PMOS tube M17, a PMOS tube M18, a PMOS tube M20 and a PMOS tube M21, an NMOS tube M5, an NMOS tube M6, an NMOS tube M7, an NMOS tube M8, an NMOS tube M13, an NMOS tube M16 and an NMOS tube M19, an inverter I1, The grid electrode of the PMOS tube M1 is connected with an input signal VINP, the drain electrode of the PMOS tube M1 is connected with the drain electrode of the NMOS tube M5 and the source electrode of the NMOS tube M7, and the source electrode of the PMOS tube M1 is connected with one end of the resistor R1 and the drain electrode of the PMOS tube M3; the other end of the resistor R1 is connected with the source electrode of the PMOS tube M3, one end of the resistor R2 and the output end of the reference current IREF, and the input end of the reference current IREF is connected with the power supply VDD, the source electrode of the PMOS tube M11, the source electrode of the PMOS tube M12, the source electrode of the PMOS tube M15, the source electrode of the PMOS tube M18 and the source electrode of the PMOS tube M21; the grid electrode of the PMOS tube M2 is connected with an input signal VINN, the drain electrode of the PMOS tube M2 is connected with the drain electrode of the NMOS tube M6 and the source electrode of the NMOS tube M8, and the source electrode of the PMOS tube M2 is connected with one end of the resistor R2 and the drain electrode of the PMOS tube M4; the grid electrode of the PMOS tube M3 is connected with a power supply VDD, and the grid electrode of the PMOS tube M4 is connected with the output end OUTN of the inverter I2; the grid electrode of the NMOS tube M5 and the grid electrode of the NMOS tube M6 are connected with a reference voltage VB1, and the source electrode of the NMOS tube M5 and the source electrode of the NMOS tube M6 are connected with the ground GND; the grid electrode of the NMOS tube M7 and the grid electrode of the NMOS tube M8 are connected with a reference voltage VB2, and the drain electrode of the NMOS tube M7 is connected with the drain electrode of the PMOS tube M9, the grid electrode of the PMOS tube M11 and the grid electrode of the PMOS tube M12; the drain electrode of the NMOS tube M8 is connected with the drain electrode of the PMOS tube M10 and the grid electrode of the NMOS tube M13; the grid electrode of the PMOS tube M9 and the grid electrode of the PMOS tube M10 are connected with a reference voltage VB3, and the source electrode of the PMOS tube M9 is connected with the drain electrode of the PMOS tube M11; the source electrode of the PMOS tube M10 is connected with the drain electrode of the PMOS tube M12; the source electrode of the NMOS tube M13, the source electrode of the NMOS tube M16 and the source electrode of the NMOS tube M19 are connected with the ground GND, and the drain electrode of the NMOS tube M13 is connected with the drain electrode of the PMOS tube M14 and the grid electrode of the NMOS tube M16; the grid electrode of the PMOS tube M14, the grid electrode of the PMOS tube M17 and the grid electrode of the PMOS tube M20 are connected with the reference voltage VB3, and the source electrode of the PMOS tube M14 is connected with the drain electrode of the PMOS tube M15; the grid electrode of the PMOS tube M15, the grid electrode of the PMOS tube M18 and the grid electrode of the PMOS tube M21 are connected with a reference voltage VB 4; the drain electrode of the NMOS tube M16 is connected with the drain electrode of the PMOS tube M17 and the grid electrode of the NMOS tube M19, and the source electrode of the PMOS tube M17 is connected with the drain electrode of the PMOS tube M18; the drain electrode of the NMOS tube M19 is connected with the drain electrode of the PMOS tube M20 and the input end of the inverter I1, and the source electrode of the PMOS tube M20 is connected with the drain electrode of the PMOS tube M21; the output end of the inverter I1 is connected to the input end of the inverter I2, and the output end OUTN of the inverter I2 is connected with the input end of the inverter I3; the output of the inverter I3 outputs a 1-bit digital code COMP.
When comp=1, it indicates that the calibration current output by the programmable current source is close to the appropriate compensation current, and when comp=0, it indicates that the offset voltage has not been calibrated, and it is necessary to further adjust the output of the programmable current source.
As shown in fig. 3, the normal phase calibration current source IOUTP circuit of the programmable current source includes a PMOS transistor M22, a PMOS transistor M23, a PMOS transistor M24, a PMOS transistor M25, a PMOS transistor M26, a PMOS transistor M36, an NMOS transistor M37, a first step-size small current circuit, a second step-size small current circuit, a third step-size small current circuit, a fourth step-size small current circuit, a fifth step-size small current circuit, a sixth step-size small current circuit, a seventh step-size small current circuit, a first step-size large current circuit, a second step-size large current circuit, and a third step-size large current circuit, wherein the first step-size small current circuit, the second step-size small current circuit, the fourth step-size small current circuit, the fifth step-size small current circuit, the sixth step-size small current circuit, the seventh step-size small current circuit, the first step-size large current circuit, the second step-size large current circuit, and the third step-size large current circuit all include a switch and three PMOS transistors, the source of the PMOS transistor M22, the source of the PMOS transistor M24, the source of the PMOS transistor M26, the drain of the PMOS transistor M23, and the drain of the PMOS transistor M23 are connected to the drain of the PMOS transistor M23, and the drain of the PMOS transistor M23; the output end of the reference current IREF2 and the output end of the reference current IREF1 are connected with the ground GND; the source electrode of the PMOS tube M25 is connected with the drain electrode of the PMOS tube M24, and the drain electrode of the PMOS tube M25 is connected with the input end of the reference current IREF1 and the grid electrode of the PMOS tube M24; the grid electrode of the PMOS tube M26 is connected with an enable signal EN, and the drain electrode of the PMOS tube M26 is connected with the grid electrode of the PMOS tube M24 and the input end of the reference current IREF 1; the first step-size small current circuit, the second step-size small current circuit, the third step-size small current circuit, the fourth step-size small current circuit, the fifth step-size small current circuit, the sixth step-size small current circuit, the seventh step-size small current circuit, the first step-size large current circuit, the second step-size large current circuit and the third step-size large current circuit are all connected with a power supply VDD, a drain electrode of a PMOS tube M26, a reference current IREF2, a source electrode of a PMOS tube M36 and a drain electrode of an NMOS tube M37; the drain electrode of the NMOS tube M37 is connected with the source electrode of the PMOS tube M36, the source electrode of the NMOS tube M37 is connected with the ground GND, the grid electrode of the NMOS tube M37 and the grid electrode of the PMOS tube M36 are commonly connected to a selection signal SEL <1:0>, and the drain electrode output of the PMOS tube M36 is the normal phase output current IOUTP of a programmable current source.
In a specific embodiment, as shown in fig. 3, the first step-size small current circuit includes a switch S0, a PMOS transistor PM11, a PMOS transistor PM12, and a PMOS transistor PM13, the second step-size small current circuit includes a switch S1, a PMOS transistor PM21, a PMOS transistor PM22, and a PMOS transistor PM23, the third step-size small current circuit includes a switch S2, a PMOS transistor PM31, a PMOS transistor PM32, and a PMOS transistor PM33, the fourth step-size small current circuit includes a switch S3, a PMOS transistor PM41, a PMOS transistor PM42, and a PMOS transistor PM43, the fifth step-size small current circuit includes a switch S4, a PMOS transistor PM51, a PMOS transistor PM52, and a PMOS transistor PM53, the sixth step-size small current circuit includes a switch S5, a PMOS transistor PM61, a PMOS transistor PM62, and a PMOS transistor PM63, the seventh step-size small current circuit includes a switch S6, a PMOS transistor PM71, a PMOS transistor PM72, and a PMOS transistor PM73, the first step-size large current circuit includes a switch L0, a PMOS transistor M27, a PMOS transistor M28, a PMOS transistor M29, and a PMOS transistor M32, and a third step-size large current circuit includes a switch M32, and a PMOS transistor M33, and a third step-size large current circuit includes a switch M3;
The drain electrode of the PMOS tube PM11 is connected with the source electrode of the PMOS tube M36, the grid electrode of the PMOS tube PM11 is connected with the input end of the reference current IREF2, and the source electrode of the PMOS tube PM11 is connected with the drain electrode of the PMOS tube PM 12; the source of the PMOS tube PM12 and the source of the PMOS tube PM13 are connected with a power supply VDD, the grid of the PMOS tube PM12 is connected with the drain of the PMOS tube PM13 and one end of a switch S0, the other end of the switch S0 is connected with the drain of a PMOS tube M26, and the grid of the PMOS tube PM13 is connected with a control signal S <0> of the switch S0;
The drain electrode of the PMOS tube PM21 is connected with the source electrode of the PMOS tube M36, the grid electrode of the PMOS tube PM21 is connected with the input end of the reference current IREF2, and the source electrode of the PMOS tube PM21 is connected with the drain electrode of the PMOS tube PM 22; the source of the PMOS tube PM22 and the source of the PMOS tube PM23 are connected with a power supply VDD, the grid of the PMOS tube PM22 is connected with the drain of the PMOS tube PM23 and one end of a switch S1, the other end of the switch S1 is connected with the drain of a PMOS tube M26, and the grid of the PMOS tube PM23 is connected with a control signal S <1> of the switch S1;
the drain electrode of the PMOS tube PM31 is connected with the source electrode of the PMOS tube M36, the grid electrode of the PMOS tube PM31 is connected with the input end of the reference current IREF2, and the source electrode of the PMOS tube PM31 is connected with the drain electrode of the PMOS tube PM 32; the source of the PMOS tube PM32 and the source of the PMOS tube PM33 are connected with a power supply VDD, the grid of the PMOS tube PM32 is connected with the drain of the PMOS tube PM33 and one end of a switch S2, the other end of the switch S2 is connected with the drain of a PMOS tube M26, and the grid of the PMOS tube PM33 is connected with a control signal S <2> of the switch S2;
The drain electrode of the PMOS tube PM41 is connected with the source electrode of the PMOS tube M36, the grid electrode of the PMOS tube PM41 is connected with the input end of the reference current IREF2, and the source electrode of the PMOS tube PM41 is connected with the drain electrode of the PMOS tube PM 42; the source of the PMOS tube PM42 and the source of the PMOS tube PM43 are connected with a power supply VDD, the grid of the PMOS tube PM42 is connected with the drain of the PMOS tube PM43 and one end of a switch S3, the other end of the switch S3 is connected with the drain of a PMOS tube M26, and the grid of the PMOS tube PM43 is connected with a control signal S <3> of the switch S3;
The drain electrode of the PMOS tube PM51 is connected with the source electrode of the PMOS tube M36, the grid electrode of the PMOS tube PM51 is connected with the input end of the reference current IREF2, and the source electrode of the PMOS tube PM51 is connected with the drain electrode of the PMOS tube PM 52; the source of the PMOS tube PM52 and the source of the PMOS tube PM53 are connected with a power supply VDD, the grid of the PMOS tube PM52 is connected with the drain of the PMOS tube PM53 and one end of a switch S4, the other end of the switch S4 is connected with the drain of a PMOS tube M26, and the grid of the PMOS tube PM53 is connected with a control signal S <4> of the switch S4;
The drain electrode of the PMOS tube PM61 is connected with the source electrode of the PMOS tube M36, the grid electrode of the PMOS tube PM61 is connected with the input end of the reference current IREF2, and the source electrode of the PMOS tube PM61 is connected with the drain electrode of the PMOS tube PM 62; the source of the PMOS tube PM62 and the source of the PMOS tube PM63 are connected with a power supply VDD, the grid of the PMOS tube PM62 is connected with the drain of the PMOS tube PM63 and one end of a switch S5, the other end of the switch S5 is connected with the drain of a PMOS tube M26, and the grid of the PMOS tube PM63 is connected with a control signal S <5> of the switch S5;
the drain electrode of the PMOS tube PM71 is connected with the source electrode of the PMOS tube M36, the grid electrode of the PMOS tube PM71 is connected with the input end of the reference current IREF2, and the source electrode of the PMOS tube PM71 is connected with the drain electrode of the PMOS tube PM 72; the source of the PMOS tube PM72 and the source of the PMOS tube PM73 are connected with a power supply VDD, the grid of the PMOS tube PM72 is connected with the drain of the PMOS tube PM73 and one end of a switch S6, the other end of the switch S6 is connected with the drain of the PMOS tube M26, and the grid of the PMOS tube PM73 is connected with a control signal S <6> of the switch S6.
The switches S0-S6 are connected with corresponding control signals S <0> -S <6>, the control signals S <0> -S <6> control the interruption of the switches S1-S6 according to the digital codes S <6:0> with smaller weight so as to control the magnitude of the output current of the programmable current source, when S <6:0> = 1111111, the switches S0-S6 are all closed, the current output by the small step current part of the programmable current source is the maximum current, and when S <6:0> = 0000000, the switches S0-S6 are all opened, and the current output by the small step current part of the programmable current source is the minimum current.
In a specific embodiment, the drain electrode of the PMOS transistor M27 is connected to the source electrode of the PMOS transistor M36, the gate electrode of the PMOS transistor M27 is connected to the input end of the reference current IREF2, and the source electrode of the PMOS transistor M27 is connected to the drain electrode of the PMOS transistor M28; the source electrode of the PMOS tube M28 and the source electrode of the PMOS tube M29 are connected with a power supply VDD, the grid electrode of the PMOS tube M28 is connected with the drain electrode of the PMOS tube M29 and one end of a switch L0, the other end of the switch L0 is connected with the drain electrode of the PMOS tube M26, and the grid electrode of the PMOS tube M29 is connected with a control signal L <0> of the switch L0;
The drain electrode of the PMOS tube M30 is connected with the source electrode of the PMOS tube M36, the grid electrode of the PMOS tube M30 is connected with the input end of the reference current IREF2, and the source electrode of the PMOS tube M30 is connected with the drain electrode of the PMOS tube M31; the source electrode of the PMOS tube M31 and the source electrode of the PMOS tube M32 are connected with a power supply VDD, the grid electrode of the PMOS tube M31 is connected with the drain electrode of the PMOS tube M32 and one end of a switch L1, the other end of the switch L1 is connected with the drain electrode of the PMOS tube M26, and the grid electrode of the PMOS tube M32 is connected with a control signal L <1> of the switch L1;
The drain electrode of the PMOS tube M33 is connected with the source electrode of the PMOS tube M36, the grid electrode of the PMOS tube M33 is connected with the input end of the reference current IREF2, and the source electrode of the PMOS tube M233 is connected with the drain electrode of the PMOS tube M34; the source of the PMOS tube M34 and the source of the PMOS tube M35 are connected with a power supply VDD, the grid of the PMOS tube M34 is connected with the drain of the PMOS tube M35 and one end of a switch L2, the other end of the switch L2 is connected with the drain of the PMOS tube M26, and the grid of the PMOS tube M35 is connected with a control signal L <2> of the switch L2.
The switches L0-L2 are all connected with control signals L <0> -L <2>, the control signals L <0> -L <2> control the interruption of the switches L0-L2 according to the digital codes L <2:0> with larger weight, when the digital codes L <2:0> =111, the switches L0-L2 are all closed, the current output by the large-step current part of the programmable current source is the maximum current, and when the digital codes L <2:0> =000, the switches L0-L2 are all opened, and the current output by the large-step current part of the programmable current source is the minimum current.
The invention also provides a calibration method of the MIPI high-speed channel circuit with offset self-calibration, which is applied to the MIPI high-speed channel circuit with offset self-calibration and comprises the following steps:
S1, inputting a transmission signal, and transmitting the transmission signal to a hysteresis comparator after being amplified by a pre-amplifier;
s2, comparing the signals amplified by the pre-amplifier by the hysteresis comparator, outputting the normal signals into corresponding single-ended signals of transmission data during normal operation, and inputting signals only containing offset voltage to the calibration switch during offset calibration;
the normal signal is a signal with offset voltage calibration completed, and the signal can be directly used for data transmission.
S3, the OFFSET calibration algorithm module sends a calibration end signal OFFSET_EN to control the conduction of a calibration switch, a signal containing OFFSET voltage is transmitted to a calibration comparator, the calibration comparator carries out polarity judgment on an input signal and then converts a comparison result into a digital code COMP (1) to be output to the OFFSET calibration algorithm module;
S4, outputting a corresponding selection signal SEL <1:0> and two digital codes S <6:0> and L <2:0> with two weights to a programmable current source by a maladjustment calibration algorithm module according to the magnitude of maladjustment voltage, and outputting corresponding current to the output end of a preamplification stage of the preamplifier by the programmable current source until obtaining a final proper compensation current I_CAL;
S5, outputting a calibration ending signal OFFSET_EN with the value of 0 to a calibration switch by the OFFSET calibration algorithm module, closing the calibration switch and the calibration comparator, and ending the calibration.
As shown in fig. 4, in a specific embodiment, the offset calibration algorithm module in step S4 outputs corresponding selection signals SEL <1:0> and two digital codes S <6:0>, L <2:0> with two weights according to the magnitude of the offset voltage to a programmable current source, and the programmable current source outputs corresponding currents to the output end of the pre-amplification stage of the pre-amplifier, which comprises the following steps:
a1, the offset calibration algorithm module generates a digital code S <6:0> =1111111, L <2:0> =111, controls the output of the programmable current source to reach the maximum current I_MAX, and the selection signal SEL <1:0> =01 controls the programmable current source to output a negative phase calibration current IOUTN to the negative output terminal O1N of the pre-amplification stage of the pre-amplifier, wherein the digital code COMP=0;
a2, the offset calibration algorithm module reduces the digital code L <2:0> with larger weight, controls the negative phase calibration current IOUTN of the programmable current source to be rapidly reduced to be close to the proper compensation current I_CAL with larger step current, judges whether the value of COMP is 1 at the moment, and increases the digital code L <2:0> with larger weight until the value of COMP is 0 if the value of COMP is 1; if COMP is not 1, the weighted digital code L <2:0> =000;
A3, the offset calibration algorithm module reduces the digital code S <6:0> with smaller weight, controls the negative phase calibration current IOUTN of the programmable current source to be finely adjusted with smaller step current, judges whether the value of COMP is 1 at the moment, and obtains the final proper compensation current I_CAL if the value of COMP is 1, and stops calibration; if not 1, the digital code with smaller weight S <6:0> =0000000;
A4, the output selection signal SEL <1:0> = 10 controls the programmable current source to output the normal phase calibration current IOUTP to the output positive end O1P of the pre-amplifying stage of the pre-amplifier, and at the moment, the digital code S <6:0> = 0000000, L <2:0> = 000 controls the output of the programmable current source to reach the minimum current I_MIN;
A5, the offset calibration algorithm module increases the digital code L <2:0> with larger weight, controls the normal phase calibration current IOUTP of the programmable current source to increase with larger step current until the current approaches to the proper compensation current I_CAL, judges whether the value of COMP is 1 at the moment, and increases the digital code L <2:0> with larger weight until the value of COMP is 0 if the value of COMP is 1; if not, the digital code L <2:0> =111 with larger weight is given;
A6, the offset calibration algorithm module increases the digital code S <6:0> with smaller weight, controls the normal phase calibration current IOUTP of the programmable current source to be finely adjusted with smaller step current, judges whether the value of COMP is 1 at the moment, and obtains the final proper compensation current I_CAL if the value of COMP is 1, and stops calibration; if not 1, the digital code S <6:0> =1111111 with smaller weight is made to proceed with the calibration in step A1.
As shown in fig. 5, firstly, the offset calibration algorithm module generates a digital code S <6:0> =1111111, L <2:0> =111 so that the output of the programmable current source reaches the maximum current i_max, the selection signal SEL <1:0> =01 controls the programmable current source to output a negative phase calibration current IOUTN to be injected into the negative output terminal O1N of the pre-amplification stage of the pre-amplifier, and a larger error is artificially injected into the terminal O1N based on the original smaller offset error, so comp=0, then the calibration algorithm reduces the digital code L <2:0> with larger weight so that the negative phase calibration current IOUTN of the programmable current source is rapidly reduced with larger step size to approach the appropriate compensation current value i_cal, and then the calibration algorithm reduces the digital code S <6:0> with smaller weight so that the negative phase calibration current IOUTN is finely adjusted with smaller step size to obtain the final appropriate compensation current i_cal, comp=1.
When the injected negative calibration current IOUTN is reduced at the output negative terminal O1N of the pre-amplifier stage and COMP is always not 1, the change selection signal SEL <1:0> =10 controls the injection of the positive calibration current IOUTP to the pre-amplifier stage output positive terminal O1P of the pre-amplifier, where S <6:0> =0000000, L <2:0> =000, and the injection current IOUTP is the smallest, i_min. Then the calibration algorithm increases the digital code L <2:0> with larger weight to enable the normal phase calibration current IOUTP of the programmable current source to be rapidly increased to approach the proper compensation current value I_CAL with larger step length, and then the calibration algorithm increases the digital code S <6:0> with smaller weight to enable the normal phase calibration current IOUTP to be finely adjusted with smaller step length to obtain the final proper compensation current I_CAL.
The foregoing is only a preferred embodiment of the invention, it being noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the invention.

Claims (6)

1. An MIPI high-speed channel circuit with offset self-calibration, comprising:
The pre-amplifier comprises an output signal positive end O2P and an output signal negative end O2N, and is used for amplifying an input signal;
The hysteresis comparator comprises a positive input end and a negative input end, wherein the positive input end is connected with an output signal positive end O2P of the pre-amplifier, and the negative input end is connected with an output signal negative end O2N of the pre-amplifier and is used for comparing signals amplified by the pre-amplifier and outputting a single-ended signal OUT and an intermediate signal O3N, O P;
The calibration switch is respectively connected with the hysteresis comparator and the calibration comparator and is used for controlling the input end of the calibration comparator;
The calibration comparator comprises a positive phase input end and a negative phase input end, wherein the positive phase input end receives an intermediate signal O3P, the negative phase input end receives an intermediate signal O3N, and is used for judging the polarities of the intermediate signals O3P and O3N output by the hysteresis comparator and converting a comparison result into a 1-bit digital code COMP and outputting the 1-bit digital code COMP to the offset calibration algorithm module;
the OFFSET calibration algorithm module is used for calculating a comparison result of the calibration comparator, generating two digital codes S <6:0>, L <2:0> and a selection signal SEL <1:0> with weights to control the current output of the programmable current source, and generating a calibration end signal OFFSET_EN to control the on-off of the calibration switch;
the programmable current source is used for outputting a calibration current to the output end of the pre-amplification stage of the pre-amplifier and compensating offset voltage;
The output end of the pre-amplification stage comprises an output positive end O1P and an output negative end O1N, the programmable current source comprises a negative phase calibration current source IOUTN circuit and a positive phase calibration current source IOUTP circuit, the negative phase calibration current source IOUTN circuit and the positive phase calibration current source IOUTP circuit both comprise a current with a larger step length and a current with a smaller step length, the current with the larger step length means that the current value is greatly changed compared with the previous current value, the current with the smaller step length means that the current value is greatly changed compared with the previous current value, the current with the larger step length and the current with the smaller step length correspond to digital codes L <2:0> and digital codes S <6:0>, when a selection signal SEL <1:0> is 01, the negative phase calibration current source IOUTN circuit outputs a negative phase calibration current IOUTN to the output negative end O1N of the pre-amplification stage, and when the selection signal SEL <1:0> is 10, the positive phase calibration current source IOUTP outputs a positive phase calibration current IOUTP to the output positive end O1P of the pre-amplification stage.
2. The MIPI high-speed channel circuit with offset self-calibration as claimed in claim 1, wherein said calibration comparator comprises a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, a PMOS tube M4, a PMOS tube M9, a PMOS tube M10, a PMOS tube M11, a PMOS tube M12, a PMOS tube M14, a PMOS tube M15, a PMOS tube M17, a PMOS tube M18, a PMOS tube M20 and a PMOS tube M21, an NMOS tube M5, an NMOS tube M6, an NMOS tube M7, an NMOS tube M8, an NMOS tube M13, a PMOS tube M13, The device comprises an NMOS tube M16, an NMOS tube M19, an inverter I1, an inverter I2, an inverter I3, a resistor R1 and a resistor R2, wherein the grid electrode of the PMOS tube M1 is connected with an input signal VINP, the drain electrode of the PMOS tube M1 is connected with the drain electrode of an NMOS tube M5 and the source electrode of an NMOS tube M7, and the source electrode of the PMOS tube M1 is connected with one end of the resistor R1 and the drain electrode of the PMOS tube M3; the other end of the resistor R1 is connected with the source electrode of the PMOS tube M3, one end of the resistor R2 and the output end of the reference current IREF, and the input end of the reference current IREF is connected with the power supply VDD, the source electrode of the PMOS tube M11, the source electrode of the PMOS tube M12, the source electrode of the PMOS tube M15, the source electrode of the PMOS tube M18 and the source electrode of the PMOS tube M21; the grid electrode of the PMOS tube M2 is connected with an input signal VINN, the drain electrode of the PMOS tube M2 is connected with the drain electrode of the NMOS tube M6 and the source electrode of the NMOS tube M8, and the source electrode of the PMOS tube M2 is connected with one end of the resistor R2 and the drain electrode of the PMOS tube M4; the grid electrode of the PMOS tube M3 is connected with a power supply VDD, and the grid electrode of the PMOS tube M4 is connected with the output end OUTN of the inverter I2; the grid electrode of the NMOS tube M5 and the grid electrode of the NMOS tube M6 are connected with a reference voltage VB1, and the source electrode of the NMOS tube M5 and the source electrode of the NMOS tube M6 are connected with the ground GND; the grid electrode of the NMOS tube M7 and the grid electrode of the NMOS tube M8 are connected with a reference voltage VB2, and the drain electrode of the NMOS tube M7 is connected with the drain electrode of the PMOS tube M9, the grid electrode of the PMOS tube M11 and the grid electrode of the PMOS tube M12; the drain electrode of the NMOS tube M8 is connected with the drain electrode of the PMOS tube M10 and the grid electrode of the NMOS tube M13; the grid electrode of the PMOS tube M9 and the grid electrode of the PMOS tube M10 are connected with a reference voltage VB3, and the source electrode of the PMOS tube M9 is connected with the drain electrode of the PMOS tube M11; the source electrode of the PMOS tube M10 is connected with the drain electrode of the PMOS tube M12; the source electrode of the NMOS tube M13, the source electrode of the NMOS tube M16 and the source electrode of the NMOS tube M19 are connected with the ground GND, and the drain electrode of the NMOS tube M13 is connected with the drain electrode of the PMOS tube M14 and the grid electrode of the NMOS tube M16; the grid electrode of the PMOS tube M14, the grid electrode of the PMOS tube M17 and the grid electrode of the PMOS tube M20 are connected with the reference voltage VB3, and the source electrode of the PMOS tube M14 is connected with the drain electrode of the PMOS tube M15; the grid electrode of the PMOS tube M15, the grid electrode of the PMOS tube M18 and the grid electrode of the PMOS tube M21 are connected with a reference voltage VB 4; the drain electrode of the NMOS tube M16 is connected with the drain electrode of the PMOS tube M17 and the grid electrode of the NMOS tube M19, and the source electrode of the PMOS tube M17 is connected with the drain electrode of the PMOS tube M18; the drain electrode of the NMOS tube M19 is connected with the drain electrode of the PMOS tube M20 and the input end of the inverter I1, and the source electrode of the PMOS tube M20 is connected with the drain electrode of the PMOS tube M21; the output end of the inverter I1 is connected to the input end of the inverter I2, and the output end OUTN of the inverter I2 is connected with the input end of the inverter I3; the output of the inverter I3 outputs a 1-bit digital code COMP.
3. The MIPI high-speed channel circuit with offset self-calibration according to claim 1, wherein the positive calibration current source IOUTP circuit of the programmable current source comprises PMOS transistor M22, PMOS transistor M23, PMOS transistor M24, PMOS transistor M25, PMOS transistor M26, PMOS transistor M36, NMOS transistor M37, first step-size low current circuit, second step-size low current circuit, third step-size low current circuit, fourth step-size low current circuit, fifth step-size low current circuit, sixth step-size low current circuit, seventh step-size low current circuit, first step-size high current circuit, second step-size high current circuit and third step-size high current circuit, the source of PMOS transistor M22, the source of PMOS transistor M24, the source of PMOS transistor M26 are connected to power supply VDD, the drain of PMOS transistor M22 is connected to the source of PMOS transistor M23, and the gate of PMOS transistor M22 is connected to the gate of PMOS transistor M23, the drain of PMOS transistor M23, the gate of PMOS transistor M25 and the input terminal of reference current IREF 2; the output end of the reference current IREF2 and the output end of the reference current IREF1 are connected with the ground GND; the source electrode of the PMOS tube M25 is connected with the drain electrode of the PMOS tube M24, and the drain electrode of the PMOS tube M25 is connected with the input end of the reference current IREF1 and the grid electrode of the PMOS tube M24; the grid electrode of the PMOS tube M26 is connected with an enable signal EN, and the drain electrode of the PMOS tube M26 is connected with the grid electrode of the PMOS tube M24 and the input end of the reference current IREF 1; the first step-size small current circuit, the second step-size small current circuit, the third step-size small current circuit, the fourth step-size small current circuit, the fifth step-size small current circuit, the sixth step-size small current circuit, the seventh step-size small current circuit, the first step-size large current circuit, the second step-size large current circuit and the third step-size large current circuit are all connected with a power supply VDD, a drain electrode of a PMOS tube M26, a reference current IREF2, a source electrode of a PMOS tube M36 and a drain electrode of an NMOS tube M37; the drain electrode of the NMOS tube M37 is connected with the source electrode of the PMOS tube M36, the source electrode of the NMOS tube M37 is connected with the ground GND, the grid electrode of the NMOS tube M37 and the grid electrode of the PMOS tube M36 are commonly connected to a selection signal SEL <1:0>, and the drain electrode output of the PMOS tube M36 is the normal phase output current IOUTP of a programmable current source.
4. The MIPI high-speed channel circuit with offset self-calibration according to claim 3, wherein the first step-size low-current circuit comprises switch S0, PMOS transistor PM11, PMOS transistor PM12 and PMOS transistor PM13, the second step-size low-current circuit comprises switch S1, PMOS transistor PM21, PMOS transistor PM22 and PMOS transistor PM23, the third step-size low-current circuit comprises switch S2, PMOS transistor PM31, PMOS transistor PM32 and PMOS transistor PM33, the fourth step-size low-current circuit comprises switch S3, PMOS transistor PM41, PMOS transistor PM42 and PMOS transistor PM43, the fifth step-size low-current circuit comprises switch S4, PMOS transistor PM51, PMOS transistor PM52 and PMOS transistor PM53, the sixth step-size low-current circuit comprises switch S5, PMOS transistor PM61, PMOS transistor PM62 and PMOS transistor PM63, the seventh step-size low-current circuit comprises switch S6, PMOS transistor PM71, PMOS transistor PM72 and PMOS transistor PM73, the first step-size high-current circuit comprises switch S0, PMOS transistor M27 and PMOS transistor M33, and PMOS transistor M32, and the third step-size high-current circuit comprises switch M3, PMOS transistor M30 and PMOS transistor M31;
The drain electrode of the PMOS tube PM11 is connected with the source electrode of the PMOS tube M36, the grid electrode of the PMOS tube PM11 is connected with the input end of the reference current IREF2, and the source electrode of the PMOS tube PM11 is connected with the drain electrode of the PMOS tube PM 12; the source of the PMOS tube PM12 and the source of the PMOS tube PM13 are connected with a power supply VDD, the grid of the PMOS tube PM12 is connected with the drain of the PMOS tube PM13 and one end of a switch S0, the other end of the switch S0 is connected with the drain of a PMOS tube M26, and the grid of the PMOS tube PM13 is connected with a control signal S <0> of the switch S0;
The drain electrode of the PMOS tube PM21 is connected with the source electrode of the PMOS tube M36, the grid electrode of the PMOS tube PM21 is connected with the input end of the reference current IREF2, and the source electrode of the PMOS tube PM21 is connected with the drain electrode of the PMOS tube PM 22; the source of the PMOS tube PM22 and the source of the PMOS tube PM23 are connected with a power supply VDD, the grid of the PMOS tube PM22 is connected with the drain of the PMOS tube PM23 and one end of a switch S1, the other end of the switch S1 is connected with the drain of a PMOS tube M26, and the grid of the PMOS tube PM23 is connected with a control signal S <1> of the switch S1;
the drain electrode of the PMOS tube PM31 is connected with the source electrode of the PMOS tube M36, the grid electrode of the PMOS tube PM31 is connected with the input end of the reference current IREF2, and the source electrode of the PMOS tube PM31 is connected with the drain electrode of the PMOS tube PM 32; the source of the PMOS tube PM32 and the source of the PMOS tube PM33 are connected with a power supply VDD, the grid of the PMOS tube PM32 is connected with the drain of the PMOS tube PM33 and one end of a switch S2, the other end of the switch S2 is connected with the drain of a PMOS tube M26, and the grid of the PMOS tube PM33 is connected with a control signal S <2> of the switch S2;
The drain electrode of the PMOS tube PM41 is connected with the source electrode of the PMOS tube M36, the grid electrode of the PMOS tube PM41 is connected with the input end of the reference current IREF2, and the source electrode of the PMOS tube PM41 is connected with the drain electrode of the PMOS tube PM 42; the source of the PMOS tube PM42 and the source of the PMOS tube PM43 are connected with a power supply VDD, the grid of the PMOS tube PM42 is connected with the drain of the PMOS tube PM43 and one end of a switch S3, the other end of the switch S3 is connected with the drain of a PMOS tube M26, and the grid of the PMOS tube PM43 is connected with a control signal S <3> of the switch S3;
The drain electrode of the PMOS tube PM51 is connected with the source electrode of the PMOS tube M36, the grid electrode of the PMOS tube PM51 is connected with the input end of the reference current IREF2, and the source electrode of the PMOS tube PM51 is connected with the drain electrode of the PMOS tube PM 52; the source of the PMOS tube PM52 and the source of the PMOS tube PM53 are connected with a power supply VDD, the grid of the PMOS tube PM52 is connected with the drain of the PMOS tube PM53 and one end of a switch S4, the other end of the switch S4 is connected with the drain of a PMOS tube M26, and the grid of the PMOS tube PM53 is connected with a control signal S <4> of the switch S4;
The drain electrode of the PMOS tube PM61 is connected with the source electrode of the PMOS tube M36, the grid electrode of the PMOS tube PM61 is connected with the input end of the reference current IREF2, and the source electrode of the PMOS tube PM61 is connected with the drain electrode of the PMOS tube PM 62; the source of the PMOS tube PM62 and the source of the PMOS tube PM63 are connected with a power supply VDD, the grid of the PMOS tube PM62 is connected with the drain of the PMOS tube PM63 and one end of a switch S5, the other end of the switch S5 is connected with the drain of a PMOS tube M26, and the grid of the PMOS tube PM63 is connected with a control signal S <5> of the switch S5;
The drain electrode of the PMOS tube PM71 is connected with the source electrode of the PMOS tube M36, the grid electrode of the PMOS tube PM71 is connected with the input end of the reference current IREF2, and the source electrode of the PMOS tube PM71 is connected with the drain electrode of the PMOS tube PM 72; the source of the PMOS tube PM72 and the source of the PMOS tube PM73 are connected with a power supply VDD, the grid of the PMOS tube PM72 is connected with the drain of the PMOS tube PM73 and one end of a switch S6, the other end of the switch S6 is connected with the drain of the PMOS tube M26, and the grid of the PMOS tube PM73 is connected with a control signal S <6> of the switch S6;
The drain electrode of the PMOS tube M27 is connected with the source electrode of the PMOS tube M36, the grid electrode of the PMOS tube M27 is connected with the input end of the reference current IREF2, and the source electrode of the PMOS tube M27 is connected with the drain electrode of the PMOS tube M28; the source electrode of the PMOS tube M28 and the source electrode of the PMOS tube M29 are connected with a power supply VDD, the grid electrode of the PMOS tube M28 is connected with the drain electrode of the PMOS tube M29 and one end of a switch L0, the other end of the switch L0 is connected with the drain electrode of the PMOS tube M26, and the grid electrode of the PMOS tube M29 is connected with a control signal L <0> of the switch L0;
The drain electrode of the PMOS tube M30 is connected with the source electrode of the PMOS tube M36, the grid electrode of the PMOS tube M30 is connected with the input end of the reference current IREF2, and the source electrode of the PMOS tube M30 is connected with the drain electrode of the PMOS tube M31; the source electrode of the PMOS tube M31 and the source electrode of the PMOS tube M32 are connected with a power supply VDD, the grid electrode of the PMOS tube M31 is connected with the drain electrode of the PMOS tube M32 and one end of a switch L1, the other end of the switch L1 is connected with the drain electrode of the PMOS tube M26, and the grid electrode of the PMOS tube M32 is connected with a control signal L <1> of the switch L1;
The drain electrode of the PMOS tube M33 is connected with the source electrode of the PMOS tube M36, the grid electrode of the PMOS tube M33 is connected with the input end of the reference current IREF2, and the source electrode of the PMOS tube M233 is connected with the drain electrode of the PMOS tube M34; the source of the PMOS tube M34 and the source of the PMOS tube M35 are connected with a power supply VDD, the grid of the PMOS tube M34 is connected with the drain of the PMOS tube M35 and one end of a switch L2, the other end of the switch L2 is connected with the drain of the PMOS tube M26, and the grid of the PMOS tube M35 is connected with a control signal L <2> of the switch L2.
5. A calibration method of an MIPI high-speed channel circuit with offset self-calibration, applied to any one of claims 1-4, characterized by comprising the steps of:
S1, inputting a transmission signal, and transmitting the transmission signal to a hysteresis comparator after being amplified by a pre-amplifier;
S2, comparing the signals amplified by the pre-amplifier by the hysteresis comparator, outputting a normal transmission signal into a corresponding single-ended signal during normal operation, and inputting a signal only containing offset voltage to the calibration switch during offset calibration;
S3, the OFFSET calibration algorithm module sends a calibration end signal OFFSET_EN to control the conduction of a calibration switch, a signal containing OFFSET voltage is transmitted to a calibration comparator, the calibration comparator carries out polarity judgment on an input signal containing OFFSET voltage, then the comparison result is converted into a digital code COMP (1), and the digital code COMP is output to the OFFSET calibration algorithm module;
s4, outputting a corresponding selection signal SEL <1:0> and two digital codes S <6:0> and L <2:0> with weights to a programmable current source by a maladjustment calibration algorithm module according to the size of maladjustment voltage, and outputting corresponding current to the output end of a preamplification stage of the preamplifier by the programmable current source until obtaining a final proper compensation current I_CAL;
S5, outputting a calibration ending signal OFFSET_EN with the value of 0 to a calibration switch by the OFFSET calibration algorithm module, closing the calibration switch and the calibration comparator, and ending the calibration.
6. The method according to claim 5, wherein the step S4 of the offset calibration algorithm module outputs corresponding selection signals SEL <1:0> and two digital codes S <6:0>, L <2:0> with two weights to a programmable current source according to the magnitude of the offset voltage, and the programmable current source outputs corresponding currents to the output end of the pre-amplification stage of the pre-amplifier comprises the following steps:
A1, the offset calibration algorithm module generates a digital code S <6:0> =1111111, L <2:0> =111, controls the output of the programmable current source to reach the maximum current I_MAX, selects the signal SEL <1:0> =01, controls the programmable current source to output a negative phase calibration current IOUTN to the negative output terminal O1N of the pre-amplification stage of the pre-amplifier, and the digital code COMP=0 at the moment;
a2, the offset calibration algorithm module reduces the digital code L <2:0> with larger weight, controls the negative phase calibration current IOUTN of the programmable current source to be rapidly reduced to be close to the proper compensation current I_CAL with larger step current, judges whether the value of COMP is 1 at the moment, and increases the digital code L <2:0> with larger weight until the value of COMP is 0 if the value of COMP is 1; if COMP is not 1, the weighted digital code L <2:0> =000;
A3, the offset calibration algorithm module reduces the digital code S <6:0> with smaller weight, controls the negative phase calibration current IOUTN of the programmable current source to be finely adjusted with smaller step current, judges whether the value of COMP is 1 at the moment, and obtains the final proper compensation current I_CAL if the value of COMP is 1, and stops calibration; if not 1, the digital code with smaller weight S <6:0> =0000000;
A4, let the selection signal SEL <1:0> =10, control the programmable current source to output the normal calibration current IOUTP to the pre-amplification stage output positive end O1P of the pre-amplifier, at this time, the digital code S <6:0> =0000000, L <2:0> =000, control the output of the programmable current source to reach the minimum current I_MIN;
A5, the offset calibration algorithm module increases the digital code L <2:0> with larger weight, controls the normal phase calibration current IOUTP of the programmable current source to increase with larger step current until the current approaches to the proper compensation current I_CAL, judges whether the value of COMP is 1 at the moment, and increases the digital code L <2:0> with larger weight until the value of COMP is 0 if the value of COMP is 1; if not, the digital code L <2:0> =111 with larger weight is given;
A6, the offset calibration algorithm module increases the digital code S <6:0> with smaller weight, controls the normal phase calibration current IOUTP of the programmable current source to be finely adjusted with smaller step current, judges whether the value of COMP is 1 at the moment, and obtains the final proper compensation current I_CAL if the value of COMP is 1, and stops calibration; if not 1, the digital code S <6:0> =1111111 with smaller weight is made to proceed with the calibration in step A1.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2547289A1 (en) * 1974-10-22 1976-04-29 Lgt Lab Gen Telecomm ARRANGEMENT FOR EQUALIZATION OF DIFFERENTIAL PHASE ERRORS
CN101079645A (en) * 2006-05-25 2007-11-28 北京六合万通微电子技术有限公司 Device for eliminating local vibration leakage in the wireless communication transmitter
CN101162910A (en) * 2006-10-10 2008-04-16 北京六合万通微电子技术有限公司 Local oscillator leakage automatic eliminator
CN104283558A (en) * 2013-07-08 2015-01-14 清华大学 High-speed comparator direct-current offset digital auxiliary self-calibration system and control method
CN106571787A (en) * 2016-11-13 2017-04-19 天津大学 Digital-analog hybrid automatic gain control amplifier
WO2023168971A1 (en) * 2022-03-11 2023-09-14 华南理工大学 Calibration and tuning method for on-chip differential active rc filter

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI485974B (en) * 2013-11-29 2015-05-21 Amtek Semiconductor Co Ltd Auto calibration driver ic and itsapplication motor driver system

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2547289A1 (en) * 1974-10-22 1976-04-29 Lgt Lab Gen Telecomm ARRANGEMENT FOR EQUALIZATION OF DIFFERENTIAL PHASE ERRORS
CN101079645A (en) * 2006-05-25 2007-11-28 北京六合万通微电子技术有限公司 Device for eliminating local vibration leakage in the wireless communication transmitter
CN101162910A (en) * 2006-10-10 2008-04-16 北京六合万通微电子技术有限公司 Local oscillator leakage automatic eliminator
CN104283558A (en) * 2013-07-08 2015-01-14 清华大学 High-speed comparator direct-current offset digital auxiliary self-calibration system and control method
CN106571787A (en) * 2016-11-13 2017-04-19 天津大学 Digital-analog hybrid automatic gain control amplifier
WO2023168971A1 (en) * 2022-03-11 2023-09-14 华南理工大学 Calibration and tuning method for on-chip differential active rc filter

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