CN113746491B - Blocking capacitor compensation system suitable for zero intermediate frequency receiver - Google Patents
Blocking capacitor compensation system suitable for zero intermediate frequency receiver Download PDFInfo
- Publication number
- CN113746491B CN113746491B CN202110810909.3A CN202110810909A CN113746491B CN 113746491 B CN113746491 B CN 113746491B CN 202110810909 A CN202110810909 A CN 202110810909A CN 113746491 B CN113746491 B CN 113746491B
- Authority
- CN
- China
- Prior art keywords
- effect transistor
- field effect
- electrode
- field
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
Abstract
The invention discloses a blocking capacitor compensation system suitable for a zero intermediate frequency receiver, which comprises a first chopping operational amplifier module, a second chopping operational amplifier module, an operational amplifier and a switched capacitor integrator. The invention carries out chopping and amplification on the signal twice through the first chopping operational amplifier module and the second chopping operational amplifier module, and can chop the offset voltage and the flicker noise of the operational amplifier once, so that the signal is separated from the direct current offset and the flicker noise of the operational amplifier, the offset and the noise are filtered, and the original signal is not influenced; meanwhile, low-pass filtering with the bandwidth of only 10Hz is realized through the switched capacitor integrator, and the control of a direct current signal is realized through the negative feedback of the switched capacitor integrator, so that the compensation effect on a large capacitor is obtained. Therefore, the system only increases a small amount of power consumption and area to achieve the effect of increasing a large blocking capacitor outside the chip, and can realize the full integration of the zero intermediate frequency receiver.
Description
Technical Field
The invention relates to the field of circuit signal processing, in particular to a blocking capacitor compensation system suitable for a zero intermediate frequency receiver.
Background
In the zero intermediate frequency receiving link, because the isolation from the local oscillator end to the radio frequency end is not enough, the frequency mixer feeds through the local oscillator signal to the radio frequency end and then carries out frequency mixing with the local oscillator to generate a direct current level (in the zero intermediate frequency receiver, the receiving and transmitting isolation is not enough, the transmitting signal enters the receiving link and is mixed with the local oscillator signal to generate direct current). After a large direct current signal is amplified by the intermediate frequency amplifier, the output of the amplifier is saturated, so that the amplifier cannot work. The traditional technology for eliminating the direct current component of the mixer is to use a passive device for filtering, for example, a high-pass filter is formed by using a large capacitor and the input impedance of an intermediate frequency amplifying part, so as to filter the direct current component, when the frequency of an output intermediate frequency signal is higher, the area can be sacrificed, and the on-chip capacitor is used for realizing full integration. However, for the zero intermediate frequency architecture, when the output intermediate frequency is less than 500Hz, the very low cut-off frequency of the filter can cause the layout area of the passive device to be too large, the integration is difficult, the off-chip capacitor needs to be used for realizing the blocking effect, and the cost can be greatly increased when the zero intermediate frequency architecture is produced in batch.
Disclosure of Invention
Aiming at the defects in the prior art, the blocking capacitor compensation system suitable for the zero intermediate frequency receiver solves the problem that the zero intermediate frequency receiver is difficult to integrate and filter a passive device of a direct current component.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that:
the blocking capacitor compensation system comprises a first chopping operational amplifier module, a second chopping operational amplifier module, an operational amplifier and a switched capacitor integrator; the two output ends of the first chopping operational amplifier module are respectively connected with the two input ends of the second chopping operational amplifier module, the two output ends of the second chopping operational amplifier module are respectively connected with the two input ends of the switched capacitor integrator and the operational amplifier, the two output ends of the operational amplifier are output ends of the blocking capacitance compensation system, and the two output ends of the switched capacitor integrator and an external differential signal are superposed to jointly serve as two input signals of the first chopping operational amplifier module.
Furthermore, the switched capacitor integrator comprises a differential equivalent resistor and a third chopping operational amplifier module which are connected with each other, the input end of the differential equivalent resistor is the input end of the switched capacitor integrator, and the output end of the third chopping operational amplifier module is the output end of the switched capacitor integrator.
Further, the differential equivalent resistor comprises a switch S1 and a switch S2, one end of the switch S1 and one end of the switch S2 are both input ends of the differential equivalent resistor, and the other end of the switch S1 is connected to one end of the capacitor C3 and one end of the switch S3 respectively; the other end of the capacitor C3 is connected with one end of the switch S5 and one end of the switch S7 respectively;
the other end of the switch S2 is connected with one end of the capacitor C4 and one end of the switch S4 respectively; the other end of the capacitor C4 is connected with one end of the switch S6 and one end of the switch S8 respectively; the other end of the switch S3, the other end of the switch S4, the other end of the switch S5 and the other end of the switch S6 are all grounded; the other end of the switch S7 and the other end of the switch S8 are the output ends of the differential equivalent resistor; the switch S1, the switch S2, the switch S5 and the switch S6 are opened and closed simultaneously; the switch S3, the switch S4, the switch S7, and the switch S8 are opened and closed.
Furthermore, the chopping operational amplifier module comprises a chopping amplifying circuit, and a bias circuit and a common mode feedback circuit which are respectively connected with the chopping amplifying circuit; the output end of the common mode feedback circuit is the output end of the chopping operational amplifier module;
the chopping amplification circuit comprises a chopper CH1 and a chopper CH2, the input end of the chopper CH1 is the input end of the chopping operational amplification module, and the output end of the chopper CH1 is respectively connected with the grid of the field-effect tube M26 and the grid of the field-effect tube M27; the source electrode of the field effect transistor M26 is respectively connected with the source electrode of the field effect transistor M27 and the drain electrode of the field effect transistor M33; the drain electrode of the field effect transistor M26 is respectively connected with the source electrode of the field effect transistor M20 and the drain electrode of the field effect transistor M18; the drain electrode of the field effect transistor M27 is respectively connected with the source electrode of the field effect transistor M21 and the drain electrode of the field effect transistor M19;
the source electrode of the field-effect tube M33 is connected with an external power supply, and the grid electrode of the field-effect tube M33 is respectively connected with the grid electrode of the field-effect tube M24, the grid electrode of the field-effect tube M25, the grid electrode of the field-effect tube M32, the grid electrode of the field-effect tube M17 and the first bias end of the bias circuit; the source electrode of the field-effect tube M17, the source electrode of the field-effect tube M24, the source electrode of the field-effect tube M25 and the source electrode of the field-effect tube M32 are all connected with an external power supply; the drain electrode of the field effect transistor M24 is connected with the source electrode of the field effect transistor M22; the drain electrode of the field effect transistor M25 is connected with the source electrode of the field effect transistor M23;
the grid electrode of the field effect transistor M22 is respectively connected with the grid electrode of the field effect transistor M23 and the second bias end of the bias circuit; the drain electrode of the field effect transistor M22 is respectively connected with one input end of the chopper CH2 and the drain electrode of the field effect transistor M20; the drain electrode of the field effect transistor M23 is respectively connected with the other input end of the chopper CH2 and the drain electrode of the field effect transistor M21; the grid electrode of the field effect transistor M20 is respectively connected with the grid electrode of the field effect transistor M21 and the third bias end of the bias circuit;
the grid electrode of the field effect transistor M18 is respectively connected with the grid electrode of the field effect transistor M19 and the feedback end of the common mode feedback circuit; the source electrode of the field-effect transistor M18 and the source electrode of the field-effect transistor M19 are both grounded;
the drain electrode of the field effect transistor M32 is respectively connected with one end of a resistor R2 and the drain electrode of the field effect transistor M31, the other end of the resistor R2 is connected with one end of a capacitor CAP2, and the other end of the capacitor CAP2 is respectively connected with the gate electrode of the field effect transistor M31 and one output end of a chopper CH 2; the source electrode of the field effect transistor M31 is grounded;
the drain electrode of the field effect transistor M17 is respectively connected with one end of a resistor R1 and the drain electrode of the field effect transistor M16, the other end of the resistor R1 is connected with one end of a capacitor CAP1, and the other end of the capacitor CAP1 is respectively connected with the gate electrode of the field effect transistor M16 and the other output end of the chopper CH 2; the source of the field effect transistor M16 is grounded.
Further, the bias circuit comprises a field effect transistor M1, a gate of the field effect transistor M1 is connected with a gate of the field effect transistor M2, a gate of the field effect transistor M3, a drain of the field effect transistor M1 and the control current IBN, respectively; the source electrode of the field-effect tube M1, the source electrode of the field-effect tube M2 and the source electrode of the field-effect tube M3 are all grounded;
the drain electrode of the field effect transistor M2 is respectively connected with the drain electrode of the field effect transistor M4, the grid electrode of the field effect transistor M4, the grid electrode of the field effect transistor M5, the grid electrode of the field effect transistor M6, the grid electrode of the field effect transistor M12 and the grid electrode of the field effect transistor M13, and is used as a second bias end of the bias circuit; the source electrode of the field effect transistor M4 is connected with the drain electrode of the field effect transistor M6; the source electrode of the field effect transistor M6 is connected with an external power supply;
the drain electrode of the field effect transistor M5 is respectively connected with the drain electrode of the field effect transistor M3, the grid electrode of the field effect transistor M7, the grid electrode of the field effect transistor M14 and the grid electrode of the field effect transistor M15 and is used as a first bias end of the bias circuit; the source electrode of the field effect transistor M5 is connected with the drain electrode of the field effect transistor M7, and the source electrode of the field effect transistor M7 is connected with an external power supply;
the source electrode of the field effect transistor M12 is connected with the drain electrode of the field effect transistor M14; the source electrode of the field effect transistor M13 is connected with the drain electrode of the field effect transistor M15; the source electrode of the field effect transistor M14 and the source electrode of the field effect transistor M15 are both connected with an external power supply; the drain of the field effect transistor M12 is connected to the drain of the field effect transistor M10, the gate of the field effect transistor M10, the gate of the field effect transistor M11 and the gate of the field effect transistor M8 respectively, and is used as a third bias terminal of the bias circuit;
the source electrode of the field-effect tube M10 is connected with the drain electrode of the field-effect tube M8, the source electrode of the field-effect tube M11 is connected with the drain electrode of the field-effect tube M9, and the source electrode of the field-effect tube M8 and the source electrode of the field-effect tube M9 are both grounded; the gate of the field effect transistor M9 is connected to the drain of the field effect transistor M11 and the drain of the field effect transistor M13, respectively.
Further, the common mode feedback circuit comprises a field effect transistor M34, the gate of the field effect transistor M34 is connected with the first bias end of the bias circuit, the source of the field effect transistor M34 is connected with an external power supply, and the drain of the field effect transistor M34 is respectively connected with the source of the field effect transistor M28 and the source of the field effect transistor M35;
the grid of the field effect transistor M35 is connected with a reference common mode level; the drain electrode of the field effect transistor M35 is respectively connected with the grid electrode and the drain electrode of the field effect transistor M30, and the source electrode of the field effect transistor M30 is grounded;
the source electrode of the field effect transistor M28 is respectively connected with the drain electrode and the grid electrode of the field effect transistor M29 and is used as the feedback end of the common mode feedback circuit; the source electrode of the field effect transistor M29 is grounded; the grid of the field effect transistor M28 is respectively connected with one end of a capacitor C1, one end of a capacitor C2, one end of a resistor R3 and one end of a resistor R4; the other end of the resistor R3 is connected with the other end of the capacitor C1 and is used as an output end of the chopping operational amplifier module; the other end of the resistor R4 is connected with the other end of the capacitor C2 and is used as the other output end of the chopping operational amplifier module.
Further, a signal Vin and a signal Vip in the external differential signal are respectively overlapped with two output signals of the switched capacitor integrator through a resistor R5 and a resistor R6 and then input to the first chopping operational amplifier module.
Further, a resistor R11 and a resistor R12 are respectively arranged in two lines between the switched capacitor integrator and the first chopping operational amplifier module.
Further, a resistor R7 and a resistor R8 are respectively arranged in two lines between the first chopping operational amplifier module and the second chopping operational amplifier module.
Further, a resistor R9 and a resistor R10 are respectively disposed in two lines between the second chopping operational amplifier module and the operational amplifier.
The invention has the beneficial effects that:
1. the system performs chopping and amplification on signals twice through the first chopping operational amplifier module and the second chopping operational amplifier module, and can perform chopping on offset voltage and flicker noise of the operational amplifier once, so that the signals are separated from direct current offset and flicker noise of the operational amplifier, the offset and noise are filtered, and the influence on original signals is avoided; meanwhile, low-pass filtering with the bandwidth of only 10Hz is realized through the switched capacitor integrator, and the control of a direct current signal is realized through the negative feedback of the switched capacitor integrator, so that the compensation effect on a large capacitor is obtained. Therefore, the system only increases a small amount of power consumption and area to achieve the effect of increasing a large blocking capacitor outside the chip, and can realize the full integration of the zero intermediate frequency receiver.
2. The system uses an integrator with a switched capacitor equivalent to a resistor as negative feedback. The integrator is low-pass characteristic, and as negative feedback, the integrator shows high-pass characteristic, so that the direct current offset output by the mixer is filtered. Meanwhile, the switched capacitor is used for replacing a resistor of a G omega level, so that the layout area is greatly reduced, the equivalent resistor is more accurate and controllable, on-chip full integration can be realized, and the zero intermediate frequency receiver mixer is very suitable for improving the performance of a zero intermediate frequency receiver mixer.
3. The high-pass inflection point of the system is determined by the frequency of an external input clock, so that the high-pass inflection point modification of filtering is conveniently realized.
Drawings
FIG. 1 is a block diagram of the overall structure of the present invention;
FIG. 2 is a circuit diagram of a chopper operational amplifier module;
FIG. 3 is an equivalent schematic of the chopper;
FIG. 4 is a schematic chopping diagram;
FIG. 5 is a timing logic diagram of the present system.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
As shown in fig. 1, the blocking capacitance compensation system suitable for the zero intermediate frequency receiver includes a first chopping operational amplifier module, a second chopping operational amplifier module, an operational amplifier and a switched capacitor integrator; the two output ends of the first chopping operational amplifier module are respectively connected with the two input ends of the second chopping operational amplifier module, the two output ends of the second chopping operational amplifier module are respectively connected with the two input ends of the switched capacitor integrator and the operational amplifier, the two output ends of the operational amplifier are output ends of the blocking capacitance compensation system, and the two output ends of the switched capacitor integrator and an external differential signal are superposed to jointly serve as two input signals of the first chopping operational amplifier module.
The switched capacitor integrator comprises a differential equivalent resistor and a third chopping operational amplifier module which are connected with each other, the input end of the differential equivalent resistor is the input end of the switched capacitor integrator, and the output end of the third chopping operational amplifier module is the output end of the switched capacitor integrator.
The differential equivalent resistor comprises a switch S1 and a switch S2, one end of the switch S1 and one end of the switch S2 are both input ends of the differential equivalent resistor, and the other end of the switch S1 is respectively connected with one end of the capacitor C3 and one end of the switch S3; the other end of the capacitor C3 is connected with one end of the switch S5 and one end of the switch S7 respectively;
the other end of the switch S2 is connected with one end of the capacitor C4 and one end of the switch S4 respectively; the other end of the capacitor C4 is connected with one end of the switch S6 and one end of the switch S8 respectively; the other end of the switch S3, the other end of the switch S4, the other end of the switch S5 and the other end of the switch S6 are all grounded; the other end of the switch S7 and the other end of the switch S8 are both output ends of the differential equivalent resistor; the switch S1, the switch S2, the switch S5 and the switch S6 are opened and closed simultaneously; the switch S3, the switch S4, the switch S7, and the switch S8 are opened and closed.
As shown in fig. 2, the chopping operational amplifier module includes a chopping amplifier circuit, and a bias circuit and a common mode feedback circuit respectively connected to the chopping amplifier circuit; the output end of the common mode feedback circuit is the output end of the chopping operational amplifier module;
the chopping amplification circuit comprises a chopper CH1 and a chopper CH2, the input end of the chopper CH1 is the input end of the chopping operational amplification module, and the output end of the chopper CH1 is respectively connected with the grid of the field-effect tube M26 and the grid of the field-effect tube M27; the source electrode of the field effect transistor M26 is respectively connected with the source electrode of the field effect transistor M27 and the drain electrode of the field effect transistor M33; the drain electrode of the field effect transistor M26 is respectively connected with the source electrode of the field effect transistor M20 and the drain electrode of the field effect transistor M18; the drain electrode of the field effect transistor M27 is respectively connected with the source electrode of the field effect transistor M21 and the drain electrode of the field effect transistor M19;
the source electrode of the field effect transistor M33 is connected with an external power supply, the grid electrode of the field effect transistor M33 is respectively connected with the grid electrode of the field effect transistor M24, the grid electrode of the field effect transistor M25, the grid electrode of the field effect transistor M32, the grid electrode of the field effect transistor M17 and a first bias end (BP1) of the bias circuit; the source electrode of the field-effect tube M17, the source electrode of the field-effect tube M24, the source electrode of the field-effect tube M25 and the source electrode of the field-effect tube M32 are all connected with an external power supply; the drain electrode of the field effect transistor M24 is connected with the source electrode of the field effect transistor M22; the drain electrode of the field effect transistor M25 is connected with the source electrode of the field effect transistor M23;
the grid electrode of the field effect transistor M22 is respectively connected with the grid electrode of the field effect transistor M23 and a second bias end (BP2) of the bias circuit; the drain electrode of the field effect transistor M22 is respectively connected with one input end of the chopper CH2 and the drain electrode of the field effect transistor M20; the drain electrode of the field effect transistor M23 is respectively connected with the other input end of the chopper CH2 and the drain electrode of the field effect transistor M21; the grid electrode of the field effect transistor M20 is respectively connected with the grid electrode of the field effect transistor M21 and a third bias end (BP3) of the bias circuit;
the grid electrode of the field effect transistor M18 is respectively connected with the grid electrode of the field effect transistor M19 and the feedback end (Vcfmb) of the common mode feedback circuit; the source electrode of the field-effect transistor M18 and the source electrode of the field-effect transistor M19 are both grounded;
the drain electrode of the field effect transistor M32 is respectively connected with one end of a resistor R2 and the drain electrode of the field effect transistor M31, the other end of the resistor R2 is connected with one end of a capacitor CAP2, and the other end of the capacitor CAP2 is respectively connected with the grid electrode of the field effect transistor M31 and one output end of a chopper CH 2; the source electrode of the field effect transistor M31 is grounded;
the drain electrode of the field effect transistor M17 is respectively connected with one end of a resistor R1 and the drain electrode of the field effect transistor M16, the other end of the resistor R1 is connected with one end of a capacitor CAP1, and the other end of the capacitor CAP1 is respectively connected with the gate electrode of the field effect transistor M16 and the other output end of the chopper CH 2; the source of the field effect transistor M16 is grounded.
The bias circuit comprises a field effect transistor M1, wherein the grid electrode of the field effect transistor M1 is respectively connected with the grid electrode of the field effect transistor M2, the grid electrode of the field effect transistor M3, the drain electrode of the field effect transistor M1 and a control current IBN; the source electrode of the field-effect tube M1, the source electrode of the field-effect tube M2 and the source electrode of the field-effect tube M3 are all grounded;
the drain electrode of the field effect transistor M2 is respectively connected with the drain electrode of the field effect transistor M4, the grid electrode of the field effect transistor M4, the grid electrode of the field effect transistor M5, the grid electrode of the field effect transistor M6, the grid electrode of the field effect transistor M12 and the grid electrode of the field effect transistor M13, and is used as a second bias end of the bias circuit; the source electrode of the field effect transistor M4 is connected with the drain electrode of the field effect transistor M6; the source electrode of the field effect transistor M6 is connected with an external power supply;
the drain electrode of the field effect transistor M5 is respectively connected with the drain electrode of the field effect transistor M3, the grid electrode of the field effect transistor M7, the grid electrode of the field effect transistor M14 and the grid electrode of the field effect transistor M15 and is used as a first bias end of the bias circuit; the source electrode of the field effect transistor M5 is connected with the drain electrode of the field effect transistor M7, and the source electrode of the field effect transistor M7 is connected with an external power supply;
the source electrode of the field effect transistor M12 is connected with the drain electrode of the field effect transistor M14; the source electrode of the field effect transistor M13 is connected with the drain electrode of the field effect transistor M15; the source electrode of the field effect transistor M14 and the source electrode of the field effect transistor M15 are both connected with an external power supply; the drain electrode of the field effect transistor M12 is respectively connected with the drain electrode of the field effect transistor M10, the grid electrode of the field effect transistor M10, the grid electrode of the field effect transistor M11 and the grid electrode of the field effect transistor M8 and is used as a third bias end of the bias circuit;
the source electrode of the field-effect tube M10 is connected with the drain electrode of the field-effect tube M8, the source electrode of the field-effect tube M11 is connected with the drain electrode of the field-effect tube M9, and the source electrode of the field-effect tube M8 and the source electrode of the field-effect tube M9 are both grounded; the gate of the field effect transistor M9 is connected to the drain of the field effect transistor M11 and the drain of the field effect transistor M13, respectively.
The common mode feedback circuit comprises a field effect transistor M34, the grid electrode of the field effect transistor M34 is connected with the first bias end of the bias circuit, the source electrode of the field effect transistor M34 is connected with an external power supply, and the drain electrode of the field effect transistor M34 is respectively connected with the source electrode of the field effect transistor M28 and the source electrode of the field effect transistor M35;
the grid of the field effect transistor M35 is connected with a reference common mode level (Vref); the drain electrode of the field effect transistor M35 is respectively connected with the grid electrode and the drain electrode of the field effect transistor M30, and the source electrode of the field effect transistor M30 is grounded;
the source electrode of the field effect transistor M28 is respectively connected with the drain electrode and the grid electrode of the field effect transistor M29 and is used as the feedback end of the common mode feedback circuit; the source electrode of the field effect transistor M29 is grounded; the grid of the field effect transistor M28 is respectively connected with one end of a capacitor C1, one end of a capacitor C2, one end of a resistor R3 and one end of a resistor R4; the other end of the resistor R3 is connected with the other end of the capacitor C1 and is used as an output end of the chopping operational amplifier module; the other end of the resistor R4 is connected with the other end of the capacitor C2 and is used as the other output end of the chopping operational amplifier module.
In the circuit, the field effect transistors M1-M15 form a current mirror to provide bias for the operational amplifier, the field effect transistors M18-M25 realize high gain for the folded cascode amplifier, and the field effect transistors M16, M17, M31 and M32 realize wide swing for the cascode amplifier. The fets M28, M29, M30, and M35 are common mode feedback circuits that determine the output common mode level. CAP1 and CAP2 are the compensation capacitance of the miller, and R1 and R2 are zero setting resistance for the stability of whole operational amplifier is adjusted. In the chopping operational amplifier module provided by the invention, the chopper is embedded into the operational amplifier circuit, and the internal self-contained two-stage choppers (CH1 and CH2) eliminate self offset voltage and flicker noise, so that the noise and offset caused by the operational amplifier can be better inhibited, and lower equivalent input noise is realized. The first-stage chopper modulates input differential signals Vin and Vip to high frequency and then transmits the signals to the amplifier for amplification, the signals are separated from flicker noise and offset frequency in the amplifier to avoid signal distortion, then the second-stage chopper demodulates and restores the original signal frequency, the noise and the offset at the moment can be modulated to the high frequency, and finally the signals are filtered by a filter, only the amplified input signals are output, and the influence of the noise and the offset is eliminated.
In a specific implementation process, a signal Vin and a signal Vip in the external differential signal are respectively overlapped with two paths of output signals of the switched capacitor integrator through a resistor R5 and a resistor R6 and then input into the first chopping operational amplifier module. And a resistor R11 and a resistor R12 are respectively arranged in two lines between the switched capacitor integrator and the first chopping operational amplifier module. And a resistor R7 and a resistor R8 are respectively arranged in two lines between the first chopping operational amplifier module and the second chopping operational amplifier module. And a resistor R9 and a resistor R10 are respectively arranged in two lines between the second chopping operational amplifier module and the operational amplifier.
The chopper CH1 and the chopper CH2 have the same structure, and as shown in FIG. 3, the chopperCan be equivalent to 4 switches (S)1、S2、S3And S4) Switch S1And switch S3Controlled by CLK clock signal, switch S2And switch S4By
Control of clock signals, CLK and
which are complementary non-overlapping clock signals, whose timing diagrams are shown in fig. 5, and the chopping which is implemented is shown in fig. 4.
In FIG. 4, chop denotes chopping, M1And M2M (t) clock signals for controlling chopping, i.e. CLK and
the mother signals of the complementary signals, CLK and m (t) are identical,
in contrast to m (t). The signal output by the mixer contains DC offset and useful signal at the point A; after the first stage chopping, all components output by the mixer are chopped to high frequency, and at this time, all signals amplified by the first stage amplifying circuit of the mixer and direct current offset and flicker noise generated by the first stage amplifying circuit are output, namely, the output corresponds to (c) in fig. 4; and then through the second stage of chopping, the direct current offset and noise generated by the first stage of amplifying circuit are converted into high frequency (the direct current offset and flicker noise of the second stage of amplifying circuit are small and neglected), and all components output by the mixer are chopped into low frequency and return to the initial state (but the amplitude is amplified). So far, the flicker noise is separated by the dc offset of the mixer output and the operational amplifier itself (corresponding to (d) in fig. 4), i.e. the dc offset and noise of the operational amplifier do not affect the useful signal of the mixer.
In FIG. 5, S1And S2For another complementary clock signal, with chopped CLK and
the signals are complementary non-overlapping clock signals, and are divided by the same signals. S1The signal controls switch S3, switch S4, switch S7, and switch S8; s2The signal controls switch S1, switch S2, switch S5, and switch S6. Within one clock period T (assuming no parasitic capacitance here), the amount of charge flowing through the differential equivalent resistor is equal to C (V)1-V2) Therefore, the average current flowing through the differential equivalent resistor in the circuit is:
therefore, the resistance of the equivalent resistor is:
when the capacitance is in the fF level, f is reasonably setclkThe level of the resistor G omega can be easily realized, the cut-off frequency is very low, and the layout area of the passive resistor is greatly reduced.
In summary, the first chopping operational amplifier module and the second chopping operational amplifier module perform chopping and amplification on the signal twice, so that the offset voltage and the flicker noise of the operational amplifier can be chopped once, the signal is separated from the direct current offset and the flicker noise of the operational amplifier, the offset and the noise are filtered, and the influence on the original signal is avoided; meanwhile, low-pass filtering with the bandwidth of only 10Hz is realized through the switched capacitor integrator, and the control of a direct current signal is realized through the negative feedback of the switched capacitor integrator, so that the compensation effect on a large capacitor is obtained. Therefore, the system only increases a small amount of power consumption and area to achieve the effect of increasing a large blocking capacitor outside the chip, and can realize the full integration of the zero intermediate frequency receiver.
Claims (9)
1. A blocking capacitor compensation system suitable for a zero intermediate frequency receiver is characterized by comprising a first chopping operational amplifier module, a second chopping operational amplifier module, an operational amplifier and a switched capacitor integrator; the two output ends of the switched capacitor integrator and an external differential signal are superposed and then are jointly used as two input signals of the first chopping operational amplifier module;
the chopping operational amplifier module comprises a chopping amplifying circuit, and a bias circuit and a common mode feedback circuit which are respectively connected with the chopping amplifying circuit; the output end of the common mode feedback circuit is the output end of the chopping operational amplifier module;
the chopping amplification circuit comprises a chopper CH1 and a chopper CH2, the input end of the chopper CH1 is the input end of the chopping operational amplification module, and the output end of the chopper CH1 is respectively connected with the grid of the field-effect tube M26 and the grid of the field-effect tube M27; the source electrode of the field effect transistor M26 is respectively connected with the source electrode of the field effect transistor M27 and the drain electrode of the field effect transistor M33; the drain electrode of the field effect transistor M26 is respectively connected with the source electrode of the field effect transistor M20 and the drain electrode of the field effect transistor M18; the drain electrode of the field effect transistor M27 is respectively connected with the source electrode of the field effect transistor M21 and the drain electrode of the field effect transistor M19;
the source electrode of the field-effect tube M33 is connected with an external power supply, and the grid electrode of the field-effect tube M33 is respectively connected with the grid electrode of the field-effect tube M24, the grid electrode of the field-effect tube M25, the grid electrode of the field-effect tube M32, the grid electrode of the field-effect tube M17 and the first bias end of the bias circuit; the source electrode of the field-effect tube M17, the source electrode of the field-effect tube M24, the source electrode of the field-effect tube M25 and the source electrode of the field-effect tube M32 are all connected with an external power supply; the drain electrode of the field effect transistor M24 is connected with the source electrode of the field effect transistor M22; the drain electrode of the field effect transistor M25 is connected with the source electrode of the field effect transistor M23;
the grid electrode of the field effect transistor M22 is respectively connected with the grid electrode of the field effect transistor M23 and the second bias end of the bias circuit; the drain electrode of the field effect transistor M22 is respectively connected with one input end of the chopper CH2 and the drain electrode of the field effect transistor M20; the drain electrode of the field effect transistor M23 is respectively connected with the other input end of the chopper CH2 and the drain electrode of the field effect transistor M21; the grid electrode of the field effect transistor M20 is respectively connected with the grid electrode of the field effect transistor M21 and the third bias end of the bias circuit;
the grid electrode of the field effect transistor M18 is respectively connected with the grid electrode of the field effect transistor M19 and the feedback end of the common mode feedback circuit; the source electrode of the field-effect transistor M18 and the source electrode of the field-effect transistor M19 are both grounded;
the drain electrode of the field effect transistor M32 is respectively connected with one end of a resistor R2 and the drain electrode of the field effect transistor M31, the other end of the resistor R2 is connected with one end of a capacitor CAP2, and the other end of the capacitor CAP2 is respectively connected with the gate electrode of the field effect transistor M31 and one output end of a chopper CH 2; the source electrode of the field effect transistor M31 is grounded;
the drain electrode of the field effect transistor M17 is respectively connected with one end of a resistor R1 and the drain electrode of the field effect transistor M16, the other end of the resistor R1 is connected with one end of a capacitor CAP1, and the other end of the capacitor CAP1 is respectively connected with the gate electrode of the field effect transistor M16 and the other output end of the chopper CH 2; the source of the field effect transistor M16 is grounded.
2. The blocking capacitance compensation system suitable for the zero intermediate frequency receiver according to claim 1, wherein the switched capacitor integrator comprises a differential equivalent resistor and a third chopping operational amplifier module which are connected with each other, an input end of the differential equivalent resistor is an input end of the switched capacitor integrator, and an output end of the third chopping operational amplifier module is an output end of the switched capacitor integrator.
3. The blocking capacitance compensation system for the zero intermediate frequency receiver of claim 2, wherein the differential equivalent resistor comprises a switch S1 and a switch S2, one end of the switch S1 and one end of the switch S2 are both input ends of the differential equivalent resistor, and the other end of the switch S1 is connected to one end of a capacitor C3 and one end of a switch S3 respectively; the other end of the capacitor C3 is connected to one end of the switch S5 and one end of the switch S7 respectively;
the other end of the switch S2 is connected with one end of the capacitor C4 and one end of the switch S4 respectively; the other end of the capacitor C4 is connected with one end of the switch S6 and one end of the switch S8 respectively; the other end of the switch S3, the other end of the switch S4, the other end of the switch S5 and the other end of the switch S6 are all grounded; the other end of the switch S7 and the other end of the switch S8 are the output ends of the differential equivalent resistor; the switch S1, the switch S2, the switch S5 and the switch S6 are opened and closed simultaneously; the switch S3, the switch S4, the switch S7, and the switch S8 are opened and closed.
4. The blocking capacitance compensation system for the zero intermediate frequency receiver of claim 1, wherein the bias circuit comprises a field effect transistor M1, a gate of the field effect transistor M1 is connected to a gate of the field effect transistor M2, a gate of the field effect transistor M3, a drain of the field effect transistor M1, and a control current IBN; the source electrode of the field-effect tube M1, the source electrode of the field-effect tube M2 and the source electrode of the field-effect tube M3 are all grounded;
the drain electrode of the field effect transistor M2 is respectively connected with the drain electrode of the field effect transistor M4, the grid electrode of the field effect transistor M4, the grid electrode of the field effect transistor M5, the grid electrode of the field effect transistor M6, the grid electrode of the field effect transistor M12 and the grid electrode of the field effect transistor M13, and is used as a second bias end of the bias circuit; the source electrode of the field effect transistor M4 is connected with the drain electrode of the field effect transistor M6; the source electrode of the field effect transistor M6 is connected with an external power supply;
the drain electrode of the field effect transistor M5 is respectively connected with the drain electrode of the field effect transistor M3, the grid electrode of the field effect transistor M7, the grid electrode of the field effect transistor M14 and the grid electrode of the field effect transistor M15 and is used as a first bias end of the bias circuit; the source electrode of the field effect transistor M5 is connected with the drain electrode of the field effect transistor M7, and the source electrode of the field effect transistor M7 is connected with an external power supply;
the source electrode of the field effect transistor M12 is connected with the drain electrode of the field effect transistor M14; the source electrode of the field effect transistor M13 is connected with the drain electrode of the field effect transistor M15; the source electrode of the field effect transistor M14 and the source electrode of the field effect transistor M15 are both connected with an external power supply; the drain of the field effect transistor M12 is connected to the drain of the field effect transistor M10, the gate of the field effect transistor M10, the gate of the field effect transistor M11 and the gate of the field effect transistor M8 respectively, and is used as a third bias terminal of the bias circuit;
the source electrode of the field-effect tube M10 is connected with the drain electrode of the field-effect tube M8, the source electrode of the field-effect tube M11 is connected with the drain electrode of the field-effect tube M9, and the source electrode of the field-effect tube M8 and the source electrode of the field-effect tube M9 are both grounded; the gate of the field effect transistor M9 is connected to the drain of the field effect transistor M11 and the drain of the field effect transistor M13, respectively.
5. The blocking capacitance compensation system for the zero intermediate frequency receiver of claim 4, wherein the common mode feedback circuit comprises a fet M34, a gate of the fet M34 is connected to the first bias terminal of the bias circuit, a source of the fet M34 is connected to the external power supply, and a drain of the fet M34 is connected to a source of the fet M28 and a source of the fet M35, respectively;
the grid of the field effect transistor M35 is connected with a reference common mode level; the drain electrode of the field effect transistor M35 is respectively connected with the grid electrode and the drain electrode of the field effect transistor M30, and the source electrode of the field effect transistor M30 is grounded;
the source electrode of the field effect transistor M28 is respectively connected with the drain electrode and the grid electrode of the field effect transistor M29 and is used as the feedback end of the common mode feedback circuit; the source electrode of the field effect transistor M29 is grounded; the grid of the field effect transistor M28 is respectively connected with one end of a capacitor C1, one end of a capacitor C2, one end of a resistor R3 and one end of a resistor R4; the other end of the resistor R3 is connected with the other end of the capacitor C1 and is used as an output end of the chopping operational amplifier module; the other end of the resistor R4 is connected with the other end of the capacitor C2 and is used as the other output end of the chopping operational amplifier module.
6. The blocking capacitance compensation system suitable for the zero intermediate frequency receiver of claim 1, wherein the signal Vin and the signal Vip in the external differential signal are respectively input to the first chopping operational amplifier module after being overlapped with the two output signals of the switched capacitor integrator through a resistor R5 and a resistor R6.
7. The blocking capacitance compensation system for the zero intermediate frequency receiver according to claim 1 or 6, wherein a resistor R11 and a resistor R12 are respectively disposed in two lines between the switched capacitor integrator and the first chopping operational amplifier module.
8. The blocking capacitance compensation system suitable for the zero intermediate frequency receiver according to claim 1, wherein a resistor R7 and a resistor R8 are respectively disposed in two lines between the first chopping operational amplifier module and the second chopping operational amplifier module.
9. The blocking capacitance compensation system for the zero intermediate frequency receiver according to claim 1, wherein a resistor R9 and a resistor R10 are respectively disposed in two lines between the second chopping operational amplifier module and the operational amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110810909.3A CN113746491B (en) | 2021-07-19 | 2021-07-19 | Blocking capacitor compensation system suitable for zero intermediate frequency receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110810909.3A CN113746491B (en) | 2021-07-19 | 2021-07-19 | Blocking capacitor compensation system suitable for zero intermediate frequency receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113746491A CN113746491A (en) | 2021-12-03 |
| CN113746491B true CN113746491B (en) | 2022-07-08 |
Family
ID=78728708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110810909.3A Active CN113746491B (en) | 2021-07-19 | 2021-07-19 | Blocking capacitor compensation system suitable for zero intermediate frequency receiver |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113746491B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114614843A (en) * | 2022-03-04 | 2022-06-10 | 成都通量科技有限公司 | DCOC circuit for zero intermediate frequency receiver |
| CN114696855A (en) * | 2022-03-22 | 2022-07-01 | 电子科技大学 | Novel zero intermediate frequency receiver |
| CN114533087B (en) * | 2022-04-28 | 2022-08-26 | 之江实验室 | Method and system for eliminating direct current offset between electrodes based on chopping technology |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101394163A (en) * | 2008-10-09 | 2009-03-25 | 捷顶微电子（上海）有限公司 | Signal conditioning circuit and dual sampling-hold circuit applying the conditioning method |
| CN102347738A (en) * | 2010-08-04 | 2012-02-08 | 中国科学院微电子研究所 | Two-stage fully-differential low-noise low-offset chopping operational amplifier |
| CN103391100A (en) * | 2013-07-03 | 2013-11-13 | 江苏博纳雨田通信电子有限公司 | Novel high pass chopper Delta-Sigma analog-digital converter |
| CN103634017A (en) * | 2013-12-09 | 2014-03-12 | 沈阳永业实业有限公司 | Ultralow-frequency electromagnetic wave receiver of tube cleaner |
| US9473074B1 (en) * | 2015-09-14 | 2016-10-18 | Ixys Corporation | Chopper stabilized amplifier with synchronous switched capacitor noise filtering |
| CN108233933A (en) * | 2018-02-02 | 2018-06-29 | 中国科学院微电子研究所 | Fully differential CMOS switched-capacitor integrator |
| CN108777671A (en) * | 2018-06-04 | 2018-11-09 | 中国电子科技集团公司第三十八研究所 | A kind of ultra-wideband orthogonal demodulates compensation method and the device of receiver |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7292095B2 (en) * | 2006-01-26 | 2007-11-06 | Texas Instruments Incorporated | Notch filter for ripple reduction in chopper stabilized amplifiers |
| CN103280948B (en) * | 2013-06-05 | 2016-04-20 | 广州金升阳科技有限公司 | A kind of impulse modulation magnetic separation drive circuit |
| CN109600120B (en) * | 2018-11-22 | 2021-11-02 | 北京航空航天大学 | Ultra-wideband low-noise amplifier adopting mixed frequency compensation network |
| US11012043B2 (en) * | 2019-08-19 | 2021-05-18 | Cirrus Logic, Inc. | Hybrid autozeroing and chopping offset cancellation for switched-capacitor circuits |
-
2021
- 2021-07-19 CN CN202110810909.3A patent/CN113746491B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101394163A (en) * | 2008-10-09 | 2009-03-25 | 捷顶微电子（上海）有限公司 | Signal conditioning circuit and dual sampling-hold circuit applying the conditioning method |
| CN102347738A (en) * | 2010-08-04 | 2012-02-08 | 中国科学院微电子研究所 | Two-stage fully-differential low-noise low-offset chopping operational amplifier |
| CN103391100A (en) * | 2013-07-03 | 2013-11-13 | 江苏博纳雨田通信电子有限公司 | Novel high pass chopper Delta-Sigma analog-digital converter |
| CN103634017A (en) * | 2013-12-09 | 2014-03-12 | 沈阳永业实业有限公司 | Ultralow-frequency electromagnetic wave receiver of tube cleaner |
| US9473074B1 (en) * | 2015-09-14 | 2016-10-18 | Ixys Corporation | Chopper stabilized amplifier with synchronous switched capacitor noise filtering |
| CN108233933A (en) * | 2018-02-02 | 2018-06-29 | 中国科学院微电子研究所 | Fully differential CMOS switched-capacitor integrator |
| CN108777671A (en) * | 2018-06-04 | 2018-11-09 | 中国电子科技集团公司第三十八研究所 | A kind of ultra-wideband orthogonal demodulates compensation method and the device of receiver |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113746491A (en) | 2021-12-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113746491B (en) | Blocking capacitor compensation system suitable for zero intermediate frequency receiver | |
| Senderowicz et al. | High-performance NMOS operational amplifier | |
| US7420423B2 (en) | Active balun device | |
| US6160450A (en) | Self-biased, phantom-powered and feedback-stabilized amplifier for electret microphone | |
| US5578964A (en) | CMOS differential operational amplifier | |
| CN102075145B (en) | High-linearity folding image mixer | |
| KR101333421B1 (en) | Low voltage low power class a/b output stage | |
| CN105207636B (en) | The low-noise amplifier of variable gain | |
| US9503053B1 (en) | Active balun for wideband applications | |
| CN106533364B (en) | Passive mixer and operation method | |
| CN105720929B (en) | A kind of wide high-frequency low-noise acoustic amplifier of band gap automatic biasing | |
| KR19980036295A (en) | Mixers with Replication Voltage-to-Current Converter | |
| CN114696855A (en) | Novel zero intermediate frequency receiver | |
| JPH04233306A (en) | Linear cmos output stage | |
| US10116267B2 (en) | Single-ended amplifier circuit with improved chopper configuration | |
| CN111371413A (en) | Analog front-end circuit suitable for human pulse signals | |
| CN101212202B (en) | Frequency mixer with a filtering module for filtering off low-frequency component and reducing noise index | |
| CN111277225B (en) | Low-power-consumption constant transconductance rail-to-rail operational amplifier | |
| US9231540B2 (en) | High performance class AB operational amplifier | |
| CN116008916A (en) | Gain and bandwidth variable low-power consumption high-linearity analog baseband circuit | |
| CN109004905A (en) | A kind of up-conversion mixer with balun | |
| CN211209670U (en) | Analog front-end circuit suitable for human pulse signals | |
| US20070139110A1 (en) | Transconductance circuit | |
| TWI833350B (en) | Linear amplifier and supply modulator | |
| CN211830712U (en) | High-speed high-gain programmable amplifier circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |