CN216490404U

CN216490404U - Operation amplifying circuit with self-adaptive slew rate enhancement

Info

Publication number: CN216490404U
Application number: CN202123224230.0U
Authority: CN
Inventors: 刘焕双; 漆星宇; 李肖飞; 郑宗源; 刘树钰; 王赛; 张明; 王新安
Original assignee: Jiangsu Runic Technology Co ltd
Current assignee: Jiangsu Runic Technology Co ltd
Priority date: 2021-12-21
Filing date: 2021-12-21
Publication date: 2022-05-10
Anticipated expiration: 2031-12-21

Abstract

The utility model relates to an operational amplification circuit of self-adaptation slew rate reinforcing. The input stage amplifying circuit comprises an input stage amplifying circuit, wherein when a rising edge slew rate enhancing module enters a rising edge slew rate enhancing state, the rising edge slew rate enhancing module detects corresponding differential input current and generates a rising edge slew compensation current, and the rising edge slew rate enhancing module loads the generated rising edge slew compensation current to the output end of the input stage amplifying circuit; when the falling edge slew rate enhancement module enters a falling edge slew rate enhancement state, the falling edge slew rate enhancement module detects corresponding differential input current and generates a falling edge slew compensation current, and the falling edge slew rate enhancement module loads the generated falling edge slew compensation current to the output end of the input stage amplification circuit. The utility model discloses can the reinforcing of self-adaptation slew rate, improve the stability and the reliability of slew rate reinforcing, the consumption is little, safe and reliable.

Description

Operation amplifying circuit with self-adaptive slew rate enhancement

Technical Field

The utility model relates to an operational amplification circuit, especially an operational amplification circuit of self-adaptation slew rate reinforcing.

Background

Operational amplifiers are basic modules in Analog circuits, and are often used as intermediate drivers, such as driving display circuits, driving ADCs (Analog-to-Digital converters), and so on. The equivalent capacitance in the display circuit is larger, and the capacitance array equivalent capacitance of the ADC is also larger; therefore, the driving capability of the operational amplifier to the capacitive load directly affects the frame rate of the display circuit and the conversion accuracy and operating frequency of the ADC. At present, an ADC mainly uses a capacitor array for scaling and quantizing point positions, the capacitance value of the capacitor array is generally hundreds of picofarads, and effective driving is difficult to realize by a common operational amplifier.

In order to drive capacitive loads quickly, the operational amplifier needs to have a sufficiently large slew rate. The slew rate of the operational amplifier needs to be increased by higher power consumption, so that the mainstream solution is to add a slew rate enhancement module on the basis of the operational amplifier, use an auxiliary amplifier to detect the difference value of the differential input voltage, and generate a path of current to charge and discharge a capacitive load when the absolute value of the difference value is greater than a threshold value, so as to enhance the slew rate. Because the operational amplifier has an input offset voltage generated due to mismatch, when the differential input is zero, the output voltage is not zero, and therefore, the slew rate enhancement mode can cause a larger error, and is not suitable for the operational amplifier connected into a negative feedback mode with high amplification factor.

In summary, how to effectively enhance the slew rate of the operational amplifier is a technical problem which needs to be solved urgently at present.

Disclosure of Invention

The utility model aims at overcoming the not enough of existence among the prior art, providing an operational amplifier circuit of self-adaptation slew rate reinforcing, its ability self-adaptation slew rate reinforcing improves the stability and the reliability of slew rate reinforcing, and the consumption is little, safe and reliable.

According to the technical scheme provided by the utility model, the operational amplification circuit of self-adaptation slew rate reinforcing, including input stage amplifier circuit, still include the slew rate reinforcing circuit who is used for reinforcing the slew rate, slew rate reinforcing circuit includes rising edge slew rate reinforcing module and/or falling edge slew rate reinforcing module, and rising edge slew rate reinforcing module, falling edge slew rate reinforcing module are connected with input stage amplifier circuit adaptation electricity;

the input stage amplifying circuit receives the loaded differential input voltage and obtains a corresponding differential input current according to the received differential input voltage; according to the differential input current, the falling edge slew rate enhancement module enters a falling edge slew rate enhancement state or the rising edge slew rate enhancement module enters a rising edge slew rate enhancement state;

when the rising edge slew rate enhancement module enters a rising edge slew rate enhancement state, the rising edge slew rate enhancement module generates an adaptive rising edge slew compensation current according to the detected differential input current, and the rising edge slew rate enhancement module loads the generated rising edge slew compensation current to the output end of the input stage amplification circuit;

when the falling edge slew rate enhancement module enters a falling edge slew rate enhancement state, the falling edge slew rate enhancement module detects that an adaptive falling edge slew compensation current is generated according to the detected differential input current, and the falling edge slew rate enhancement module loads the generated falling edge slew compensation current to the output end of the input stage amplification circuit.

The input stage amplifying circuit comprises a differential input connecting part and a folding type cascode circuit which is in adaptive connection with the differential input connecting part, and a rising edge slew rate enhancing module and a falling edge slew rate enhancing module are in adaptive connection with the folding type cascode circuit;

the differential input connecting part comprises a PMOS tube M1 and a PMOS tube M2, wherein a gate terminal of the PMOS tube M1 is used for forming a differential input end INP, a gate terminal of the PMOS tube M2 is used for forming a differential input end INN, a source terminal of the PMOS tube M1 and a source terminal of the PMOS tube M2 are connected with a drain terminal of the PMOS tube M11, a gate terminal of the PMOS tube M11 is connected with a bias voltage VBIAS1, and a source terminal of the PMOS tube M11 is in adaptive connection with a folding cascode circuit, a rising edge slew rate enhancement module and a falling edge slew rate enhancement module; the drain end of the PMOS tube M1 and the drain end of the PMOS tube M2 are in adaptive connection with the folding cascode circuit.

The folded cascode circuit comprises a PMOS tube M3 and a PMOS tube M4, wherein the grid end of the PMOS tube M3 is in adaptive connection with the grid end of the PMOS tube M4, the drain end of the PMOS tube M5, the drain end of the NMOS tube M7, a rising edge slew rate enhancement module and a falling edge slew rate enhancement module;

the source end of the PMOS tube M3 and the source end of the PMOS tube M4 are in adaptive connection with the source end of the PMOS tube M11, the rising edge slew rate enhancement module and the falling edge slew rate enhancement module; the drain end of the PMOS tube M3 is connected with the source end of the PMOS tube M5, and the source end of the NMOS tube M7 is connected with the drain end of the PMOS tube M2 and the drain end of the NMOS tube M9;

the drain end of the PMOS tube M4 is connected with the source end of the PMOS tube M6, and the grid end of the PMOS tube M6 and the grid end of the PMOS tube M5 are both connected with a bias voltage VBIAS 2; the drain end of the PMOS tube M6 is in adaptive connection with the drain end of the NMOS tube M8, the rising edge slew rate enhancement module and the falling edge slew rate enhancement module;

the source end of the NMOS tube M8 is connected with the drain end of the NMOS tube M10 and the drain end of the PMOS tube M1, and the gate end of the NMOS tube M8 and the gate end of the NMOS tube M7 are both connected with a bias voltage VBIAS 3; the drain end of the NMOS tube M8 is in adaptive connection with the drain end of the PMOS tube M6, the rising edge slew rate enhancement module and the falling edge slew rate enhancement module to form an output end VOUT of an input stage amplification circuit of the input stage amplification circuit;

the source terminal of the NMOS transistor M9, the source terminal of the NMOS transistor M10, the rising edge slew rate enhancement module, and the falling edge slew rate enhancement module are adaptively connected, and the gate terminal of the NMOS transistor M9 and the gate terminal of the NMOS transistor M10 are connected to the bias voltage VBIAS 4.

The rising edge slew rate enhancement module comprises a PMOS tube M22, a PMOS tube M23, a PMOS tube M24, a PMOS tube M25, an NMOS tube M26, an NMOS tube M27, an NMOS tube M28 and an NMOS tube M29;

the grid end of the PMOS tube M22 is connected with the grid end of the POMS tube M3, the grid end of the PMOS tube M4, the drain end of the PMOS tube M5 and the drain end of the PMOS tube M7, and the source end of the PMOS tube M22 is connected with the source end of the PMOS tube M23, the source end of the PMOS tube M11, the source end of the PMOS tube M3 and the source end of the PMOS tube M4; the drain terminal of the PMOS transistor M22 is connected with the source terminal of the PMOS transistor M24, the drain terminal of the PMOS transistor M24 is connected with the drain terminal of the NMOS transistor M26, the source terminal of the NMOS transistor M26 is connected with the drain terminal of the NMOS transistor M28, the gate terminal of the NMOS transistor M29, the drain terminal of the NMOS transistor M29 and the source terminal of the NMOS transistor M27, the source terminal of the NMOS transistor M28 is connected with the source terminal of the NMOS transistor M29, the source terminal of the NMOS transistor M9 and the source terminal of the NMOS transistor M10, and the gate terminal of the NMOS transistor M28 receives a bias voltage VBIAS 4;

the drain end of the PMOS tube M23 is connected with the source base of the PMOS tube M25, the drain end of the PMOS tube M25 is connected with the drain end of the NMOS tube M27, the grid end of the PMOS tube M25 and the grid end of the PMOS tube M24 are both connected with a bias voltage VBIAS2, and the grid end of the NMOS tube M26 and the grid end of the NMOS tube M27 are both connected with a bias voltage VBIAS 3; the drain end of the PMOS transistor M23 is also connected to the output terminal VOUT of the input stage amplifier circuit through a rising edge current limiting protection transmission circuit, so that the rising edge slew compensation current is loaded to the output terminal VOUT of the input stage amplifier circuit through the rising edge current limiting protection transmission circuit.

The rising edge current-limiting protection transmission circuit comprises a PMOS tube M30 and a PMOS tube M31, wherein a source end of the PMOS tube M30 is connected with a source end of the PMOS tube M22, a source end of the PMOS tube M23, a source end of the PMOS tube M11, a source end of the PMOS tube M3 and a source end of the PMOS tube M4, a drain end of the PMOS tube M30 is connected with a source end of the PMOS tube M31, and a grid end of the PMOS tube M30 is connected with a grid end of the PMOS tube M23, a drain end of the PMOS tube M23 and a source end of the PMOS tube M25;

the drain end of the PMOS transistor M31 is connected to the output terminal VOUT of the input stage amplifying circuit, and the gate end of the PMOS transistor M31 is connected to the bias voltage VBIAS 2.

The falling edge slew rate enhancement module comprises a PMOS tube M12, a PMOS tube M13, a PMOS tube M14, a PMOS tube M15, an NMOS tube M16, an NMOS tube M17, an NMOS tube M18 and an NMOS tube M19;

the grid end of the PMOS tube M12 is connected with the grid end of the POMS tube M3, the grid end of the PMOS tube M4, the drain end of the PMOS tube M5 and the drain end of the PMOS tube M7, and the source end of the PMOS tube M12 is connected with the source end of the PMOS tube M13, the source end of the PMOS tube M11, the source end of the PMOS tube M3 and the source end of the PMOS tube M4; the drain terminal of the PMOS tube M12 is connected with the source terminal of the PMOS tube M14, the gate terminal of the PMOS tube M13, the drain terminal of the PMOS tube M13 and the source terminal of the PMOS tube M15, the drain terminal of the PMOS tube M14 is connected with the drain terminal of the NMOS tube M16, the source terminal of the NMOS tube M16 is connected with the drain terminal of the NMOS tube M18, the drain terminal of the PMOS tube M15 is connected with the drain terminal of the NMOS tube M17, the source terminal of the NMOS tube M17 is connected with the drain terminal of the NMOS tube M19 and the gate terminal of the NMOS tube M19, and the source terminal of the NMOS tube M17 is also connected with the output terminal VOUT of the input stage amplifying circuit through a falling edge protection transmission circuit;

the grid end of the PMOS tube M14 and the grid end of the PMOS tube M15 are connected with a bias voltage VBIAS2, the grid end of the NMOS tube M16 and the grid end of the NMOS tube M17 are connected with a bias voltage VBIAS3, and the grid end of the NMOS tube M18 is connected with the source end of the NMOS tube M18, the source end of the NMOS tube M19, the source end of the NMOS tube M9 and the source end of the NMOS tube M10.

The falling edge current-limiting protection transmission circuit comprises an NMOS tube M20 and an NMOS tube M21, wherein a drain electrode of the NMOS tube M21 is connected with an output end VOUT of the input-stage amplifying circuit, a source electrode of the NMOS tube M21 is connected with a drain electrode of the NMOS tube M20, a grid electrode of the NMOS tube M20 is connected with a grid electrode of the NMOS tube M19, a drain electrode of the NMOS tube M19 and a source electrode of the NMOS tube M17, and a source electrode of the NMOS tube M20 is connected with a source electrode of the NMOS tube M9, a source electrode of the NMOS tube M10, a source electrode of the NMOS tube M19, a source electrode of the NMOS tube M18 and a grid electrode of the NMOS tube M18.

The device also comprises an output stage circuit which is in adaptive connection with the input stage amplifying circuit and a Miller compensation circuit which is used for performing nested Miller compensation on the input stage amplifying circuit and the output stage circuit.

The Miller compensation circuit comprises a compensation resistor Rc connected with the output end of the input stage amplification circuit, and the compensation resistor Rc is connected with the output end of the output stage circuit through a compensation capacitor Cc.

The bias voltage generating circuit comprises a reference voltage circuit and a bias connecting circuit connected with the reference voltage circuit, and is in adaptive connection with the input stage amplifying circuit and the slew rate enhancing circuit through the bias connecting circuit.

The utility model has the advantages that: the slew rate enhancement circuit is connected with the input stage amplification circuit, when the rising edge slew rate enhancement module enters a rising edge slew rate enhancement state, the rising edge slew rate enhancement module can be used for generating rising edge slew compensation current, and the generated rising edge slew compensation current is loaded to the output end of the input stage amplification circuit so as to accelerate the charging and discharging of a capacitive load connected with the output end of the input stage amplification circuit; similarly, when the falling edge slew rate enhancement module enters a falling edge slew rate enhancement state, the falling edge slew rate enhancement module can be used for generating a falling edge slew compensation current, and the generated falling edge slew compensation current is loaded to the output end of the input stage amplification circuit so as to accelerate the charging and discharging of a capacitive load connected with the output end of the input stage amplification circuit; namely, the rising edge slew rate enhancement module and the falling edge slew rate enhancement module can effectively detect the slew state corresponding to the differential input voltage by detecting the differential input current corresponding to the differential input voltage, can self-adapt to the differential input voltage of the input stage amplification circuit, reduce the requirement on the size of the corresponding input geminate transistor in the input stage amplification circuit, reduce the cost and improve the adaptation range and the reliability.

Drawings

Fig. 1 is a block diagram of the present invention.

Fig. 2 is a schematic circuit diagram of the input stage amplifying circuit and slew rate enhancement circuit of the present invention.

Fig. 3 is a schematic circuit diagram of the miller compensation circuit in cooperation with the input stage amplifying circuit and the output stage circuit.

Description of reference numerals: the circuit comprises a 1-input stage amplifying circuit, a 2-output stage circuit, a 3-Miller compensation circuit, a 4-slew rate enhancement circuit, a 5-bias connection circuit and a 6-reference voltage circuit.

Detailed Description

The invention is further described with reference to the following specific drawings and examples.

As shown in fig. 1: in order to enhance the slew rate in a self-adaptive manner and improve the stability and reliability of the slew rate enhancement, the utility model discloses an input stage amplifying circuit 1, further comprising a slew rate enhancing circuit 4 for enhancing the slew rate, wherein the slew rate enhancing circuit 4 comprises a rising edge slew rate enhancing module and/or a falling edge slew rate enhancing module, and the rising edge slew rate enhancing module and the falling edge slew rate enhancing module are in adaptive electric connection with the input stage amplifying circuit 1;

the input stage amplifying circuit 1 receives the loaded differential input voltage and obtains a corresponding differential input current according to the received differential input voltage; the rising edge slew rate enhancement module and the falling edge slew rate enhancement module simultaneously detect differential input currents, and the falling edge slew rate enhancement module enters a falling edge slew rate enhancement state or the rising edge slew rate enhancement module enters a rising edge slew rate enhancement state according to the detected differential input currents;

when the rising edge slew rate enhancement module enters a rising edge slew rate enhancement state, the rising edge slew rate enhancement module generates an adaptive rising edge slew compensation current according to the detected differential input current, and the rising edge slew rate enhancement module loads the generated rising edge slew compensation current to the output end of the input stage amplification circuit 1 so as to utilize the rising edge slew compensation current to accelerate charging and discharging of a capacitive load connected with the output end of the input stage amplification circuit 1;

when the falling edge slew rate enhancement module enters a falling edge slew rate enhancement state, the falling edge slew rate enhancement module detects that an adaptive falling edge slew compensation current is generated according to the detected differential input current, and the falling edge slew rate enhancement module loads the generated falling edge slew compensation current to the output end of the input stage amplification circuit 1, so that the capacitive load connected with the output end of the input stage amplification circuit 1 can be charged and discharged quickly by utilizing the falling edge slew compensation current.

Specifically, the input stage amplifying circuit 1 may adopt a conventional form, and the input stage amplifying circuit 1 specifically adopts a differential input form, that is, the input stage amplifying circuit 1 can receive a differential input voltage, the input stage amplifying circuit 1 can amplify the received differential input voltage, and the specific condition of amplifying the differential input voltage by using the input stage amplifying circuit 1 is consistent with the conventional one, which is known to those skilled in the art and is not described herein again.

Slew rate enhancement can be realized through slew rate enhancement circuit 4, and slew rate enhancement circuit 4 specifically can include rising edge slew rate enhancement module or falling edge slew rate enhancement module, and of course, in order to adapt to all operating conditions of input stage amplifier circuit 1, generally include rising edge slew rate enhancement module and falling edge slew rate enhancement module simultaneously in slew rate enhancement circuit 4. According to the difference of the differential input voltage of the input stage amplifying circuit 1, that is, when the rising speed of the output signal of the input stage amplifying circuit 1 is limited by the slew rate, the rising edge slew rate enhancement module can enhance the rising edge slew rate, or when the falling speed of the output signal of the input stage amplifying circuit 1 is limited by the slew rate, the falling edge slew rate enhancement module enhances the falling edge slew rate, and the specific slew rate enhancement condition is related to the differential input voltage received by the input stage amplifying circuit 1, which is well known to those skilled in the art, and is not described herein again.

The embodiment of the utility model provides an in, according to the differential input voltage who loads to input stage amplifier circuit 1 to obtain a corresponding differential input current according to the differential input voltage who receives, differential input current is promptly for being used for the reference current that charges or the reference current that discharges to being connected capacitive load with input stage amplifier circuit 1 output. During specific implementation, the rising edge slew rate enhancement module and the falling edge slew rate enhancement module simultaneously detect differential input currents, and according to the detected differential input currents, the falling edge slew rate enhancement module enters a falling edge slew rate enhancement state or the rising edge slew rate enhancement module enters a rising edge slew rate enhancement state.

During specific implementation, when the rising edge slew rate enhancement module enters a rising edge slew rate enhancement state, the rising edge slew rate enhancement module generates adaptive rising edge slew compensation current according to the detected differential input current, and the rising edge slew rate enhancement module loads the generated rising edge slew compensation current to the output end of the input stage amplification circuit 1 so as to utilize the rising edge slew compensation current to accelerate charging and discharging of a capacitive load connected with the output end of the input stage amplification circuit 1; specifically, the charging state or the discharging state of the capacitive load is accelerated by the rising edge rolling compensation current, that is, the differential input current and the rising edge rolling compensation current are simultaneously loaded on the capacitive load, and the charging state or the discharging state of the capacitive load is specifically related to the connection form of the capacitive load and the input stage amplifying circuit 1, which is well known to those skilled in the art and is not described herein again. As can be seen from the calculation and determination of the slew rate, when the capacitive load is determined, the slew rate of the input stage amplifying circuit 1 when the differential input voltage is in the rising edge state can be increased by increasing the charge/discharge current of the capacitive load.

Similarly, when the falling edge slew rate enhancement module enters a falling edge slew rate enhancement state, the falling edge slew rate enhancement module detects that an adaptive falling edge slew compensation current is generated according to the detected differential input current, and the falling edge slew rate enhancement module loads the generated falling edge slew compensation current to the output end of the input stage amplification circuit 1, so that the capacitive load connected with the output end of the input stage amplification circuit 1 can be charged and discharged in an accelerated manner by utilizing the falling edge slew compensation current. The specific manner and process of enhancing the falling edge slew rate by generating the falling edge slew rate compensation current can refer to the above description, which is well known to those skilled in the art and will not be described herein again.

When the existing slew rate enhancement detects the slew state through the difference value of the differential input voltage, when the differential input voltage difference of an application scene is small, the slew state cannot be detected, and the slew state can be accurately detected only when the area of input geminate transistors receiving the differential input voltage is large due to the existence of input offset voltage of the input stage amplifying circuit 1. Therefore, compare with current slew rate reinforcing difference through differential input voltage and detect the slew state, the utility model discloses rising edge slew rate reinforcing module and falling edge slew rate reinforcing module are through detecting the corresponding differential input current with differential input voltage to can effectively detect the corresponding slew state of pressing of differential input voltage, can adapt to input stage amplifier circuit 1's the condition, reduce the dimensional requirement to corresponding input geminate transistor in the input stage amplifier circuit 1, reduce cost improves accommodation and reliability.

As shown in fig. 2, the input stage amplifying circuit 1 includes a differential input connection portion and a folded cascode circuit adaptively connected to the differential input connection portion, and a rising edge slew rate enhancement module and a falling edge slew rate enhancement module are adaptively connected to the folded cascode circuit;

The embodiment of the utility model provides an in, when input stage amplifier circuit 1 adopted the cooperation form of difference input connecting portion and foldable cascode circuit, can also obtain great output amplitude of oscillation when improving the operational amplification gain. An input pair transistor can be formed by a PMOS transistor M1 and a PMOS transistor M2, and can receive a differential input voltage through a differential input terminal INP connected with the gate terminal of the PMOS transistor M1 and through a differential input terminal INN connected with the gate terminal of the PMOS transistor M2, and is generally in a rising edge state when the voltage of the differential input terminal INP is greater than that of the differential input terminal INN; when the voltage at the differential input terminal INP is smaller than the voltage at the differential input terminal INN, the falling edge state is assumed.

Further, the folded cascode circuit comprises a PMOS transistor M3 and a PMOS transistor M4, wherein the gate terminal of the PMOS transistor M3 is adaptively connected to the gate terminal of the PMOS transistor M4, the drain terminal of the PMOS transistor M5, the drain terminal of the NMOS transistor M7, the rising edge slew rate enhancement module, and the falling edge slew rate enhancement module;

the source end of the NMOS tube M8 is connected with the drain end of the NMOS tube M10 and the drain end of the PMOS tube M1, and the gate end of the NMOS tube M8 and the gate end of the NMOS tube M7 are both connected with a bias voltage VBIAS 3; the drain end of the NMOS tube M8 is in adaptive connection with the drain end of the PMOS tube M6, the rising edge slew rate enhancement module and the falling edge slew rate enhancement module to form an output end VOUT of the input stage amplification circuit 1;

Specifically, the input stage amplifying circuit output terminal VOUT is an output terminal of the input stage amplifying circuit 1. The folded cascode circuit and the differential input connection portion cooperate to form the input stage amplification circuit 1, and the process of implementing amplification of the differential input is the same as that in the prior art, which is well known to those skilled in the art and will not be described herein again.

Further, the rising edge slew rate enhancement module comprises a PMOS transistor M22, a PMOS transistor M23, a PMOS transistor M24, a PMOS transistor M25, an NMOS transistor M26, an NMOS transistor M27, an NMOS transistor M28, and an NMOS transistor M29;

the grid end of the PMOS tube M22 is connected with the grid end of the POMS tube M3, the grid end of the PMOS tube M4, the drain end of the PMOS tube M5 and the drain end of the PMOS tube M7, and the source end of the PMOS tube M22 is connected with the source end of the PMOS tube M23, the source end of the PMOS tube M11, the source end of the PMOS tube M3 and the source end of the PMOS tube M4; the drain terminal of the PMOS transistor M22 is connected with the source terminal of the PMOS transistor M24, the drain terminal of the PMOS transistor M24 is connected with the drain terminal of the NMOS transistor M26, the source terminal of the NMOS transistor M26 is connected with the drain terminal of the NMOS transistor M28, the gate terminal of the NMOS transistor M29, the drain terminal of the NMOS transistor M29 and the source terminal of the NMOS transistor M27, the source terminal of the NMOS transistor M28 is connected with the source terminal of the NMOS transistor M29, the source terminal of the NMOS transistor M9 and the source terminal of the NMOS transistor M10, and the gate terminal of the NMOS transistor M28 receives bias voltage VBIAS 4;

In specific implementation, the rising edge current-limiting protection transmission circuit comprises a PMOS transistor M30 and a PMOS transistor M31, wherein a source terminal of the PMOS transistor M30 is connected with a source terminal of the PMOS transistor M22, a source terminal of the PMOS transistor M23, a source terminal of the PMOS transistor M11, a source terminal of the PMOS transistor M3 and a source terminal of the PMOS transistor M4, a drain terminal of the PMOS transistor M30 is connected with a source terminal of the PMOS transistor M31, and a gate terminal of the PMOS transistor M30 is connected with a gate terminal of the PMOS transistor M23, a drain terminal of the PMOS transistor M23 and a source terminal of the PMOS transistor M25;

The embodiment of the utility model provides an in, PMOS pipe M22 constitutes a current comparator with NMOS pipe M28, wherein, because PMOS pipe M22's grid end and PMOS pipe M3, PMOS pipe M4, PMOS pipe M5 and NMOS pipe M7 adaptation connection, consequently, PMOS pipe M22 can acquire the electric current that flows through PMOS pipe M3, PMOS pipe M5 and NMOS pipe M7 place branch road, and the electric current that flows through NMOS pipe M28 mirror image NMOS pipe M9, with as rising edge pressure pendulum reinforcing reference current.

In order to realize hysteresis control, when the whole rising edge slew rate enhancement module is in a non-slew state according to the rising edge slew enhancement reference current, the current mirrored by the PMOS transistor M22 is smaller than the reference current mirrored by the NMOS transistor M28. In a non-slew state, the PMOS transistor M22 operates in a saturation region, the NMOS transistor M28 operates in a linear region, and at this time, the NMOS transistor M29 is in an off state, no current flows through the NMOS transistor M29, and the rising edge slew rate enhancement module does not output a rising edge slew compensation current. In a 'swing voltage' state, the current mirrored by the PMOS tube M22 is larger than the current mirrored by the NMOS tube M18, the NMOS tube M18 enters a saturation region, redundant current flows through the NMOS tube M29 and is amplified and output through a current mirror formed by the PMOS tube M23 and the PMOS tube M30, according to the specific situation of differential input voltage, the rising edge swing voltage compensation current of the mirrored output can be adjusted accordingly, namely, a rising edge swing voltage compensation current can be generated in a self-adaptive manner, the PMOS tube M31 provides current limiting protection for a PMOS tube M30 current source, and the overlarge current is limited to flow through the PMOS tube M30.

Further, the falling edge slew rate enhancement module comprises a PMOS transistor M12, a PMOS transistor M13, a PMOS transistor M14, a PMOS transistor M15, an NMOS transistor M16, an NMOS transistor M17, an NMOS transistor M18, and an NMOS transistor M19;

In specific implementation, the falling edge current-limiting protection transmission circuit comprises an NMOS transistor M20 and an NMOS transistor M21, wherein a drain electrode of the NMOS transistor M21 is connected to the output terminal VOUT of the input stage amplification circuit, a source electrode of the NMOS transistor M21 is connected to a drain electrode of the NMOS transistor M20, a gate electrode of the NMOS transistor M20 is connected to the gate electrode of the NMOS transistor M19, the drain electrode of the NMOS transistor M19 and the source electrode of the NMOS transistor M17, and a source electrode of the NMOS transistor M20 is connected to the source electrode of the NMOS transistor M9, the source electrode of the NMOS transistor M10, the source electrode of the NMOS transistor M19, the source electrode of the NMOS transistor M18 and the gate electrode of the NMOS transistor M18.

The embodiment of the utility model provides an in, PMOS pipe M12 constitutes a current comparator with NMOS pipe M18, and wherein, PMOS pipe M12 image difference input current of the same kind, through NMOS pipe M18 image current that flows NMOS pipe M9 to as falling edge pressure pendulum reinforcing reference current.

In order to realize hysteresis control, the current mirrored by the PMOS transistor M12 is larger than the current mirrored by the NMOS transistor M18. When the differential input signal is small, the PMOS transistor M12 works in a linear region, the NMOS transistor M18 works in a saturation region, the gate of the PMOS transistor M13 is at a high level, and the PMOS transistor M13 is not turned on at this time, so that the falling edge slew rate enhancement module is in an off state, that is, a "non-slew" state, and at this time, a falling edge slew compensation current is not loaded to the input stage discharge circuit 1. When the differential input current corresponding to the differential input voltage is large, the input-stage operational amplification circuit 1 enters a pressure swing working state, the current mirrored by the PMOS transistor M12 is smaller than the current mirrored by the NMOS transistor M18, the NMOS transistor M18 enters a linear region, a falling edge pressure swing compensation current can be generated through the PMOS transistor M13, the PMOS transistor M15 provides current limiting protection for a PMOS transistor M13 current source, and the excessive current is limited to flow through the PMOS transistor M13. The falling edge swing compensation current is amplified by a current mirror consisting of an NMOS tube M19 and an NMOS tube M20 and then is output to an input stage amplifying circuit VOUT.

In specific implementation, when the slew rate enhancement circuit 4 includes the rising edge slew rate enhancement module and the falling edge slew rate enhancement module at the same time, the rising edge slew rate enhancement module and the falling edge slew rate enhancement module detect the differential input current at the same time.

As can be seen from the above description, the currents flowing through the PMOS transistors M3 are related to the currents flowing through the PMOS transistors M12 and M22. The quiescent operating current of the whole input stage amplifying circuit 1 is I2, and the maximum value of the differential input current is I1, so that the current I3 of the PMOS transistor M3 ranges from [ I2-I1, I2+ I1], and the quiescent operating current flowing through the NMOS transistor M9 is I9. The quiescent operating current of the input stage amplifying circuit 1 is specifically a current value when the voltages received by the differential input terminal INP and the differential input terminal INN are the same, and is specifically the same as the current value, and will not be described herein again.

According to the characteristic parameters of the PMOS transistor M22 and the characteristic parameters of the NMOS transistor M28, in operation, the current I22 flowing through the PMOS transistor M22 is a × I3, and the current I28 flowing through the NMOS transistor M28 is b × I9, that is, the reference current for increasing the rising edge pressure swing; similarly, according to the characteristic parameters of the PMOS transistor M12 and the characteristic parameters of the NMOS transistor M18, the current I12 flowing through the PMOS transistor M12 is c × I3, and the current I18 flowing through the NMOS transistor M18 is d × I9, that is, the falling edge rolling enhancement reference current; wherein, a, b, c, d are respectively related to the width-to-length ratios of the corresponding conductive channels of the PMOS transistor M22, the NMOS transistor M28, the PMOS transistor M12, and the NMOS transistor M18, which are well known to those skilled in the art and will not be described herein again.

When the differential input current is positioned between c (I2-I1) and d I9, the differential input current is in a falling edge slew rate state, and at the moment, the falling edge slew rate enhancement module is in a working state; when the differential input current is at b × I9 and a (I2+ I1), the differential input current is in a rising edge slew rate enhancement state, and at the moment, the rising edge slew rate enhancement module is in a working state; when the differential input current is between d × I9 and b × I9, the rising edge slew rate enhancement module and the falling edge slew rate enhancement module are both in a non-working state, that is, in a "non-slew" state.

Therefore, in specific implementation, by configuring specific characteristic parameters of the PMOS transistor M22, the NMOS transistor M28, the PMOS transistor M12, and the NMOS transistor M18, it can be determined that the whole input stage amplifying circuit 1 enters a falling edge slew rate enhancement state or a rising edge slew rate enhancement state, and the specific conditions are satisfied, and are not listed here.

Further, the output stage circuit 2 is adaptively connected with the input stage amplifying circuit 1, and the miller compensation circuit 3 is used for performing nested miller compensation on the input stage amplifying circuit 1 and the output stage circuit 2.

The embodiment of the utility model provides an in, output stage circuit 2 can adopt current form commonly used, specifically can select as required, generally, output stage circuit 2 can adopt the common source structure to improve whole operational amplification circuit's the output amplitude of oscillation. The nested Miller compensation can be realized through the Miller compensation circuit 3, so that the whole operational amplification circuit can be improved to have good closed-loop stability.

As shown in fig. 3, the miller compensation circuit 3 is a specific form in which the miller compensation circuit 3 is matched with the input stage amplifier circuit 1 and the output stage circuit 2, wherein the miller compensation circuit 3 includes a compensation resistor Rc connected to the output terminal of the input stage amplifier circuit 1, and the compensation resistor Rc is connected to the output terminal of the output stage circuit 2 through a compensation capacitor Cc.

As shown in fig. 1, the apparatus further includes a bias voltage generating circuit, which provides a bias voltage required by the input stage amplifying circuit 1 and the slew rate enhancement circuit 4, and includes a reference voltage circuit 6 and a bias connection circuit 5 connected to the reference voltage circuit 6, and is adaptively connected to the input stage amplifying circuit 1 and the slew rate enhancement circuit 4 through the bias connection circuit 5.

The embodiment of the utility model provides an in, reference voltage circuit 6 can adopt the current form commonly used, utilizes reference voltage circuit 6 can produce required bias voltage, can load the bias voltage that reference voltage circuit 6 produced to input stage amplifier circuit 1 and slew rate reinforcing circuit 4 in through biasing connecting circuit 5, and above-mentioned bias voltage VIBAS1, bias voltage VIBAS2, bias voltage VIBAS3 and bias voltage VIBAS4 are provided by reference voltage circuit 6 and biasing connecting circuit 5 promptly. The reference voltage circuit 6 and the bias connection circuit 5 may specifically adopt a conventional form, and the specific circuit form may be selected as needed, which is well known to those skilled in the art and will not be described herein again.

Claims

1. An operation amplifying circuit with an enhanced self-adaptive slew rate comprises an input stage amplifying circuit (1), and is characterized in that: the slew rate enhancement circuit (4) is used for enhancing the slew rate, the slew rate enhancement circuit (4) comprises a rising edge slew rate enhancement module and/or a falling edge slew rate enhancement module, and the rising edge slew rate enhancement module and the falling edge slew rate enhancement module are in adaptive electric connection with the input stage amplification circuit (1);

the input stage amplifying circuit (1) receives the loaded differential input voltage and obtains a corresponding differential input current according to the received differential input voltage; according to the differential input current, the falling edge slew rate enhancement module enters a falling edge slew rate enhancement state or the rising edge slew rate enhancement module enters a rising edge slew rate enhancement state;

when the rising edge slew rate enhancement module enters a rising edge slew rate enhancement state, the rising edge slew rate enhancement module generates an adaptive rising edge slew compensation current according to the detected differential input current, and the rising edge slew rate enhancement module loads the generated rising edge slew compensation current to the output end of the input stage amplification circuit (1);

when the falling edge slew rate enhancement module enters a falling edge slew rate enhancement state, the falling edge slew rate enhancement module detects that an adaptive falling edge slew compensation current is generated according to the detected differential input current, and the falling edge slew rate enhancement module loads the generated falling edge slew compensation current to the output end of the input stage amplification circuit (1).

2. The adaptive slew rate enhanced operational amplifier circuit of claim 1, wherein: the input stage amplifying circuit (1) comprises a differential input connecting part and a folding type cascode circuit which is in adaptive connection with the differential input connecting part, and a rising edge slew rate enhancing module and a falling edge slew rate enhancing module are in adaptive connection with the folding type cascode circuit;

3. The adaptive slew rate enhanced operational amplifier circuit of claim 2, wherein: the folded cascode circuit comprises a PMOS tube M3 and a PMOS tube M4, wherein the grid end of the PMOS tube M3 is in adaptive connection with the grid end of the PMOS tube M4, the drain end of the PMOS tube M5, the drain end of the NMOS tube M7, a rising edge slew rate enhancement module and a falling edge slew rate enhancement module;

the drain end of the PMOS tube M4 is connected with the source end of the PMOS tube M6, and the gate end of the PMOS tube M6 and the gate end of the PMOS tube M5 are both connected with a bias voltage VBIAS 2; the drain end of the PMOS tube M6 is in adaptive connection with the drain end of the NMOS tube M8, the rising edge slew rate enhancement module and the falling edge slew rate enhancement module;

the source end of the NMOS tube M8 is connected with the drain end of the NMOS tube M10 and the drain end of the PMOS tube M1, and the gate end of the NMOS tube M8 and the gate end of the NMOS tube M7 are both connected with a bias voltage VBIAS 3; the drain end of the NMOS tube M8 is in adaptive connection with the drain end of the PMOS tube M6, the rising edge slew rate enhancement module and the falling edge slew rate enhancement module to form the output end VOUT of the input stage amplification circuit (1);

4. The adaptive slew rate enhanced operational amplifier circuit of claim 3, wherein: the rising edge slew rate enhancement module comprises a PMOS tube M22, a PMOS tube M23, a PMOS tube M24, a PMOS tube M25, an NMOS tube M26, an NMOS tube M27, an NMOS tube M28 and an NMOS tube M29;

5. The adaptive slew rate enhanced operational amplifier circuit of claim 4, wherein: the rising edge current-limiting protection transmission circuit comprises a PMOS tube M30 and a PMOS tube M31, wherein a source end of the PMOS tube M30 is connected with a source end of the PMOS tube M22, a source end of the PMOS tube M23, a source end of the PMOS tube M11, a source end of the PMOS tube M3 and a source end of the PMOS tube M4, a drain end of the PMOS tube M30 is connected with a source end of the PMOS tube M31, and a grid end of the PMOS tube M30 is connected with a grid end of the PMOS tube M23, a drain end of the PMOS tube M23 and a source end of the PMOS tube M25;

6. The adaptive slew rate enhanced operational amplifier circuit of claim 3, wherein: the falling edge slew rate enhancement module comprises a PMOS tube M12, a PMOS tube M13, a PMOS tube M14, a PMOS tube M15, an NMOS tube M16, an NMOS tube M17, an NMOS tube M18 and an NMOS tube M19;

the grid end of a PMOS tube M12 is connected with the grid end of a POMS tube M3, the grid end of a PMOS tube M4, the drain end of a PMOS tube M5 and the drain end of a PMOS tube M7, and the source end of a PMOS tube M12 is connected with the source end of the PMOS tube M13, the source end of the PMOS tube M11, the source end of the PMOS tube M3 and the source end of the PMOS tube M4; the drain terminal of the PMOS tube M12 is connected with the source terminal of the PMOS tube M14, the gate terminal of the PMOS tube M13, the drain terminal of the PMOS tube M13 and the source terminal of the PMOS tube M15, the drain terminal of the PMOS tube M14 is connected with the drain terminal of the NMOS tube M16, the source terminal of the NMOS tube M16 is connected with the drain terminal of the NMOS tube M18, the drain terminal of the PMOS tube M15 is connected with the drain terminal of the NMOS tube M17, the source terminal of the NMOS tube M17 is connected with the drain terminal of the NMOS tube M19 and the gate terminal of the NMOS tube M19, and the source terminal of the NMOS tube M17 is also connected with the output terminal VOUT of the input stage amplifying circuit through a falling edge protection transmission circuit;

7. The adaptive slew rate enhanced operational amplifier circuit of claim 6, wherein: the falling edge current-limiting protection transmission circuit comprises an NMOS tube M20 and an NMOS tube M21, wherein a drain electrode of the NMOS tube M21 is connected with an output end VOUT of the input-stage amplifying circuit, a source electrode of the NMOS tube M21 is connected with a drain electrode of the NMOS tube M20, a grid electrode of the NMOS tube M20 is connected with a grid electrode of the NMOS tube M19, a drain electrode of the NMOS tube M19 and a source electrode of the NMOS tube M17, and a source electrode of the NMOS tube M20 is connected with a source electrode of the NMOS tube M9, a source electrode of the NMOS tube M10, a source electrode of the NMOS tube M19, a source electrode of the NMOS tube M18 and a grid electrode of the NMOS tube M18.

8. The adaptive slew rate enhanced operational amplifier circuit of any one of claims 1-7, wherein: the device also comprises an output stage circuit (2) which is in adaptive connection with the input stage amplifying circuit (1) and a Miller compensation circuit (3) which is used for performing nested Miller compensation on the input stage amplifying circuit (1) and the output stage circuit (2).

9. The adaptive slew rate enhanced operational amplifier circuit of claim 8, wherein: the Miller compensation circuit (3) comprises a compensation resistor Rc connected with the output end of the input stage amplification circuit (1), and the compensation resistor Rc is connected with the output end of the output stage circuit (2) through a compensation capacitor Cc.

10. The adaptive slew rate enhanced operational amplifier circuit of any one of claims 1-7, wherein: the voltage-controlled oscillator further comprises a bias voltage generating circuit, wherein the bias voltage generating circuit provides bias voltage required by the input-stage amplifying circuit (1) and the slew rate enhancing circuit (4), the bias voltage generating circuit comprises a reference voltage circuit (6) and a bias connecting circuit (5) connected with the reference voltage circuit (6), and the bias connecting circuit (5) is in adaptive connection with the input-stage amplifying circuit (1) and the slew rate enhancing circuit (4).