CN206790445U - Offset voltage eliminates circuit - Google Patents
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- CN206790445U CN206790445U CN201720739626.3U CN201720739626U CN206790445U CN 206790445 U CN206790445 U CN 206790445U CN 201720739626 U CN201720739626 U CN 201720739626U CN 206790445 U CN206790445 U CN 206790445U
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Abstract
Offset voltage eliminates circuit, belongs to integrated circuit fields, and the utility model is low to solve the problems, such as the low offset voltage of existing limiting amplifier elimination circuit precision, low-response, performance.The utility model includes Current Voltage control unit, low pass filter, Full differential operational amplifier A0, voltage comparator COMP, fine current adjustment unit and shift register；Shift register receiving voltage comparator COMP is instructed, and shift register issues control instruction with timeticks batch (-type), and when COMP outputs 1, control fine current adjustment unit opens positive branch switch and closes reverse branch switch；When COMP outputs 0, control fine current adjustment unit opens reverse branch switch and closes positive branch switch；Current Voltage control unit changes the size of output voltage under the control of fine current adjustment unit, by adjusting the size of internal forward and reverse branch current, to eliminate offset voltage.
Description
Technical field
The utility model belongs to integrated circuit fields, is related to the offset voltage adjustment technology of limiting amplifier.
Background technology
In the receiving terminal of optical-fibre communications integrated circuit, trans-impedance amplifier (TIA) is by photodiode (PD) current signal
Voltage signal is converted into, the usual size of the voltage signal is only tens millivolts.Therefore, must be installed after trans-impedance amplifier attached
The limiting amplifier added, the voltage signal that trans-impedance amplifier exports is amplified to certain logical level in order to which subsequent conditioning circuit makes
With.Design requirement for limiting amplifier is that have high-gain, low noise, the bandwidth equal with data rate, so amplitude limit
Amplifier is designed to casacade multi-amplifier cascade structure, but device easily has mismatch condition in chip manufacturing proces, so as to
It is zero and offset voltage (offset) that output voltage is not zero to produce single-stage op-amp input voltage, and the offset voltage is by multi-cascade
Limiting amplifier amplification, the voltage signal of final output is by substantial deviation correct data.So prior art is used in amplitude limit
The technological means that offset cancellation circuit is introduced in amplifier suppresses the offset voltage.
Fig. 1 gives the structure that conventional offset voltage eliminates circuit.In Fig. 1, amplifier A1 is represented in limiting amplifier
Any first stage amplifier, the amplifier exported one big due to device mismatch in the case where input voltage is zero
Small is VoffsetOffset voltage.Amplifier A2 is that feedback amplifier effect is to suppress offset voltage Voffset。
The offset voltage V of amplifier A1 outputsoffsetBy positive and negative two input for being input to feedback amplifier A2 of same phase.
Because feedback amplifier A2 normal phase input end corresponds to its reversed-phase output, therefore rise with the current potential of normal phase input end, instead
The current potential of phase output terminal will decline；Again because feedback amplifier A2 inverting input corresponds to its positive output end, therefore with
The current potential of inverting input declines, and the current potential of positive output end will rise.Final feedback amplifier A2 output voltage is inverted
Positive and negative two input for being input to amplifier A1, i.e., amplifier A1 normal phase input ends current potential decline, it is corresponding anti-phase defeated
Go out terminal potential rising；A1 anti-phase inputs terminal potential rises, and corresponding positive output end current potential declines；Final A1 completes whole
The negative-feedback of body circuit causes the potential difference of its two output end to reduce, i.e. offset voltage VoffsetReduce.
In practical application, feedback amplifier A2 gain can not be accomplished very high, therefore limit the amplification being able to detect that
Device A1 output end offset voltages VoffsetMinimum amplitude, and feedback amplifier A2 is due to the restriction of power consumption, response speed mistake
Slowly, response offset voltage V that can not be real-timeoffsetChange and make adjustment.The offset voltage of this structure eliminates circuit
High-performance limiting amplifier actual demand can not have been met.
The content of the invention
The purpose of the utility model is that the offset voltage of existing limiting amplifier elimination circuit precision is low, responds in order to solve
Slowly the problem of, performance is low, there is provided a kind of offset voltage eliminates circuit.
Offset voltage described in the utility model eliminates circuit, including current-voltage control unit, low pass filter, complete poor
Divide operational amplifier A0, voltage comparator COMP, fine current adjustment unit and shift register；
Current-voltage control unit：For receiving the homophase input voltage DIN, anti-phase of previous stage trans-impedance amplifier output
Input voltage DINB；
For after being adjusted to next stage limiting amplifier, low pass filter output with phase output voltage DOUT, anti-phase
Output voltage DOUTB；
Change the size of output voltage by adjusting the size of internal forward and reverse branch current；
Low pass filter：For the data filtering for exporting current-voltage control unit, retain direct current part；And
Voltage comparator COMP is given with mutually exporting；
Voltage comparator COMP：For being compared to the voltage of input, when same phase output voltage DOUT, anti-phase output electricity
Press DOUTB exist imbalance when, and offset voltage be more than 0 when, voltage comparator COMP output high level 1；Offset voltage is less than 0
When, voltage comparator COMP output low levels 0；
Shift register：Receiving voltage comparator COMP is instructed, and switching control instruction is sent to fine current adjustment unit；
When voltage comparator COMP exports high level 1, shift register issues switching control instruction with timeticks batch (-type), comes
Control fine current adjustment unit to open positive branch switch and close reverse branch switch；When voltage comparator COMP outputs are low
During level 0, shift register issues switching control instruction with timeticks batch (-type), to control fine current adjustment unit to open
Open reverse branch switch and close positive branch switch；
Fine current adjustment unit：The control instruction of shift register is received, when opening positive branch switch, control is just
Increase to branch current, and then control and reduce with phase output voltage DOUT；Control reverse branch current to reduce simultaneously, and then control
Reversed phase output voltage DOUTB increases；Reduce the numerical value of offset voltage by above-mentioned adjustment；Carrying out multistage identical adjustment makes imbalance
Voltage is to 0 convergence；
When opening reverse branch switch, control branch current in the same direction to reduce, and then control and increase with phase output voltage DOUT
Greatly；Control reverse branch current to increase simultaneously, and then control reversed phase output voltage DOUTB to reduce；Reduced by above-mentioned adjustment
The numerical value of offset voltage；Carrying out multistage identical adjustment makes offset voltage to 0 convergence；
Offset voltage is finally adjusted to 0 or so dynamic equilibrium and exported to next stage.
Preferably, current-voltage control unit includes NPN transistor Q3, NPN transistor Q4, resistance R1 and resistance R2；
NPN transistor Q3 base stage is connected with NPN transistor Q4 base stage, and accesses bias voltage VB；
NPN transistor Q3 colelctor electrode passes through resistance R1 connection dc sources VDD；
NPN transistor Q4 colelctor electrode passes through resistance R2 connection dc sources VDD；
NPN transistor Q3 emitter stage is grounded by the positive branch switch in fine current adjustment unit；
NPN transistor Q4 emitter stage is grounded by the reverse branch switch in fine current adjustment unit；
Resistance R1 and resistance R2 resistance are equal；
NPN transistor Q3 colelctor electrode and resistance R1 common node X are exported with phase output voltage DOUT, common node X
NPN transistor Q1 colelctor electrode is also connected with, NPN transistor Q1 base stage accesses homophase input voltage DIN by electric capacity C1；
NPN transistor Q4 colelctor electrode and resistance R2 common node Y outputs reversed phase output voltage DOUTB, common node Y
NPN transistor Q2 colelctor electrode is also connected with, NPN transistor Q2 base stage accesses reverse inter-input-ing voltage DINB by electric capacity C2；
NPN transistor Q1 emitter stage and NPN transistor Q2 emitter stage are grounded commonly through current source I0.
Preferably, low pass filter includes resistance R3, resistance R4 and electric capacity C3；Resistance R3 one end connection common node X,
The resistance R3 other end connects electric capacity C3 one end and Full differential operational amplifier A0 in-phase input end simultaneously；The one of resistance R4
End connection common node Y, the resistance R4 other end connect simultaneously electric capacity C3 the other end and Full differential operational amplifier A0 it is anti-
Phase input.
Preferably, fine current adjustment unit includes n positive branch switch MN1, MN3, MN5 ..., and MN2n-1, n anti-
To branch switch MN2, MN4, MN6 ..., MN2n and n current source I1, I2 ..., In；N is the positive integer more than or equal to 2；
N positive branch switch are in parallel, and the drain electrode of n positive branch switch connects NPN transistor Q3 transmitting simultaneously
Pole, the anode of the source electrode of n positive branch switch respectively with n current source I1, I2 ..., In connect one to one；
N reversely branch switch parallel connections, and the drain electrode of n reverse branch switch connects NPN transistor Q4 transmitting simultaneously
Pole, the anode of the source electrode of the reverse branch switch of n respectively with n current source I1, I2 ..., In connect one to one；
N current source I1, I2 ..., In negative terminal meets GND.
Preferably, shift register is made up of n d type flip flop D1, D2 ... Dn cascade, d type flip flop D1 D ends and voltage
Comparator COMP output end connection；
The Q ends of previous d type flip flop are connected with the D ends of next d type flip flop；
The CP ends incoming clock signal CLK of n d type flip flop；
The Q ends of n d type flip flop and the grid of n positive branch switch connect one to one respectively；
N d type flip flopThe grid with n reverse branch switch is held to connect one to one respectively.
The beneficial effects of the utility model：The utility model proposes a kind of high-precision offset voltage to eliminate circuit, abandons
Existing offset voltage eliminates the feedback amplifier network in circuit and changes detection, adjustment offset voltage VoffsetMode, improve
Offset voltage eliminate circuit to the accuracy of detection of offset voltage, shorten the response time and have already been through simulation results show.
Brief description of the drawings
Fig. 1 is that offset voltage eliminates schematic diagram in the prior art；
Fig. 2 is the theory diagram that offset voltage described in the utility model eliminates circuit；
Fig. 3 is the physical circuit figure that offset voltage described in the utility model eliminates circuit.
Embodiment
Embodiment of the present utility model is described in detail below with reference to drawings and Examples, whereby to the utility model
How application technology means solve technical problem, and the implementation process for reaching technique effect can fully understand and implement according to this.
The utility model proposes high-precision offset voltage eliminate circuit abandon traditional offset voltage eliminate it is anti-in circuit
Amplifier is presented, d type flip flop is used instead and coordinates clock pulses, adjust the number of the size of offset voltage, d type flip flop and differential pair tube in real time
Amount is more more more offset voltage can be caused closer to zero；Clock frequency is improved, the adjustment to offset voltage can be completed faster.Most
Whole limiting amplifier is improved in performance.
One embodiment：Referring to Fig. 3, offset voltage described in the utility model, which eliminates circuit, includes fully differential operation amplifier
Device A0, voltage comparator COMP, n d type flip flops D1, D2 ... Q4, n Dn, NPN transistor Q3, NPN transistor positive branch roads
MN1, MN3, MN5 are switched ..., MN2n-1, n reverse branch switch MN2, MN4, MN6 ..., MN2n, n current source I1,
I2 ..., In, resistance R1~R4, electric capacity C3；
NPN transistor Q3 colelctor electrode passes through resistance R1 connection dc sources VDD；
NPN transistor Q4 colelctor electrode passes through resistance R2 connection dc sources VDD；
NPN transistor Q3 emitter stage by n in parallel positive branch switch MN1, MN3, MN5 ..., MN2n-1 connects
Ground；
NPN transistor Q4 emitter stage by n in parallel reverse branch switch MN2, MN4, MN6 ..., MN2n ground connection；
Resistance R1 and resistance R2 resistance are equal；
NPN transistor Q3 colelctor electrode and resistance R1 common node X are exported with phase output voltage DOUT, common node X
NPN transistor Q1 colelctor electrode is also connected with, NPN transistor Q1 base stage accesses homophase input voltage DIN by electric capacity C1；
NPN transistor Q4 colelctor electrode and resistance R2 common node Y outputs reversed phase output voltage DOUTB, common node Y
NPN transistor Q2 colelctor electrode is also connected with, NPN transistor Q2 base stage accesses reverse inter-input-ing voltage DINB by electric capacity C2；
NPN transistor Q1 emitter stage and NPN transistor Q2 emitter stage are grounded commonly through current source I0.
Resistance R3 one end connection common node X, resistance the R3 other end connect electric capacity C3 one end and fully differential simultaneously
The in-phase input end of operational amplifier A 0；Resistance R4 one end connection common node Y, resistance the R4 other end connect electric capacity simultaneously
The C3 other end and Full differential operational amplifier A0 inverting input.
N positive branch switch are in parallel, and the drain electrode of n positive branch switch connects NPN transistor Q3 transmitting simultaneously
Pole, the anode of the source electrode of n positive branch switch respectively with n current source I1, I2 ..., In connect one to one；
N reversely branch switch parallel connections, and the drain electrode of n reverse branch switch connects NPN transistor Q4 transmitting simultaneously
Pole, the anode of the source electrode of the reverse branch switch of n respectively with n current source I1, I2 ..., In connect one to one；
N current source I1, I2 ..., In negative terminal meets GND.
N d type flip flop D1, D2 ... Dn cascade, d type flip flop D1 D ends are connected with voltage comparator COMP output end；
The Q ends of previous d type flip flop are connected with the D ends of next d type flip flop；
The CP ends incoming clock signal CLK of n d type flip flop；
The Q ends of n d type flip flop and the grid of n positive branch switch connect one to one respectively；
N d type flip flopThe grid with n reverse branch switch is held to connect one to one respectively.
In illustrating that conventional offset voltage eliminates circuit, due to having used feedback amplifier in circuit to offset voltage
VoffsetDetection amplification, the offset voltage minimum amplitude being able to detect that during this is limited, and adjustment time is long.Fig. 2
A kind of high-precision offset voltage proposed eliminates circuit, solves conventional offset voltage and eliminates circuit feedback amplifier
The situation that the accuracy of detection brought is low, adjustment time is long.
The Q ends of n d type flip flop are as signal wire G1, G3, G5 ..., G2n-1, to connect n positive branch switch respectively
MN1, MN3, MN5 ..., MN2n-1 grid；N d type flip flopEnd is as signal wire G2, G4, G6 ..., G2n, to distinguish
N reversely branch switch MN2, MN4, MN6 are connected ..., MN2n grid；
Assume initially that the original state of d type flip flop：G1, G3, G5 are until G2n-1 signal wire zero setting；G2, G4, G6 are until G2n
Signal wire puts 1.
X point voltages can be expressed as：
VX=VDD-Ib1R1 (1)
Ib1For NPN transistor Q3 branch currents, and it is used as positive branch current.
Y point voltages can be expressed as：
VY=VDD-Ib2R2 (2)
Ib2For NPN transistor Q4 branch currents, and it is used as reverse branch current.
Due to the mismatch of device, i.e. X points and Y points voltage difference are imbalance between two output ends DOUT, DOUTB of amplifier
Voltage Voffset。
As offset voltage VoffsetIn the presence of i.e. VX＞ VY, Ib1＜ Ib2, what the voltage difference of X and Y points was made up of R3, R4, C3
Low pass filter filters out high fdrequency component, and DC component is amplified by fully-differential amplifier A0 certain amplitude, the same phase of output signal
Be input to voltage comparator COMP, voltage comparator COMP will export high level 1.D type flip flop D1 D ends put 1, when clock is believed
Number it is high level 1, d type flip flop D1 Q ends put 1, and connected nmos pass transistor MN1 grid ends are high potential, and are opened, and are led
Cause positive branch current Ib1Increase, according to formula (1), X points voltage declines, i.e., declines with phase output voltage DOUT；D type flip flop D1
'sHold as low level 0, connected nmos pass transistor MN2 grid end is low potential, and is turned off, and causes reverse branch road electricity
Flow Ib2Reduce, according to formula (2), Y points voltage rises, i.e. reversed phase output voltage DOUTB rises.When clock signal transitions are low electricity
Flat, all d type flip flop output states will keep constant.By the adjustment of first d type flip flop, X point voltages and Y point voltages
Difference reduces, i.e. offset voltage VoffsetReduce.Now X points voltage is still more than Y point voltages, is height in next clock signal
Level 1, d type flip flop D2 D ends are high level 1, and Q ends are high level 1, and connected nmos pass transistor MN3 grid end is height
Current potential, and open, cause positive branch current Ib1Further increase, according to formula (1), X point voltages further decline, i.e., same
Phase output voltage DOUT further declines；D type flip flop D2'sHold as low level, connected nmos pass transistor MN4 grid
Hold as low potential, and turn off, cause anti-road branch current Ib2Further reduce, according to formula (2), Y points voltage further on
Rise, i.e. reversed phase output voltage DOUTB is further up.When clock signal transitions are low level, all d type flip flop output states
It will keep constant.By the adjustment of second d type flip flop, the difference of X point voltages and Y point voltages further reduces, i.e. imbalance electricity
Press VoffsetFurther reduce.Appeal process will be with clock signal and constantly carry out, until X point voltages and Y point voltages are infinitely forced
It is near equal.
If while X point voltages infinitely approach equal with Y point voltages, there is V in circuitX＜ VYSituation when, voltage ratio
Low level 0 will be exported compared with device CMOP, when clock signal is high level 1, d type flip flop D1 D ends are low level, connected
Nmos pass transistor MN1 grid end is low potential, and is turned off, and causes positive branch current Ib1Reduce, according to formula (1), X points electricity
Pressure rises, i.e., rises with phase output voltage DOUT；D type flip flop D1'sHold as high level, connected nmos pass transistor MN2
Grid end be high potential, and open, cause reverse branch current Ib2Increase, according to formula (2), Y points voltage declines, i.e., anti-phase
Output voltage DOUTB declines.When clock signal transitions are low level, all d type flip flop output states will keep last defeated
Go out result.It is gradually reduced by the difference of the adjustment X point voltages and Y point voltages of d type flip flop, appeal process will be with clock letter
Number constantly carry out so that X point voltages and Y point voltage differences (i.e. offset voltage) are in 0 or so dynamic equilibrium.After eliminating offset voltage
Export again and give next stage limiting amplifier.
Based on above-mentioned analysis, it is seen that the present embodiment offset voltage, which eliminates circuit, can bring following beneficial effect：This practicality is new
Type coordinates clock pulses using d type flip flop, adjusts the size of offset voltage in real time, makes it in 0 or so dynamic equilibrium, d type flip flop
Cascade quantity and forward and reverse branch road switching tube quantity it is more, Adjustment precision is higher, and clock frequency is higher, regulates the speed more
It hurry up.Using the utility model circuit limiting amplifier is improved in performance.
Although the embodiment disclosed by the utility model is as above, described content is only to facilitate understand this practicality
New and use embodiment, is not limited to the utility model.Skill in any the utility model art
Art personnel, can be in the formal and details of implementation on the premise of the spirit and scope disclosed by the utility model are not departed from
On make any modification and change, but scope of patent protection of the present utility model, must still be defined with appended claims
Scope be defined.
Claims (5)
1. offset voltage eliminate circuit, it is characterised in that including current-voltage control unit (100), low pass filter (101),
Full differential operational amplifier A0, voltage comparator COMP, fine current adjustment unit (102) and shift register (103)；
Current-voltage control unit (100)：For receiving the homophase input voltage DIN, anti-phase of previous stage trans-impedance amplifier output
Input voltage DINB；
For after being adjusted to next stage limiting amplifier, low pass filter (101) output with phase output voltage DOUT, anti-phase
Output voltage DOUTB；
Change the size of output voltage by adjusting the size of internal forward and reverse branch current；
Low pass filter (101)：For the data filtering for exporting current-voltage control unit (100), retain direct current splenium
Point；And give voltage comparator COMP with mutually exporting；
Voltage comparator COMP：For being compared to the voltage of input, when same phase output voltage DOUT, reversed phase output voltage
DOUTB exist imbalance when, and offset voltage be more than 0 when, voltage comparator COMP output high level 1；When offset voltage is less than 0,
Voltage comparator COMP exports low level 0；
Shift register (103)：Receiving voltage comparator COMP is instructed, and switch control is sent to fine current adjustment unit (102)
System instruction；When voltage comparator COMP exports high level 1, shift register (103) is opened with the issue of timeticks batch (-type)
Control instruction is closed, to control fine current adjustment unit (102) to open positive branch switch and close reverse branch switch；Work as electricity
When pressing comparator COMP output low levels 0, shift register (103) issues switching control instruction with timeticks batch (-type),
To control fine current adjustment unit (102) to open reverse branch switch and close positive branch switch；
Fine current adjustment unit (102)：The control instruction of shift register (103) is received, when opening positive branch switch,
Control positive branch current to increase, and then control and reduce with phase output voltage DOUT；Control reverse branch current to reduce simultaneously, enter
And reversed phase output voltage DOUTB is controlled to increase；Reduce the numerical value of offset voltage by above-mentioned adjustment；Carry out multistage identical adjustment
Make offset voltage to 0 convergence；
When opening reverse branch switch, control branch current in the same direction to reduce, and then control and increase with phase output voltage DOUT；Together
When control reverse branch current to increase, and then control reversed phase output voltage DOUTB to reduce；Imbalance electricity is reduced by above-mentioned adjustment
The numerical value of pressure；Carrying out multistage identical adjustment makes offset voltage to 0 convergence；
Offset voltage is finally adjusted to 0 or so dynamic equilibrium and exported to next stage.
2. offset voltage eliminates circuit according to claim 1, it is characterised in that current-voltage control unit (100) includes
NPN transistor Q3, NPN transistor Q4, resistance R1 and resistance R2；NPN transistor Q3 base stage and NPN transistor Q4 base stage phase
Even, and bias voltage VB is accessed；
NPN transistor Q3 colelctor electrode passes through resistance R1 connection dc sources VDD；
NPN transistor Q4 colelctor electrode passes through resistance R2 connection dc sources VDD；
NPN transistor Q3 emitter stage is grounded by the positive branch switch in fine current adjustment unit (102)；
NPN transistor Q4 emitter stage is grounded by the reverse branch switch in fine current adjustment unit (102)；
Resistance R1 and resistance R2 resistance are equal；
NPN transistor Q3 colelctor electrode and resistance R1 common node X outputs also connect with phase output voltage DOUT, common node X
NPN transistor Q1 colelctor electrode is connect, NPN transistor Q1 base stage accesses homophase input voltage DIN by electric capacity C1；
NPN transistor Q4 colelctor electrode and resistance R2 common node Y export reversed phase output voltage DOUTB, and common node Y also connects
NPN transistor Q2 colelctor electrode is connect, NPN transistor Q2 base stage accesses reverse inter-input-ing voltage DINB by electric capacity C2；
NPN transistor Q1 emitter stage and NPN transistor Q2 emitter stage are grounded commonly through current source I0.
3. according to claim 2 offset voltage eliminate circuit, it is characterised in that low pass filter (101) include resistance R3,
Resistance R4 and electric capacity C3；Resistance R3 one end connection common node X, the resistance R3 other end connect simultaneously electric capacity C3 one end and
Full differential operational amplifier A0 in-phase input end；Resistance R4 one end connection common node Y, the resistance R4 other end connect simultaneously
Connect the electric capacity C3 other end and Full differential operational amplifier A0 inverting input.
4. offset voltage eliminates circuit according to claim 2, it is characterised in that fine current adjustment unit (102) includes n
Individual positive branch switch MN1, MN3, MN5 ..., MN2n-1, n reverse branch switch MN2, MN4, MN6 ..., MN2n and n electricity
Stream source I1, I2 ..., In；N is the positive integer more than or equal to 2；
N positive branch switch are in parallel, and the drain electrode of n positive branch switch connects NPN transistor Q3 emitter stage, n simultaneously
The source electrode of individual positive branch switch respectively with n current source I1, I2 ..., In anode connects one to one；
N reversely branch switch parallel connections, and the drain electrode of n reverse branch switch connects NPN transistor Q4 emitter stage, n simultaneously
It is individual reversely branch switch source electrode respectively with n current source I1, I2 ..., In anode connects one to one；
N current source I1, I2 ..., In negative terminal meets GND.
5. offset voltage eliminates circuit according to claim 4, it is characterised in that shift register (103) is triggered by n D
Device D1, D2 ... Dn cascades are formed, and d type flip flop D1 D ends are connected with voltage comparator COMP output end；
The Q ends of previous d type flip flop are connected with the D ends of next d type flip flop；
The CP ends incoming clock signal CLK of n d type flip flop；
The Q ends of n d type flip flop and the grid of n positive branch switch connect one to one respectively；
N d type flip flopThe grid with n reverse branch switch is held to connect one to one respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720739626.3U CN206790445U (en) | 2017-06-23 | 2017-06-23 | Offset voltage eliminates circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720739626.3U CN206790445U (en) | 2017-06-23 | 2017-06-23 | Offset voltage eliminates circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206790445U true CN206790445U (en) | 2017-12-22 |
Family
ID=60717961
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720739626.3U Withdrawn - After Issue CN206790445U (en) | 2017-06-23 | 2017-06-23 | Offset voltage eliminates circuit |
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| Country | Link |
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| CN (1) | CN206790445U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108462400A (en) * | 2018-03-01 | 2018-08-28 | 芯海科技（深圳）股份有限公司 | A kind of full wave rectified signal generation circuit of adaptive deadband eliminating |
| CN110266314A (en) * | 2019-07-25 | 2019-09-20 | 中北大学 | A kind of concentration sequence generator |
-
2017
- 2017-06-23 CN CN201720739626.3U patent/CN206790445U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108462400A (en) * | 2018-03-01 | 2018-08-28 | 芯海科技（深圳）股份有限公司 | A kind of full wave rectified signal generation circuit of adaptive deadband eliminating |
| CN108462400B (en) * | 2018-03-01 | 2024-04-26 | 芯海科技（深圳）股份有限公司 | Full-wave rectification signal generating circuit capable of adaptively eliminating dead zone |
| CN110266314A (en) * | 2019-07-25 | 2019-09-20 | 中北大学 | A kind of concentration sequence generator |
| CN110266314B (en) * | 2019-07-25 | 2022-10-04 | 中北大学 | Centralized sequence generator |
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