CN117573584A - DAC device supporting DMA request and processing method thereof - Google Patents

DAC device supporting DMA request and processing method thereof Download PDF

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Publication number
CN117573584A
CN117573584A CN202311525799.1A CN202311525799A CN117573584A CN 117573584 A CN117573584 A CN 117573584A CN 202311525799 A CN202311525799 A CN 202311525799A CN 117573584 A CN117573584 A CN 117573584A
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CN
China
Prior art keywords
dac
module
dma
fifo buffer
digital
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Pending
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CN202311525799.1A
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Chinese (zh)
Inventor
孙佳伟
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Praran Semiconductor Shanghai Co ltd
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Praran Semiconductor Shanghai Co ltd
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Priority to CN202311525799.1A priority Critical patent/CN117573584A/en
Publication of CN117573584A publication Critical patent/CN117573584A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

The invention discloses a DAC device supporting DMA request, comprising: the device comprises a FIFO buffer module, a DAC digital module and a DAC analog module. The input end of the FIFO buffer module is connected with the DMA module and is used for buffering the DMA data transmitted by the DMA module. The output end of the FIFO buffer module is connected with the input end of the DAC digital module and is used for transmitting the buffered DMA data to the DAC digital module. The output end of the DAC digital module is connected with the DAC analog module. The invention also discloses a processing method of the DAC device supporting the DMA request. The invention can realize the buffer of DMA data, thereby realizing continuous DMA request and improving DAC processing rate.

Description

DAC device supporting DMA request and processing method thereof
Technical Field
The present invention relates to the field of semiconductor integrated circuits, and more particularly to a digital-to-analog converter (DAC) device supporting direct memory access (direct memory access, DMA) requests. The invention also relates to a method for processing the DAC device supporting the DMA request.
Background
As shown in fig. 1, a block diagram of a DAC device supporting a DMA request in the prior art; existing DAC devices supporting DMA requests include: a DAC digital module 102 and a DAC analog module 103. In fig. 1, DAC digital module 102 is also denoted dac_dig, and DAC analog module 103 is also denoted dac_ana.
The output of DMA module 104 is directly connected to the input of DAC digital module 102.
The output end of the DAC digital module 102 is connected with the DAC analog module 103. The DAC analog module 103 performs digital-to-analog conversion according to the digital signal output from the DAC digital module 102 and outputs an analog signal.
It can be seen that the DMA functions of existing DACs do not require buffering. If the DMA module 104 does not complete the last request, the next request will not be processed, and the DAC processes: either no request is issued and a flag bit is set that cannot be processed by a DMA module 104, or the DMA module 104 ignores the request, which slows down the DMA processing of the DAC and reduces the DAC processing rate.
Disclosure of Invention
The invention aims to provide a DAC device supporting DMA requests, which can realize the buffering of DMA data, thereby realizing continuous DMA requests and improving the DAC processing rate. To this end, the invention also provides a method for processing DAC devices supporting DMA requests.
To this end, the DAC device supporting DMA requests provided by the present invention includes: a first-in first-out (first input first output, FIFO) buffer module, a DAC digital module, and a DAC analog module.
The input end of the FIFO buffer module is connected with the DMA module and is used for buffering the DMA data transmitted by the DMA module.
The output end of the FIFO buffer module is connected with the input end of the DAC digital module and is used for transmitting the buffered DMA data to the DAC digital module.
And the output end of the DAC digital module is connected with the DAC analog module.
A further improvement is that the DMA data that can be buffered by the FIFO buffer module is larger than one set.
In a further improvement, a first flag bit is set in the DAC, and the first flag bit is a DMA data underrun (DMA underrun) flag bit.
And when the FIFO buffer module is not full, setting the first flag bit, and continuing to work by the DMA module.
And when the FIFO buffer module is filled, the DAC stops sending out the request after the data of the first zone bit is switched.
The DAC analog module realizes digital-to-analog conversion according to the digital signal output by the DAC digital module and outputs an analog signal.
In a further improvement, the DMA module transfers the DMA data to the FIFO buffer module according to the request sent by the DAC.
In order to solve the above technical problems, in a method for processing a DAC device supporting a DMA request, the DAC includes: the device comprises a FIFO buffer module, a DAC digital module and a DAC analog module.
The input end of the FIFO buffer module is connected with the DMA module and is used for buffering the DMA data transmitted by the DMA module.
The output end of the FIFO buffer module is connected with the input end of the DAC digital module and is used for transmitting the buffered DMA data to the DAC digital module.
And the output end of the DAC digital module is connected with the DAC analog module.
The DAC processing steps include:
the DMA module transmits DMA data to the FIFO buffer module for buffering;
the FIFO buffer module transmits the buffered DMA data to the DAC digital module.
The DAC digital module outputs digital signals to the DAC analog module for digital-to-analog conversion.
A further improvement is that the DMA data that can be buffered by the FIFO buffer module is larger than one set.
The DAC is further improved in that a first flag bit is arranged in the DAC, and the first flag bit is a DMA data underload flag bit.
And when the FIFO buffer module is not full, setting the first flag bit, and continuing to work by the DMA module.
And when the FIFO buffer module is filled, the DAC stops sending out the request after the data of the first zone bit is switched.
A further improvement is that the output end of the DAC analog module outputs an analog signal.
In a further improvement, the DMA module transfers the DMA data to the FIFO buffer module according to the request sent by the DAC.
The invention adds the FIFO buffer module at the input end of the DAC device, thereby realizing the buffer of DMA data, realizing continuous DMA request and improving the DAC processing rate.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a block diagram of a prior art DAC device supporting DMA requests;
fig. 2 is a block diagram of a DAC device supporting DMA requests according to an embodiment of the invention.
Detailed Description
FIG. 2 is a block diagram of a DAC device supporting DMA requests according to an embodiment of the present invention; the DAC device supporting the DMA request according to the embodiment of the invention comprises: FIFO buffer module 205, DAC digital module 202, and DAC analog module 203. In fig. 2, DAC digital module 202 is also represented by dac_dig, and DAC analog module 203 is also represented by dac_ana.
The input end of the FIFO buffer module 205 is connected to the DMA module 204 and is used for buffering DMA data transmitted from the DMA module 204.
The DMA module 204 generally includes a DMA controller and a plurality of DMA channels that enable direct transfer between peripherals and memory without processing by the CPU. In the embodiment of the present invention, the DAC device is used as a peripheral and the memory, and is transferred between the peripheral and the memory through a DMA channel, and the DMA module 204 and the DAC device are often connected through an APB bus.
The output end of the FIFO buffer module 205 is connected to the input end of the DAC digital module 202, and is used for transmitting the buffered DMA data to the DAC digital module 202.
The DAC digital module 202 is configured to receive data that needs to be analog-to-digital converted, and typically uses registers to receive the data. The type of data to be input is different depending on the application of the DAC device, for example, the DAC device can be applied to an audio system, and the input data is a digital audio signal. When DMA transmission is performed, the DAC device may send a request, and the DMA module 204 processes and implements DMA transmission according to the received request, and in the embodiment of the present invention, the FIFO buffer module 205 is provided, so that sequential transmission of a plurality of DMA data can be implemented before the FIFO buffer module 205 is full, thereby supporting DMA request buffering and improving data transmission efficiency.
The output end of the DAC digital module 202 is connected with the DAC analog module 203.
The DAC analog module 203 performs digital-to-analog conversion according to the digital signal output from the DAC digital module 202 and outputs an analog signal.
The digital signal input by the DAC analog module 203 can have a bit number of 8 bits or more than 12 bits, and each bit of data of the digital signal controls the resistance of the corresponding weight bit through the corresponding switch, so as to realize accurate control of the analog signal.
The analog signals output by the DAC analog module 203 include voltage signals or current signals, and the analog signals further perform corresponding functions on driving of subsequent components, for example: in some applications, the analog signal can drive a speaker or headphones to enable output of an audio signal; in some applications, the analog signal can drive a motor to effect control of the motion of the motor.
In the embodiment of the present invention, the FIFO buffer module 205 can buffer more than one set of DMA data.
The DAC device 201 is provided with a first flag bit, where the first flag bit is a DMA data underrun flag bit.
When the FIFO buffer module 205 is not full, the first flag is set and the DMA module 204 continues to operate. When the FIFO buffer module 205 is full, the data of the first flag bit is switched, and the DAC device 201 stops issuing requests.
In the embodiment of the present invention, the DMA module 204 transfers the DMA data to the FIFO buffer module 205 according to the request sent by the DAC device 201. At the request of the DAC device 201, the DMA module 204 continues to transfer DMA data to the FIFO buffer module 205 until the FIFO buffer module 205 is full.
According to the embodiment of the invention, the FIFO buffer module 205 is added at the input end of the DAC device 201, so that the buffer of DMA data can be realized, the continuous DMA request can be realized, and the processing rate of the DAC device 201 is improved.
In the method for processing a DAC device supporting a DMA request according to the embodiment of the invention, the DAC device 201 includes: FIFO buffer module 205, DAC digital module 202, and DAC analog module 203.
The input end of the FIFO buffer module 205 is connected to the DMA module 204 and is used for buffering DMA data transmitted from the DMA module 204.
The DMA module 204 generally includes a DMA controller and a plurality of DMA channels that enable direct transfer between peripherals and memory without processing by the CPU. In the embodiment of the present invention, the DAC device is used as a peripheral and the memory, and is transferred between the peripheral and the memory through a DMA channel, and the DMA module 204 and the DAC device are often connected through an APB bus.
The output end of the FIFO buffer module 205 is connected to the input end of the DAC digital module 202, and is used for transmitting the buffered DMA data to the DAC digital module 202.
The DAC digital module 202 is configured to receive data that needs to be analog-to-digital converted, and typically uses registers to receive the data. The type of data to be input is different depending on the application of the DAC device, for example, the DAC device can be applied to an audio system, and the input data is a digital audio signal. When DMA transmission is performed, the DAC device may send a request, and the DMA module 204 processes and implements DMA transmission according to the received request, and in the embodiment of the present invention, the FIFO buffer module 205 is provided, so that sequential transmission of a plurality of DMA data can be implemented before the FIFO buffer module 205 is full, thereby supporting DMA request buffering and improving data transmission efficiency.
The output end of the DAC digital module 202 is connected with the DAC analog module 203.
The DAC device 201 includes the processing steps of:
the DMA module 204 transfers DMA data to the FIFO buffer module 205 for buffering.
In the method of the embodiment of the present invention, the FIFO buffer module 205 can buffer more than one set of DMA data.
The DAC device 201 is provided with a first flag bit, where the first flag bit is a DMA data underrun flag bit.
The DMA module 204 transfers the DMA data to the FIFO buffer module 205 according to a request issued by the DAC device 201.
When the FIFO buffer module 205 is not full, the first flag is set and the DMA module 204 continues to operate.
When the FIFO buffer module 205 is full, the data of the first flag bit is switched, and the DAC device 201 stops issuing requests.
The FIFO buffer module 205 transfers the buffered DMA data into the DAC digital module 202.
The DAC digital module 202 outputs a digital signal to the DAC analog module 203 for digital-to-analog conversion. The output end of the DAC analog module 203 outputs an analog signal.
The digital signal input by the DAC analog module 203 can have a bit number of 8 bits or more than 12 bits, and each bit of data of the digital signal controls the resistance of the corresponding weight bit through the corresponding switch, so as to realize accurate control of the analog signal.
The analog signals output by the DAC analog module 203 include voltage signals or current signals, and the analog signals further perform corresponding functions on driving of subsequent components, for example: in some applications, the analog signal can drive a speaker or headphones to enable output of an audio signal; in some applications, the analog signal can drive a motor to effect control of the motion of the motor.
In the method of the embodiment of the present invention, a FIFO buffer module 205 is added to the DAC, so that the data of the DMA module 204 is sequentially processed after passing through the FIFO buffer module 205. If more than one set of data is present in the FIFO buffer 205, the flag bit of DMA outstanding is set, but the DMA module 204 may continue to operate until the FIFO buffer 205 is full. If the FIFO buffer module 205 is full, the DAC will not issue a request.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims (10)

1. A DAC device for supporting DMA requests, comprising: the device comprises a FIFO buffer module, a DAC digital module and a DAC analog module;
the input end of the FIFO buffer module is connected with the DMA module and is used for buffering the DMA data transmitted by the DMA module;
the output end of the FIFO buffer module is connected with the input end of the DAC digital module and is used for transmitting the buffered DMA data to the DAC digital module;
and the output end of the DAC digital module is connected with the DAC analog module.
2. The DAC device supporting DMA requests of claim 1 wherein: the DMA data which can be buffered by the FIFO buffer module is larger than one group.
3. The DAC device supporting DMA requests of claim 2 wherein: a first flag bit is arranged in the DAC, and the first flag bit is a DMA data underload flag bit;
when the FIFO buffer module is not full, the first flag bit is set, and the DMA module continues to work;
and when the FIFO buffer module is filled, the DAC stops sending out the request after the data of the first zone bit is switched.
4. The DAC device supporting DMA requests of claim 1 wherein: and the DAC analog module realizes digital-to-analog conversion according to the digital signal output by the DAC digital module and outputs an analog signal.
5. A DAC device supporting DMA requests as claimed in claim 3, characterized by: and the DMA module transmits the DMA data to the FIFO buffer module according to the request sent by the DAC.
6. A method of processing a DAC device supporting a DMA request, the DAC comprising: the device comprises a FIFO buffer module, a DAC digital module and a DAC analog module;
the DAC processing steps include:
the DMA module transmits DMA data to the FIFO buffer module for buffering;
the FIFO buffer module transmits the buffered DMA data to the DAC digital module;
the DAC digital module outputs digital signals to the DAC analog module for digital-to-analog conversion.
7. The method of processing a DAC apparatus for supporting a DMA request according to claim 6, wherein: the DMA data which can be buffered by the FIFO buffer module is larger than one group.
8. The DAC apparatus for supporting DMA requests of claim 7 wherein: a first flag bit is arranged in the DAC, and the first flag bit is a DMA data underload flag bit;
when the FIFO buffer module is not full, the first flag bit is set, and the DMA module continues to work;
and when the FIFO buffer module is filled, the DAC stops sending out the request after the data of the first zone bit is switched.
9. The DAC apparatus for supporting DMA requests of claim 6 wherein: and the output end of the DAC analog module outputs an analog signal.
10. The DAC apparatus for supporting DMA requests of claim 8 wherein: and the DMA module transmits the DMA data to the FIFO buffer module according to the request sent by the DAC.
CN202311525799.1A 2023-11-15 2023-11-15 DAC device supporting DMA request and processing method thereof Pending CN117573584A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311525799.1A CN117573584A (en) 2023-11-15 2023-11-15 DAC device supporting DMA request and processing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311525799.1A CN117573584A (en) 2023-11-15 2023-11-15 DAC device supporting DMA request and processing method thereof

Publications (1)

Publication Number Publication Date
CN117573584A true CN117573584A (en) 2024-02-20

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311525799.1A Pending CN117573584A (en) 2023-11-15 2023-11-15 DAC device supporting DMA request and processing method thereof

Country Status (1)

Country Link
CN (1) CN117573584A (en)

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