SU1730634A1 - Controller of load of multiprocessor system switching environment - Google Patents

Abstract

The invention relates to computing and can be applied in the construction of the switching environment of multi-processor computers. The aim of the invention is to improve the performance of the switching network by controlling the load on the network. The device contains a group of switching units 1, a group of terminating resistors 2. Each switching unit 1 has an input 3 requests, an output 4 of confirmation, an input 5 of the processor module, information input 6. an output 7 of the processor module, information output 8, an analog output A, output B of load control the processor module and the output C of the voltage reference. 4 il.

Description

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The invention relates to computing and can be applied in the construction of the switching environment of multiprocessor computers.

The purpose of the invention is to improve the performance of the switching network by controlling the network load.

FIG. 1 shows a functional diagram of the device; in fig. 2 - functional circuit of the switching unit; in fig. 3 is a diagram of the input interface and switch; in fig. 4 - algorithm of operation of the firmware.

The device contains a group of switching units 1 and a group of terminating resistors 2.

Each switching unit 1 has a request 3 input, a confirmation 4 output, a processor module output 5, information input 6, processor module input 7, information output 8, analog output A, processor control load output B, and a reference voltage input C .

Each switching unit 1 contains the first 9, second 10i and third 102 interfaces, switch 11, first 12, second 13i and third 132 buffer registers, first 141 and second 142 and third 15 digital-to-analog converters (DAC) and analogue comparator 16.

Each interface consists of an address decoder 17 and a control unit 18.

The switch 11 contains the key 19, the arbiter of 20 output channels, the register 21 and the group of elements OR 22,

The transfer of information between the PM of the multiplexer is carried out using packets. The package consists of an operating and address part. The address part is the address code of the PM receiver. Consider, for example, packet transmission in the most topologically simple switching environment, which is a process matrix. The packets are moved in the vertical and horizontal directions, at the beginning, for example, horizontally, until they coincide with the column to which the PM receiver of the packet belongs, then vertically until they coincide with the PM receiver.

Consider the transfer of packets between network nodes. A packet from the output of the buffer register 13 of the source node enters the interface 10 of the receiver node and is written to the input 21 register of the receiver node. The exchange protocol between nodes is asynchronous on the principle of request-confirmation.

To describe the algorithms, the following notation is adopted: RQin - source request for information output

(inverted output buffer register buffer is empty); AQin - receiver acknowledgment of information reception (from MPA 23); RQa - request to the arbitrator (from 18); Ada confirmation (permission) from the arbitrator; RQout request for writing to the output buffer register; AQout - confirmation of writing to the output buffer register (inverted signal Buffer full).

0 The generation of control signals is carried out by a control unit 18, the transition diagram of which is shown in FIG. four.

After writing the packet to the input register

5, the address part is decoded by address decoder 17, which determines the direction of the further transmission:

- if the coordinates of the receiver node are different from the coordinates of the current node

0, the decoder issues a code corresponding to the possibility of output in any direction (vertical or horizontal);

- if one of the coordinates does not match, the decoder generates a code for the request

5 by an output channel control block 18, over which there is no match (for example, if the column coordinates do not match, block 18 requests a horizontal output channel);

0 - when coordinates coincide, a channel is requested for output to the current PM.

Switching the direction of the movement of the packet is carried out by a switch 11, which is a complete switch. In this case, it has two inputs and two outputs. Each output channel has a channel arbiter 20 to which requests are received from the control unit 18 of the input interfaces 10, which, in accordance with

The 0 prioritized system presents its output channel to one of the output channels. This opens the corresponding key 19 and the packet from the output of the input register 21 enters the output

Channel 5 to the input of the output buffer registers 14 and 15.

The control unit 18 of the corresponding input channel forms the write signals to the buffer register. The OR 22 elements are used to combine the write signals to the buffer registers from all input interfaces 9 and 10. Upon receipt of the write confirmation, the buffer registers of the control unit 18 are returned to their original position and this input interface is ready for operation. Such a method of constructing switching nodes is generally accepted.

With an increase in the total number of packets (load on the network), the network performance drops, and with further

by increasing the load, it may go into a locked state.

To eliminate the blocking effect, methods and devices for local and global network load control are used. Analog equipment was used to control the load.

1. The conversion of the fill factor of the output buffers, which is proportional to the number of packets in the queues (network load), is made into an analog signal using a DAC 14 and 15.

2. The summation of signals from all nodes is performed. The resulting signal is proportional to the total number of packets.

3. When the level of the reference voltage source specified by the source signal is exceeded, a signal is generated at output B, controlling the operation of the PM and preventing packets from entering the network from the PM through the inputs 5. Thus, the load is limited and maintained by the required (optimal) number of packets in network. At the same time, maximum performance is achieved.

When the network dimension is small, the resistance of the resistors 2 is chosen to be equal to zero (replaced by conductors). As the network dimension increases, resistance of connecting conductors, which are different (due to different geometrical interposition of PM), is manifested. To equalize the resistances of the connections, resistors 2 are used, the resistances of which are greater than the resistance of the connections. In this case, the voltage at each node is determined by the following relationship:

U Z | + ... + Zi

311 i i

where Z is the idler resistance transmission;

i is the current of the converted source.

The transfer resistance characterizes the source's contribution to the resulting node voltage. The farther away the source from the node (electrical circuit), the less influence it has. In this example, the current sources i are DAC nodes. The current i is proportional to the loading of the i-ro switching node buffers.

Due to the effect of resistance, the resulting voltage at the nodes is not proportional to the total number of packages due to different transfer resistances Z. In this case, the proposed device maintains the specified number of packages in a certain zone. In this case, the reference voltage should be chosen based on the compromise between underloading the network and the possibility of blocking. At the same time, productivity increase (control using feedback on loading only buffer registers

its node is achieved by controlling when using feedback from a certain zone, which more adequately reflects the situation in the network as a whole, therefore, more precisely, the level of restriction of the incoming load can be set with greater accuracy.

The ability to manage the load on the switch network reduces the likelihood of interlocks and therefore increases

5 device performance.

Claims (1)

Claims of the invention A load control device of a switching medium of a multiprocessor system containing a group of blocks 0 switching, each of which contains the first, second and third interfaces, a switch, the first second and third buffer registers, the first input of the first interface of the switching unit is connected to 5 by the output of the processor module of the switching unit 1, the first inputs of the second and third interfaces of the switching unit are connected to the information input of the switching unit, the information outputs of all 0 interfaces of the switching unit are connected respectively to the switch input of the switching unit, and the switch outputs are connected respectively to the inputs of the first, second and third buffer registers of the switching unit, the information output of the first buffer register is connected to the input of the processor unit of the switching unit, outputs of the second and third buffer registers the switching unit is connected to the information output of the switching unit; the second inputs of all the interfaces of the switching unit are connected to the request input of the switching unit The confirmation outputs of all interfaces of the switching unit are combined and are the output of confirmation of the switching unit, the inputs of the first and second digital-to-analog converters are connected to the outputs of the second and third buffer registers of the switching unit, characterized in that, in order to improve performance by controlling the switching load network, in each switching unit entered the third digital-analog 5 a converter and an analog comparator, with the input of the third digital-to-analog converter connected to the output of the first buffer register of the switching unit, the outputs of all the digital-to-analog converters of the switching unit are combined and are connected to the first input of the analog comparator and are the analog output of the switching unit; the second input of the analog comparator of the switching unit is connected to the input voltage of the switching unit, the output of the analog com { 12 Yu, P 13, ten, 13, the parator is the load control output of the processor unit of the switching unit; the analog outputs of all the switching units are interconnected via the terminating resistors. fe Start Record 8 K & Zt IDD decryption AQln-0; RQct-0; RQoitt 0