JP2002247096A - Cell delay reducing method and cell delay reduction system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cell delay reducing method and a cell delay reduction system to reduce delay of cells. SOLUTION: A SAR or ATM Switch 1 transmits the cells at a set peak rate. The peak rate to be set in the SAR or ATM Switch 1 is set according to SAR (low throughput) 4 in the case of normal broadcast data transfer here, however, setting of the rate according to a receiving ability of SAR (high throughput) 3 is enabled by using a cell interval converting circuit 2. This is because the cell interval converting circuit 2 converts the intervals of the cells transmitted from the SAR or ATM Switch 1 into the ones where the cells are receivable by the SAR (low throughput) 4. Thus, reception of the cells transmitted from the SAR or ATM Switch 1 with the intervals where the cells can not be received by the SAR (low throughput) 4 is also enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cell delay reduction method and a cell delay reduction system.

[0002]

2. Description of the Related Art Conventionally, UTOPIA (Universal Test and Ope
rations PHY Interface for ATM: Utopia) Level2
In systems where data transfer was performed using
er and some slaves directly, or UTOPIA
SAR with only Level1 interface (Segmentatio
n and Reassemby sublayer (cell division / assembly sublayer) were connected by inserting a level conversion unit of UTOPIA between them.

[0003]

However, the above configuration has the following problems.

[0004] The first problem is that when broadcast data transfer is performed, the processing capability of the SAR serving as a slave is different. Therefore, it is necessary to lower the transmission peak rate on the master side in accordance with the SAR having the lowest processing capability. Yes, this causes data delays,
The point is that real-time processing as a system is hindered.

[0005] The second problem is that a temporary increase in traffic to the memory due to the reception of a cell from the Slave causes some of the traffic to increase.
The point is that there is a possibility that the processing unit including the SAR as the slave cannot perform higher priority real-time processing.
Therefore, it is necessary to reduce the peak rate of cells transmitted from the Master to such an extent that the real-time processing of the processing unit including the SAR is not hindered.

An object of the present invention is to provide a cell delay reduction method and a cell delay reduction system that solve the above problems.

[0007]

SUMMARY OF THE INVENTION A cell interval conversion circuit, a cell interval conversion method and a cell delay reduction method using the same according to the present invention are disclosed in UTOPIA (Universal Test & Operations).
PHY Interface for ATM) Reduces cell delay in a system that broadcasts data using Level2. This is because for devices with low cell reception capability, the cell interval conversion circuit is used to convert the cell interval, and the master
This is because the cell transmission at a higher peak rate becomes possible. Further, it is possible to prevent a delay in real-time processing to be performed by the CPU.

The SAR or ATM Switch according to the present invention transmits cells at a set peak rate. Here, in the case of normal broadcast data transfer, the peak rate set in the SAR or ATM Switch is set according to the SAR (low processing capacity). ) Can be set in accordance with the receiving capability of (capability). This is because the cell interval conversion circuit is SAR or ATM Swi
This is because the interval between cells transmitted from tch is converted into an interval that can be received by SAR (low processing capability). As a result, cells transmitted from the SAR or ATM Switch at intervals where SAR (low processing capacity) cannot be received can also be received.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment of the Invention) FIG.
, The SAR or ATM Switch 1 has a UTOPIA Level2 interface 15 for transmitting / receiving cells to / from another SAR, and a communication path with another device or device.
The SAR or ATM Switch 1 is connected to a cell interval conversion circuit 2 and a SAR (high processing capacity) 3 through a UTOPIA Level 2 interface 15.

The cell interval conversion circuit 2 includes a UTOPIA Level 2 interface 15 for transmitting and receiving cells, and a SAR
(Low processing capacity) UTOPIA Lev for transmitting and receiving cells with 4
It has an el1 interface. Cell interval conversion circuit 2
SAR o through UTOPIA Level2 interface 15
r Connected to ATM Switch 1 and SAR (high processing capacity) 3, UTOPI
It is connected to SAR (low processing capability) 4 through ALevel1 interface.

SAR or AT according to a first embodiment of the present invention
M Switch 1 transmits cells at the set peak rate. Here, for normal broadcast data transfer, SAR or ATM
The peak rate set in Switch 1 is SAR (low processing capacity)
4, the use of the cell interval conversion circuit 2 makes it possible to set the rate in accordance with the reception capability of the SAR (high processing capability) 3. This is because, as shown in FIG.
This is for converting the interval of cells transmitted from the SAR into an interval that the SAR (low processing capability) 4 can receive. As a result, the SAR or ATM Switch 1 is set at intervals where SAR (low processing capacity) 4 cannot be received.
Can also be received.

The SAR (high throughput) 3 has a UTOPIA Level 2 interface 15 for transmitting and receiving cells,
It is connected to the AR or ATM Switch 1 and the cell interval conversion circuit 2. Further, it is connected to a CPU and its peripheral circuit 5 for transmitting and receiving data and controlling SAR (high processing capability) 3.

The SAR (low processing capability) 4 has a UTOPIA Level 1 interface for transmitting and receiving cells, and is connected to the cell interval conversion circuit 2. Further, it is connected to a CPU and its peripheral circuit 6 for data transmission / reception and SAR (low processing capability) 4 control.

The CPU and its peripheral circuits 5 are connected to the SAR (high processing capability) 3 for transmitting and receiving data and controlling the SAR (high processing capability) 3.

The CPU and its peripheral circuit 6 are connected to the SAR (low processing capability) 4 in order to transmit and receive data and control the SAR (low processing capability) 4.

FIG. 3 is a block diagram showing a configuration example of the cell interval conversion circuit 2 according to the first embodiment of the present invention. The cell interval conversion circuit 2 includes a UTOPIA Level2Slave interface unit 7, a cell buffer 8, an address monitoring unit 9,
Address monitoring and interval control unit 10, cell buffer 11,
It comprises a UTOPIA Level1 interface unit 12.

The UTOPIA Level 2 interface unit 7
The cell received from the TOPIA Level 2 interface 15 is transferred to the cell buffer 11. Further, the address monitoring unit 9
Receives the cell transmission request signal from the cell buffer 8 and fetches the cell data from the cell buffer 8 to the UTOPIA Level 2 interface 1
5 to the cell.

The address monitoring unit 9 monitors the read pointer and the write pointer of the cell buffer 8 and, if there is one or more cells of data in the cell buffer 8, UTOPIA Level 2
A cell transmission request signal is output to the Slave interface unit 7.

The address monitoring and interval control unit 10 monitors the read pointer and the write pointer of the cell buffer 11, and monitors whether there is one or more cells of data in the cell buffer 11. If there is more than one cell of data, UTOPIA
If a predetermined interval or more has elapsed since the last transmission of the cell by the Level1 interface, a cell transmission request signal is output to the UTOPAI Level1 interface unit 12. Cell interval control is controlled by the control signal line R of the UTOPIA Level 1 interface.
This is done by monitoring the assertion intervals of xClav and RxSOC.

UTOPIA Level 1 interface section 12
Transfers the cell received from the UTOPIA Level 1 interface to the cell buffer 8. Further, when receiving a cell transmission request signal from the address monitoring and interval control unit 10, the cell data is fetched from the cell buffer 11 and the UTOPIA Level 1 is read.
Send a cell to the interface.

Next, the operation of transmitting a cell from the SAR or ATM Switch 1 and transferring it to the CPU and its peripheral circuit 6 will be described with reference to FIG.

First, the SAR or ATM Switch 1 converts the generated cell or the transmitted cell into a cell interval conversion circuit 2.
And SAR (high processing capacity) 3 to transmit. Here, the cell interval is converted into a receivable cell interval by the SAR (low processing capability) 4 by the cell interval conversion circuit 2, so that the SAR or ATM Swi
tch1 can transmit cells at a peak rate that SAR (high processing capacity) 3 can process. Therefore, SAR or
There is no need to lower the peak rate of ATM Switch 1 for SAR (low processing capacity) 4.

SAR (high processing capacity) 3 is SAR or ATM Switch
The cell data received from CPU 1 and its peripheral circuits 5
Transfer to

The cell interval conversion circuit 2 is SAR or ATM Switch 1
The UTOPIA Level 2 interface unit 7 shown in FIG. The address monitoring and interval control unit 10 monitors a read pointer and a write pointer of the cell buffer 11 and monitors whether or not the cell buffer 11 has data of one or more cells. If there is one or more cells of data in the cell buffer 11 and a predetermined interval has elapsed since the last transmission of the cell by the UTOPIA Level 1 interface, UTOPAI
A cell transmission request signal is output to the Level1 interface unit 12. Here, the cell interval control is performed by monitoring the assert interval of the control signal lines RxClav and RxSOC of the UTOPIA Level1 interface unit 12. By monitoring the cell interval, it is possible to prevent the output of the cell transmission request signal at the cell interval that the SAR (low processing capability) 4 cannot process.

UTOPIA Level 1 interface section 12
Receives the cell transmission request signal from the address monitoring and interval control unit 10, fetches the cell data from the cell buffer 11, and transmits the cell to the SAR (low processing capability) 6 in FIG. 1 through the UTOPIA Level 1 interface.

The SAR (low processing capacity) 4 converts the cell data received from the cell interval conversion circuit 2 into a CPU and its peripheral circuits 6.
Transfer to

Next, referring to FIG.
The operation from the time when the AR (low processing capacity) 4 takes in the data, divides the data and transmits the cell, and the time when the SAR or ATM Switch 1 receives the cell will be described.

First, the SAR (low processing capability) 4 takes in data from the CPU and the peripheral circuit 6 and divides it to transmit cells.

The cell interval conversion circuit 2 has a SAR (low processing capability) 4
When receiving a cell from the UTOPIA Level 1 interface unit 12 in FIG. The address monitoring unit monitors the address pointer and the read pointer of the cell buffer 8 and outputs a cell transmission request signal to the UTOPIA Level 2 Slave interface unit 7 when there is data of one or more cells. UTOPIA Level2 Slav
The e interface unit 7 receives the cell transmission request signal from the address monitoring unit 7, receives the cell data from the cell buffer, and transfers the cell to the SAR or ATM Switch 1 through the UTOPIA Level 2 interface 15.

The SAR or ATM Switch 1 receives the cell transmitted from the cell interval conversion circuit 2.

(Second Embodiment of the Invention) Next, a second embodiment of the present invention will be described.

Referring to FIG. 3, the address monitoring and interval control unit 10 includes a UTOPIA Level 1 interface unit 12.
From UTOPIA Level1 interface control signal line RxCla
v, RxSOC, etc. are monitored and intervals are controlled. Another interval control method includes an address monitoring and interval control unit 10.
There is a method of monitoring a transmission request signal from the Internet, and this method is used in the second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration example of the cell interval conversion circuit 2 according to the second embodiment of the present invention.

The second embodiment of the present invention is the first embodiment of the present invention.
According to the embodiment, the signal line from the UTOPIA Level 1 interface unit 12 to the address monitoring and interval control unit 10 can be deleted.

In this case, the address monitoring and interval control unit 1
The operation of 0 is as follows.

The address monitoring and interval control unit 10 monitors the read pointer and the write pointer of the cell buffer 11 to monitor whether or not there is one or more cells of data in the cell buffer. When one or more cells of data are present in the cell buffer 11, if the predetermined interval has elapsed since the address monitoring and interval control unit 10 outputs the last cell transmission request signal to the UTOPIA Level 1 interface unit 12, the cell transmission is performed. Output a request signal.

[0037]

As described above, the present invention has the following effects.

The first effect is that the SAR or ATM Switch shown in FIG.
1 allows cells to be transmitted at a peak rate that SAR (high throughput) 3 can process without considering the reception capability of SAR (low throughput) 4 and reduces cell delay for SAR (high throughput) 5 It is to be. The reason that cell transmission is possible at the peak rate is that the cell interval conversion circuit 2
This is because the interval between cells transmitted from the ATM switch 1 is converted into a cell interval that the SAR (low processing capability) 4 can receive.

The second effect is that when the SAR (low processing capability) 4 transfers a received cell to the system memory used by the CPU, it prevents a delay in real-time processing to be performed by the CPU. The reason is that the cell interval conversion circuit 2 converts the cell interval to a constant interval, so that the traffic from the SAR (low processing capacity) 4 to the system memory can be kept constant.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing that a cell interval conversion circuit converts an interval between cells transmitted from a SAR or an ATM Switch into an interval that can be received by a SAR (low processing capability).

FIG. 3 is a block diagram illustrating a configuration example of a cell interval conversion circuit according to the first embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration example of a cell interval conversion circuit according to a second embodiment of the present invention.

[Description of Signs] 1 SAR or ATM SwitchUTOPIA Level2 interface 2 Cell interval conversion circuit 3 SAR (high processing capability) 4 SAR (low processing capability) 5, 6 CPU and its peripheral circuits 7 UTOPIA Level2 interface unit 8, 11 cell buffer 9 Address monitoring unit 10 Address monitoring and interval control unit 12, 14 UTOPIA Level1 interface unit 13 UTOPIA Level2 Slave interface unit 15 UTOPIA Level2 interface 16 UTOPIA Level2Master interface unit

Claims (6)

[Claims] 1. A cell interval conversion circuit and a SAR or ATM Switch connected to a SAR (high processing capability) through a UTOPIA Level2 interface, a UTOPIA Level2 Slave interface unit for transmitting and receiving cells, and a SAR (low processing capability) ) And a UTOPIA Level1 interface for transmitting and receiving cells,
The SAR o through the UTOPIA Level2 interface
r Connected to the ATM Switch and the SAR (high throughput), and through the UTOPIA Level 1 interface unit, the SAR
(Low processing capacity), and a UTOPIA Level 2 Slave interface for transmitting and receiving cells, and a SAR (ATM switch) connected to the SAR or ATM Switch and the cell interval conversion circuit. processing power)
Having a UTOPIA Level1 interface for transmitting and receiving cells, and connected to the cell interval conversion circuit.
A first CPU connected to the SAR (high processing capability) and its peripheral circuits for transmitting and receiving data and controlling the SAR (high processing capability); And a cell delay reduction system including a second CPU connected to the SAR (low processing capability) and its peripheral circuit for controlling the SAR (low processing capability). 2. The UTOPIA Level2 Slave interface unit, a first cell buffer, an address monitoring unit, an address monitoring and interval control unit, a second cell buffer, and a UTOPIA Level1 interface unit. And the UTOPIA Level2 Slave interface unit is a UTOPIA
SAR or ATM Switch through IA Level2 interface
Transfer the cell received from the second cell buffer,
Upon receiving a cell transmission request signal from the address monitoring unit,
Fetching cell data from the first cell buffer;
SAR or AT through UTOPIA Level2 interface
M switch means for transmitting a cell, the address monitoring unit monitors a read pointer and a write pointer of the first cell buffer,
If there is one or more cells in the cell buffer, the UTO
PIA Level2 Slave interface means for outputting a cell transmission request signal to the interface unit, the address monitoring and interval control unit monitors the read pointer and the write pointer of the second cell buffer, the second cell buffer Monitors whether there is more than one cell in the data, and if there is more than one cell, UTO
If the PIA Level1 interface has transmitted a cell last, and if the interval is equal to or longer than a predetermined interval, a cell transmission request signal is output to the UTOPAI Level1 interface unit. The UTOPIA Level1 interface unit has a means for performing
When the cell received from the Level1 interface is transferred to the first cell buffer, and a cell transmission request signal is received from the address monitoring and interval control unit, the cell data is fetched from the second cell buffer and the cell is transferred to the UTOPIA Level1 interface. The cell delay reduction system according to claim 1, wherein: 3. The UTOPIA Level2 Slave interface unit, a first cell buffer, an address monitoring unit, an address monitoring and interval control unit, a second cell buffer, and a UTOPIA Level1 interface unit. And the UTOPIA Level2 Slave interface unit is a UTOPIA
SAR or ATM Switch through IA Level2 interface
Transfer the cell received from the second cell buffer,
Upon receiving a cell transmission request signal from the address monitoring unit,
Fetching cell data from the first cell buffer;
SAR or AT through UTOPIA Level2 interface
M switch means for transmitting a cell, the address monitoring unit monitors a read pointer and a write pointer of the first cell buffer,
If there is one or more cells in the cell buffer, the UTO
A means for outputting a cell transmission request signal to a PIA Level2 Slave interface unit, wherein the address monitoring and interval control unit monitors a read pointer and a write pointer of the second cell buffer, and the second cell buffer Monitor whether there is more than one cell of data, if there is more than one cell of data, the address monitoring and interval control unit outputs the last cell transmission request signal to the UTOPIA Level1 interface unit, then the default If the interval has elapsed, the UTOPIA Level 1
A cell transmission request signal is output to the interface unit, and the cell interval control has means for performing by monitoring the cell transmission request signal from the address monitoring and interval control unit.The UTOPIA Level1 interface unit includes the UTOPIA
When the cell received from the Level 1 interface is transferred to the first cell buffer, and a cell transmission request signal is received from the address monitoring and interval control unit, the cell data is fetched from the second cell buffer and the cell is transferred to the UTOPIA Level 1 interface. The cell delay reduction system according to claim 1, wherein: 4. A cell generated by the SAR or ATM Switch or a transmitted cell is converted into a cell interval conversion circuit and an SA.
R (high processing capability) to broadcast, and, by the SAR (high processing capability), transfer the cell data received from the SAR or ATM Switch to the first CPU and its peripheral circuits, The SAR or ATM Switch
The cell data received from the SAR (low processing capacity) is converted to a receivable cell interval, the cell data is transferred to the second cell buffer by the UTOPIA Level2 interface unit, the address monitoring and interval control unit, Monitor the read pointer and write pointer of the second cell buffer, monitor whether there is one or more cells of data in the second cell buffer, there is one or more cells of data in the second cell buffer, If a predetermined interval has elapsed since the UTOPIA Level 1 interface last transmitted a cell, a cell transmission request signal is output to the UTOPAI Level 1 interface unit, and the cell interval control is performed on the control signal line of the UTOPIA Level 1 interface unit. Monitoring the assertion interval; and performing the address monitoring and interval control by the UTOPIA Level1 interface unit. Receiving the cell transmission request signal from the second cell buffer, fetching the cell data from the second cell buffer, transmitting the cell to the SAR (low processing capability) through the UTOPIA Level1 interface, and the SAR (low processing capability) Transferring the cell data received from the cell interval conversion circuit to a second CPU and its peripheral circuits. 5. A cell generated by the SAR or ATM Switch or a transmitted cell is converted into a cell interval conversion circuit and an SA.
R (high processing capacity) to broadcast, and, by the SAR (high processing capacity), transfer the cell data received from the SAR or ATM Switch to the first CPU and its peripheral circuits, The SAR or ATM Switch
The cell data received from the SAR (low processing capability) is converted to a receivable cell interval, the cell data is transferred to the second cell buffer by the UTOPIA Level2 interface unit, the address monitoring and interval control unit, Monitor the read pointer and the write pointer of the second cell buffer, monitor whether there is one or more cells of data in the second cell buffer, there is one or more cells of data in the second cell buffer, and If a predetermined interval has elapsed since the address monitoring and interval control unit outputs the last cell transmission request signal to the UTOPIA Level 1 interface unit, a cell transmission request signal is output to the UTOPIA Level 1 interface unit, and the cell Performing interval control by monitoring a cell transmission request signal from the address monitoring and interval control unit; and performing the UTOPIA Level 1 interface. Interface unit, upon receiving a cell transmission request signal from the address monitoring and interval control unit, fetches cell data from the second cell buffer and transmits cells to the SAR (low processing capacity) through the UTOPIA Level 1 interface. A cell delay reducing method comprising: transferring cell data received from the cell interval conversion circuit to a second CPU and its peripheral circuit by the SAR (low processing capability). 6. A step of taking in data from a second CPU and peripheral circuits by SAR (low processing capability) and transmitting the divided cells, and a cell interval conversion circuit receiving cells from said SAR (low processing capability). Then, by UTOPIA Level1 interface part,
The cell data is transferred to the first cell buffer, the address monitoring unit monitors the address pointer and the read pointer of the first cell buffer, and if there is data of one or more cells, a cell transmission request is sent to the UTOPIA Level2 interface unit. When a cell transmission request signal is received from the address monitoring unit by the UTOPIA Level 2 interface unit, a cell data is received from the first cell buffer, and the SAR is transmitted through the UTOPIA Level 2 interface.
A cell delay reduction method, comprising: transferring a cell to an orATM Switch; and receiving, by the SAR or ATM Switch, a cell transmitted from the cell interval conversion circuit.