CN117546624A

CN117546624A - Memory, memory control method and forming method, and electronic device

Info

Publication number: CN117546624A
Application number: CN202180099438.8A
Authority: CN
Inventors: 黄凯亮; 景蔚亮; 冯君校; 王正波
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-11-03
Filing date: 2021-11-03
Publication date: 2024-02-09
Also published as: WO2023077314A1

Abstract

The embodiment of the application provides a memory, a memory control method, a memory forming method and electronic equipment. Relates to the technical field of semiconductor memories. The method is mainly used for improving the integration density of the memory cells. The memory comprises a substrate and at least one memory cell integrated on the substrate, wherein the memory cell comprises a first transistor and a second transistor, that is to say, the memory cell belongs to a cell structure of a gain-cell of 2T 0C; in addition, the memory cell further includes a first control line, a second control line, and a third control line, a first pole of the first transistor is electrically connected to a gate of the second transistor, a second pole of the first transistor is electrically connected to a second pole of the second transistor, the gate of the first transistor is electrically connected to the first control line, the first pole of the second transistor is electrically connected to the second control line, and both the second pole of the first transistor and the second pole of the second transistor that are electrically connected to the third control line. I.e. by reducing the number of control lines, to increase the storage density.

Description

Memory, memory control method and forming method, and electronic device

Technical Field

The present disclosure relates to the field of semiconductor memory technology, and more particularly, to a memory, a method for controlling the memory, a method for forming the memory, and an electronic device including the memory.

Background

In a computing system, a dynamic random access memory (dynamic random access memory, DRAM) is a memory structure that can be used to temporarily store operation data of a central processing unit (central processing unit, CPU) and exchange data with an external memory such as a hard disk, and is an important component in the computing system.

Fig. 1 shows a circuit diagram of one of memory cells in a conventional DRAM, which includes two transistors, and thus the formed memory cell may be referred to as a 2T0C (where T represents a transistor and C represents a capacitor) memory cell. Wherein, the two transistors in the 2T0C memory cell shown in fig. 1 may be referred to as a write transistor Tr0 and a read transistor Tr1, respectively; a gate of the write transistor Tr0 is electrically connected to a Write Word Line (WWL), one of a source and a drain of the write transistor Tr0 is electrically connected to a Write Bit Line (WBL), and the other of the source and the drain of the write transistor Tr0 is electrically connected to a gate of the read transistor Tr1; one of the source and the drain of the read transistor Tr1 is electrically connected to a Read Word Line (RWL), and the other of the source and the drain of the read transistor Tr1 is electrically connected to a Read Bit Line (RBL).

In the memory including the memory cells of fig. 1, each memory cell occupies a larger area and has a lower integration density. With the continuous increase of the operation data volume of the processor, a memory with higher integration density needs to be designed to meet the requirements of people on data processing in the information age.

Disclosure of Invention

The application provides a memory, a memory control method, a memory forming method and an electronic device comprising the memory. The main purpose is to provide a memory which can reduce the occupied space of a memory unit and improve the integration density of the memory unit.

In order to achieve the above purpose, the embodiments of the present application adopt the following technical solutions:

in a first aspect, the present application provides a memory, which may be a dynamic random access memory (dynamic random access memory, DRAM).

The memory comprises a substrate and at least one memory cell integrated on the substrate, wherein the memory cell comprises a first transistor and a second transistor, that is to say, the memory cell belongs to a cell structure of a gain-cell of 2T 0C; in addition, the memory cell further includes a first control line, a second control line, and a third control line, wherein a first pole of the first transistor is electrically connected to a gate of the second transistor, a second pole of the first transistor is electrically connected to a second pole of the second transistor, the gate of the first transistor is electrically connected to the first control line, the first pole of the second transistor is electrically connected to the second control line, and the second pole of the electrically connected first transistor and the second pole of the second transistor are electrically connected to the third control line.

The memory cell of the memory provided by the application is a 2T0C gain-cell. In the memory cell, not only the first electrode of the first transistor is electrically connected to the gate of the second transistor, but also the second electrode of the first transistor is electrically connected to the second electrode of the second transistor, and the electrically connected second electrode of the first transistor and second transistor are electrically connected to a third control line, which may be referred to herein as a write bit line WBL or a read word line RWL. That is, in the memory cell, the write bit line WBL is shared with the read word line RWL, i.e., one control line is shared; in addition, each memory cell includes a first control line that is a write word line WWL and a second control line that is a read bit line RBL. When the design is adopted, each storage unit comprises three control lines, compared with the existing storage units comprising four control lines, the number of the control lines can be reduced, and further, the occupied area of each storage unit can be reduced by reducing the number of the control lines, the storage density of the storage units is improved, and the storage capacity is improved so as to adapt to the operation data amount of a processor.

In one possible implementation, the first transistor and the second transistor are stacked in a direction perpendicular to the substrate.

It will be appreciated that in the memory cell presented herein, the first transistor and the second transistor are vertically stacked on the substrate. In this way, the area occupied by each memory cell on the substrate can be further reduced, for example, the area of each memory cell can be reduced to 4F ² And, 3-dimensional (3 d) stacking on the substrate can also be implemented.

In one possible implementation, the gate of the second transistor shares the same electrode as the first electrode of the first transistor, the electrode shared by the gate of the second transistor and the first electrode of the first transistor is the first common electrode, the second electrode of the second transistor shares the same electrode as the second electrode of the first transistor, and the electrode shared by the second electrode of the second transistor and the second electrode of the first transistor is the second common electrode. That is, in this memory cell, the first electrode of the first transistor and the gate electrode of the second transistor share the same electrode structure, and the second electrode of the first transistor and the second electrode of the second transistor also share the same electrode. In this way, the original 2T0C memory cell including six electrodes becomes a 2T0C memory cell including four electrodes, that is, by reducing the number of electrodes to be arranged, the area occupied by each memory cell can be further reduced, so as to improve the memory density.

In one possible implementation, the second common electrode has a first side perpendicular to the substrate and has a second side parallel to the substrate; the first common electrode is positioned on one side of the first side face facing the first electrode; the first electrode of the second transistor is positioned on one side facing the second side face; the gate of the first transistor is located on a side of the first and second common electrodes remote from the first pole of the second transistor. Based on the above description of the electrode arrangement positions, it can be seen that in the first transistor, the channel thus formed may be a horizontal channel parallel to the substrate since the first and second poles are arranged in a direction parallel to the substrate, and in the second transistor, the channel thus formed may be a vertical channel perpendicular to the substrate since the first and second poles are arranged in a direction perpendicular to the substrate.

In one possible implementation, the second transistor further comprises a semiconductor layer; in the second transistor, the semiconductor layer includes a first semiconductor portion and a second semiconductor portion which are in contact with each other, and an extending direction of the first semiconductor portion is perpendicular to the substrate and an extending direction of the second semiconductor portion is parallel to the substrate; the first semiconductor portion is in contact with the second side surface, and the second semiconductor portion is in contact with the third side surface; the third side is a side of the first electrode of the second transistor facing the second common electrode.

In the second transistor of this embodiment, the semiconductor layer structure includes two connected portions, which may be considered as an L-shaped structure, where the first semiconductor portion is in ohmic contact with the second common electrode and the second semiconductor portion is in ohmic contact with the first electrode of the second transistor, so that the ohmic contact area of the semiconductor layer may be increased to increase the current flow speed, and further, the read/write speed may be correspondingly increased.

In one possible implementation, the second transistor further includes a gate dielectric layer; the first common electrode and the second common electrode, the first common electrode and the first semiconductor part and the first common electrode and the second semiconductor part are isolated by a gate dielectric layer.

In one possible implementation, the second transistor further comprises a semiconductor layer; in the second transistor, the semiconductor layer includes a first semiconductor portion perpendicular to the substrate; one end of the first semiconductor portion near the second common electrode is in contact with the first side surface, and one end of the first semiconductor portion near the first electrode of the second transistor is in contact with the third side surface; the third side is a side of the first electrode of the second transistor facing the second common electrode.

That is, in this embodiment, the semiconductor layer of the second transistor has a linear structure to form a vertical channel of the second transistor.

In one possible implementation, the second transistor further includes a gate dielectric layer and a dielectric layer; the first common electrode and the first semiconductor part and the first common electrode and the first electrode of the second transistor are separated by a gate dielectric layer, and the second common electrode and the first electrode of the second transistor are separated by a dielectric layer.

In one possible implementation, the first pole of the second transistor includes a first portion and a second portion in contact, the first portion extending in a direction perpendicular to the substrate, the second portion extending in a direction parallel to the substrate, and the first portion being disposed proximate to the second common electrode relative to the second portion.

It can be understood that the first pole of the second transistor is in an L-shaped structure, so that the ohmic contact area between the semiconductor layer and the first pole of the L-shaped structure can be increased to increase the current speed, thereby increasing the read-write speed.

In one possible implementation, in the first transistor, the semiconductor layer is disposed on a side of the first and second common electrodes remote from the first pole of the second transistor; the first semiconductor portion is in contact with the semiconductor layer of the first transistor; alternatively, the first semiconductor portion is isolated from the semiconductor layer of the first transistor by a gate dielectric layer.

In one possible implementation, the first transistor further includes a semiconductor layer and a gate dielectric layer; in the first transistor, a gate electrode, a gate dielectric layer and a semiconductor layer are disposed on one side of a first common electrode and a second common electrode away from a first electrode of a second transistor, and the gate electrode, the gate dielectric layer and the semiconductor layer are stacked in order along a direction perpendicular to a substrate, and the semiconductor layer is in contact with the first common electrode and the second common electrode.

Based on the above description of the structure of the first transistor, it can be seen that in the first transistor, the semiconductor layer is arranged in a direction parallel to the substrate, and further, the channel of the first transistor belongs to a horizontal channel.

In one possible implementation, the first transistor, the second transistor, the first control line, the second control line, and the third control line are formed on the substrate using a subsequent process.

The first transistor and the second transistor are manufactured by adopting a back-pass process, and the control circuit can be manufactured by adopting a front-pass process. The control circuitry may include one or more of decoders, drivers, timing controllers, buffers, or input-output drivers, as well as other functional circuitry. The control circuit may control the first control line, the second control line, and the third control line in the embodiments of the present application. After the front end of line FEOL is completed, the interconnect lines, as well as the memory array, are fabricated by the back end of line BEOL. The transistor and the control line are manufactured through a subsequent process, so that the circuit density in the unit area is higher, and the storage performance of the unit area is improved.

In one possible implementation, the memory unit has a plurality of memory cells; the first control line and the second control line extend along a first direction parallel to the substrate, the first control line is electrically connected with the grid electrodes of the first transistors of the memory cells in the first direction, and the second control line is electrically connected with the first poles of the second transistors of the memory cells in the first direction; a third control line extending in a second direction parallel to the substrate, the third control line electrically connected to second poles of second transistors of the plurality of memory cells located in the second direction; the second direction is perpendicular to the first direction.

That is, when the plurality of memory cells are arranged in an array in a first direction and a second direction perpendicular to each other, the first control line and the second control line extend in the same direction, and the third control line extends in a direction perpendicular to the first control line. In the memory array, the first control line, the second control line, and the third control line are also laid out in an array.

In one possible implementation, during the write phase, the first control line is used to receive a first write word line control signal, such that the first transistor is turned on, and the third control line is used to receive a write bit line control signal to write logic information into the memory cell.

In one possible implementation, during a read phase, the first control line is used to receive a second write word line control signal, causing the first transistor to turn off, the third control line is used to receive a read word line control signal, and the second control line is used to output a signal to read logic information in the memory cell.

In a second aspect, the present application further provides a control method of a memory, where the memory includes at least one memory cell, and the memory cell includes a first transistor, a second transistor, a first control line, a second control line, and a third control line; the first transistor and the second transistor comprise a grid electrode, a first pole and a second pole, the first pole of the first transistor is electrically connected with the grid electrode of the second transistor, the second pole of the first transistor is electrically connected with the second pole of the second transistor, and the grid electrode of the first transistor is electrically connected with the first control line; the first electrode of the second transistor is electrically connected with the second control line, and the second electrode of the first transistor and the second electrode of the second transistor which are electrically connected with the third control line;

the control method comprises the following steps:

in the writing stage, the first control line is used for receiving a first writing word line control signal so that the first transistor is turned on, and the third control line is used for receiving a writing bit line control signal so as to write logic information into the memory cell.

In the control method of the memory, the second pole of the first transistor is electrically connected with the second pole of the second transistor in the memory, so that three control lines for controlling reading and writing are needed in one memory cell, and based on the characteristics, the occupied area of each memory cell can be reduced, and the memory density is improved.

In one possible implementation, the control method further includes: in the reading stage, the first control line is used for receiving a second write word line control signal so that the first transistor is turned off, the third control line is used for receiving a read word line control signal, and the second control line is used for outputting a signal to read logic information in the memory cell.

In one possible implementation, the gate of the second transistor shares the same electrode as the first electrode of the first transistor, and the second electrode of the second transistor shares the same electrode as the second electrode of the first transistor.

That is, in this memory cell, the first electrode of the first transistor and the gate electrode of the second transistor share the same electrode structure, and the second electrode of the first transistor and the second electrode of the second transistor also share the same electrode. In this way, the original 2T0C memory cell including six electrodes becomes a 2T0C memory cell including four electrodes, that is, by reducing the number of electrodes to be arranged, the area occupied by each memory cell can be further reduced, so as to improve the memory density.

In a third aspect, the present application further provides a method for forming a memory, where the forming method includes:

forming a first transistor and a second transistor on a substrate, the first transistor and the second transistor each including a gate, a first pole and a second pole, the first pole of the first transistor being electrically connected to the gate of the second transistor, the second pole of the first transistor being electrically connected to the second pole of the second transistor;

the first control line, the second control line and the third control line are formed, and the gate of the first transistor is electrically connected to the first control line, the first pole of the second transistor is electrically connected to the second control line, and the second pole of the electrically connected first transistor and the second pole of the second transistor are electrically connected to the third control line.

In the method for forming the memory, the first transistor, the second transistor, the first control line, the second control line and the third control line form a memory unit, and compared with the existing memory unit structure, the number of control lines for controlling reading and writing is reduced, so that the memory density of the memory unit can be improved, and the memory performance is improved.

In one possible implementation, forming the first transistor and the second transistor on the substrate includes: the first transistor and the second transistor are stacked in a direction perpendicular to the substrate.

That is, the first transistor and the second transistor are stacked in a direction perpendicular to the substrate, so that three-dimensional stacking of memory cells on the substrate can be realized to further improve the memory density.

In one possible implementation, when forming the second transistor, the method includes: forming a first pole of a second transistor; forming a gate and a second pole on one side of the first pole of the second transistor far away from the substrate, wherein the second pole is provided with a first side surface perpendicular to the substrate, and the gate is positioned on one side of the first side surface facing to the substrate; in forming a first transistor, comprising: and forming a grid electrode of the first transistor on one side, far away from the substrate, of the grid electrode of the second transistor and the second electrode, wherein the grid electrode of the second transistor and the first electrode of the first transistor share the same electrode, and the second electrode of the second transistor and the second electrode of the first transistor share the same electrode.

The first electrode of the first transistor and the grid electrode of the second transistor share the same electrode, and the second electrode of the first transistor and the second electrode of the second transistor also share the same electrode, so that the number of electrodes can be reduced, and the storage density can be further improved.

In a fourth aspect, the present application further provides an electronic device, including a processor and a memory in any implementation manner of the first aspect, the second aspect or the third aspect, where the processor is electrically connected to the memory.

The electronic device provided by the embodiment of the application includes the memories of the embodiments of the first aspect, the embodiments of the second aspect and the embodiments of the third aspect, so that the electronic device provided by the embodiment of the application and the memory of the above technical scheme can solve the same technical problems and achieve the same expected effects.

Drawings

FIG. 1 is a circuit diagram of a memory cell in a DRAM according to the prior art;

fig. 2 is a circuit diagram of an electronic device according to an embodiment of the present application;

FIG. 3 is a circuit diagram of a memory according to an embodiment of the present disclosure;

FIG. 4 is a simplified block diagram of a memory according to an embodiment of the present application;

FIG. 5 is a circuit diagram of a memory cell in a memory according to an embodiment of the present application;

FIG. 6 is a circuit diagram of a memory array formed by a plurality of memory cells in a memory according to an embodiment of the present disclosure;

fig. 7 is a diagram of a positional relationship between a memory cell and a substrate in a memory according to an embodiment of the present application;

FIG. 8 is a cross-sectional view of a process structure of a memory cell in a memory according to an embodiment of the present disclosure;

FIG. 9 is a three-dimensional diagram of a process structure of a memory cell in a memory according to an embodiment of the present application;

FIG. 10 is a simplified top view of a plurality of memory cells in a memory according to an embodiment of the present application;

FIG. 11 is a process block diagram of a memory according to an embodiment of the present disclosure;

FIG. 12 is a cross-sectional view of a process structure of a memory cell in a memory according to an embodiment of the present disclosure;

FIG. 13 is a cross-sectional view of a process structure of a memory cell in a memory according to an embodiment of the present disclosure;

FIG. 14 is a cross-sectional view of a process structure of a memory cell in a memory according to an embodiment of the present disclosure;

FIG. 15 is a cross-sectional view of a prior art process structure of a memory cell in a memory;

FIG. 16 is a block flow diagram of a method for fabricating a memory according to an embodiment of the present disclosure;

fig. 17a to 17e are cross-sectional views of corresponding process structures after each step in a memory manufacturing method according to an embodiment of the present application is completed;

fig. 18a to 18h are cross-sectional views of corresponding process structures after each step in a memory manufacturing method according to an embodiment of the present application is completed;

fig. 19a to 19h are cross-sectional views of corresponding process structures after each step in a memory manufacturing method according to an embodiment of the present application is completed;

fig. 20a to 20h are cross-sectional views of corresponding process structures after each step in a memory manufacturing method according to an embodiment of the present application is completed.

Reference numerals:

100-a substrate;

200-interconnecting lines;

300-a memory array;

400-memory cell;

500-dielectric layers;

tr 1-read transistor; 101-a first pole; 101-1-a first part; 101-2-a second part; 102-a semiconductor layer; 102-1-a first semiconductor portion; 102-2-a second semiconductor portion; 103-a gate dielectric layer; 104-gate; 105-second pole; 109-a dielectric layer;

tr 0-write transistor; 104-a first pole (first common electrode); 105-second pole (second common electrode); 106-a semiconductor layer; 107-gate dielectric layer; 108-grid electrode;

001-a first conductive layer;

002-a first semiconductor material layer;

003-a second conductive layer;

004-groove;

005-a layer of a first dielectric material;

006-a third conductive layer;

007-a layer of a second semiconductor material;

008-a layer of a second dielectric material;

009-a fourth conductive layer;

010-through holes;

011-a third dielectric material layer.

Detailed Description

The embodiments presented in the present application are described below with reference to the accompanying drawings.

The embodiment of the application provides an electronic device comprising a memory. Fig. 2 is a block circuit diagram of an electronic device 200 according to an embodiment of the present application, where the electronic device 200 may be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, a personal computer (personal computer, PC), a server, a workstation, or the like. As shown in fig. 2, the electronic device 200 includes a bus 205, and a System On Chip (SOC) 210 and a read-only memory (ROM) 220 connected to the bus 205. The SOC210 may be used to process data, such as data of processing applications, process image data, and buffer temporary data. The ROM220 may be used to hold non-volatile data such as audio files, video files, and the like. ROM220 may be a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), a flash memory, or the like.

In addition, the electronic device 200 may further include a communication chip 230 and a power management chip 240. The communication chip 230 may be used for processing the protocol stack, amplifying, filtering, etc. the analog radio frequency signal, or simultaneously implementing the above functions. The power management chip 240 may be used to power other chips.

In one embodiment, the SOC210 may include an application processor (application processor, AP) 211 for processing applications, an image processing unit (graphics processing unit, GPU) 212 for processing image data, and a random access memory (random access memory, RAM) 213 for caching data.

The AP211, GPU212, and RAM213 may be integrated into one die (die), or may be integrated into multiple dies (die), respectively, and packaged in a package structure, for example, using 2.5D (dimension), 3D packaging, or other advanced packaging techniques. In one embodiment, the AP211 and the GPU212 are integrated in one die, the RAM213 is integrated in another die, and the two die are packaged in a package structure, so as to obtain a faster inter-die data transmission rate and a higher data transmission bandwidth.

Fig. 3 is a circuit block diagram of a memory 300 according to an embodiment of the present application. The memory 300 may be the RAM213 as shown in fig. 2. In one embodiment, memory 300 may also be RAM disposed external to SOC 210. The position of the memory 300 in the electronic device and the positional relationship with the SOC210 are not limited in the present application.

Continuing with fig. 3, memory 300 includes a memory array 310, a decoder 320, a driver 330, a timing controller 340, a buffer 350, and an input-output driver 360. The memory array 310 includes a plurality of memory cells 400 arranged in an array, wherein each memory cell 400 may be used to store 1bit or more of data. The memory array 310 further includes signal control lines such as Word Lines (WL), bit Lines (BL), and the like. Each memory cell 400 is electrically connected to a corresponding word line WL, bit line BL. One or more of the word lines WL and the bit lines BL are used to select the memory cells 400 to be read and written in the memory array by receiving the level output by the control circuit, so as to implement the read and write operation of data.

In the memory 300 structure shown in fig. 3, the decoder 320 is configured to decode according to the received address to determine the memory cell 400 that needs to be accessed. The driver 330 is used to control the level of the signal line according to the decoding result generated by the decoder 320, thereby realizing access to the designated memory cell 400. The buffer 350 is used for buffering the read data, and may be, for example, a first-in first-out (FIFO) buffer. The timing controller 330 is used for controlling the timing of the buffer 350 and controlling the driver 330 to drive the signal lines in the memory array 310. The input-output driver 360 is used to drive transmission signals, such as to drive received data signals and to drive data signals to be transmitted, so that the data signals can be transmitted over a long distance.

The memory array 310, the decoder 320, the driver 330, the timing controller 340, the buffer 350, and the input/output driver 360 may be integrated into one chip or may be integrated into a plurality of chips.

The memory array 310 described above may be a single layer memory array, may include a first layer memory array and a second layer memory array stacked in a Z-direction perpendicular to the substrate as shown in fig. 4, or may include more layers of memory arrays in alternative embodiments. Where two or more layers of memory arrays are involved, such memories may be referred to as three-dimensional integrated memory structures.

In the memory structure shown in fig. 4, the control circuit is integrated on the substrate through a front end of line (FEOL) process, and the interconnect and the memory are integrated on the control circuit through a back end of line (BEOL) process. The control circuit may generate control signals, which may be read-write control signals, for controlling read-write operations of data in the memory.

The memory 300 according to the present application may be a dynamic random access memory (dynamic random access memory, DRAM) or a ferroelectric random access memory (ferroelectric random access memory, feRAM).

Fig. 5 is a circuit diagram of one memory cell 400 in the memory 300 presented herein. As shown in fig. 5, the memory cell 400 is of a gain-cell structure of 2T0C, that is, a memory cell 400 includes a write transistor Tr0 (may also be referred to as a first transistor) and a read transistor Tr1 (may also be referred to as a second transistor), and a first pole of the write transistor Tr0 is electrically connected to a gate of the read transistor Tr1 and a second pole of the write transistor Tr0 is electrically connected to a second pole of the read transistor Tr 1. In addition, the memory unit 400 further includes: a Write Word Line (WWL) and a Read Bit Line (RBL), and another signal line, which is electrically connected to the second pole of the write transistor Tr0 and the second pole of the read transistor Tr1, and which may be referred to as a Write Bit Line (WBL) or a Read Word Line (RWL); the write word line WWL is electrically connected to the gate of the write transistor Tr0, and the read bit line RBL is electrically connected to the first pole of the read transistor Tr 1.

In this application, the write word line WWL may also be referred to as a first control line for loading a signal to the gate of the write transistor Tr0, the read bit line RBL may also be referred to as a second control line for loading a signal to the first pole of the read transistor Tr1, and the write bit line WBL or the read word line RWL may also be referred to as a third control line for loading a signal to the second pole of the write transistor Tr0 and the second pole of the read transistor Tr 1.

In this application, one of the drain (drain) and source (source) of the transistor Tr is referred to as a first pole, the other pole is referred to as a second pole, and the control terminal of the transistor Tr is a gate. The drain and source of the transistor Tr may be determined according to the flow direction of current, for example, in the write transistor Tr0 of fig. 5, when the current is from left to right, the left end is the drain, and the right end is the source; conversely, when the current is going from right to left, the right end is the drain and the left end is the source.

In the memory cell 400 of the present embodiment, as shown in fig. 5, since the second pole of the write transistor Tr0 is electrically connected to the second pole of the read transistor Tr1, it is electrically connected to the signal control line write bit line WBL or to the signal control line read word line RWL. That is, the second pole of the write transistor Tr0 and the second pole of the read transistor Tr1 may share the control signal line. In this way, the memory cell provided by the application comprises three signal lines for controlling reading and writing, and compared with the existing four signal lines for controlling reading and writing, the number of the signal lines can be reduced, so that the occupied area of each memory cell is reduced, and the storage density and the storage capacity are improved.

The memory cells 400 shown in fig. 5 are arranged in an array to obtain the memory array 310, where the circuit structure of each memory cell 400 is the same. For example, fig. 6 illustrates a memory array 310 in which a 4×4 memory array is shown and arranged in orthogonal X and Y directions. As can also be readily seen from fig. 6, since the write transistor Tr0 and the read transistor Tr1 share the write bit line WBL and the read word line RWL, the number of signal control lines can be greatly reduced in a memory array including a plurality of memory cells, and thus the integration density of the memory cells can be significantly improved.

In some alternative embodiments, when the storage arrays shown in fig. 6 are stacked along the Z direction shown in fig. 4, three-dimensional stacking can be implemented, so as to further improve the storage capacity, so as to adapt to the processor with high operation efficiency.

With continued reference to fig. 5 and 6, a writing operation procedure and a reading operation procedure of the 2T0C memory cell 400 will be described, respectively.

The write operation process: during a write operation, the voltage of the read bit line RBL is 0 and the read transistor Tr1 does not operate; the write word line WWL is supplied with a first write word line control signal that controls the write transistor Tr0 to be turned on. When first logic information, for example, "0", is written, a first write bit line control signal is supplied to the write bit line WBL (or the read word line RWL), and the first write bit line control signal is written to the node N through the write transistor Tr 0. When the second logic information, for example, "1", is written, the second write bit line control signal is supplied to the write bit line WBL (or the read word line RWL), and is written to the node N through the write transistor Tr 0.

It should be understood that the read transistor Tr0 does not operate after the write operation is completed; the write word line WWL is supplied with a second write word line control signal which controls the write transistor Tr0 to be turned off, and at this time, the potential stored in the node is not affected by the outside.

The read operation process comprises the following steps: providing a second write word line control signal to the write word line WWL, the second write word line control signal controlling the write transistor Tr0 to be turned off; the read word line RWL (or the write bit line WBL) is supplied with a read word line control signal, and the logic information stored in the memory cell is determined according to the level of the current on the read bit line RBL. When the first write bit line control signal is stored in the node N, since the first write bit line control signal can control the read transistor Tr1 to be turned on, when the read word line RWL (or the write bit line WBL) provides the read word line control signal, the read word line RWL (or the write bit line WBL) charges the read bit line RBL through the read transistor Tr1, and the voltage on the read bit line RBL increases, so that when the current on the read bit line RBL is detected to be large, the logic information "0" stored in the memory cell can be read. When the node N stores the second write bit line control signal, since the second write bit line control signal can control the read transistor Tr1 to be turned off, when the read word line RWL (or the write bit line WBL) provides the read word line control signal, the read word line RWL (or the write bit line WBL) does not charge the read bit line RBL through the read transistor Tr1, and the read bit line RBL maintains the 0V voltage, so that when the current on the read bit line RBL is detected to be small, the logic information "1" stored in the memory cell can be read.

In some alternative embodiments, in order to further increase the storage density, in the memory cell 400 according to the present application, as shown in a simplified schematic diagram of a process structure in fig. 7, the write transistor Tr0 and the read transistor Tr1 may be stacked in a direction perpendicular to the substrate 100. In the embodiment shown in fig. 7, the read transistor Tr1 is disposed close to the substrate 100 with respect to the write transistor Tr 0. In other alternative embodiments, the write transistor Tr0 may be disposed closer to the substrate 100 than the read transistor Tr 1.

Also, the write transistor Tr0 and the read transistor Tr1 of the memory cell 400 of the present application each belong to a thin film transistor (Thin film transistor, TFT) structure. In combination with the layout manner shown in fig. 7, the write transistor Tr0 and the read transistor Tr1 of the TFT may be formed on the substrate 100 to form a three-dimensional integration, for example, as shown in fig. 4, and may be formed on the substrate 100 by a subsequent process to further increase the integration density and increase the storage capacity per unit area, thereby improving the storage performance of the memory.

Various manners that can be realized are given below for the structures of the write transistor Tr0 and the read transistor Tr1, and are described below with reference to the drawings, respectively.

Fig. 8 shows a cross-sectional view of one possible process structure of the write transistor Tr0 and the read transistor Tr1, which is a cross-sectional view taken along a plane parallel to the X-Z plane shown in fig. 7, and fig. 9 shows a three-dimensional structural view of fig. 8. Referring to fig. 8 and 9 together, the write transistor Tr0 includes a first electrode 104, a second electrode 105, a gate electrode 108, a gate dielectric layer 107, and a semiconductor layer 106 (the semiconductor layer 106 may also be referred to as a channel layer); the read transistor Tr1 includes a first pole 101, a second pole 105, a gate 104, a gate dielectric layer 103, and a semiconductor layer 102.

As can be seen from the process structure of the memory cell 400 shown in fig. 8 and 9, the first electrode 104 of the write transistor Tr0 and the gate electrode 104 of the read transistor Tr1 share the same electrode, which may be referred to as the first common electrode 104; in addition, the second electrode 105 of the write transistor Tr0 and the second electrode 105 of the read transistor Tr1 also share the same electrode, and this shared electrode may be referred to as a second shared electrode 105.

That is, in the stacked write transistor Tr0 and read transistor Tr1 shown in the present embodiment, two electrode structures are shared so that one memory cell 400 includes only four electrode structures in the process structure. Such a process structure can further reduce the area occupied by each memory cell 400 on the surface parallel to the substrate by reducing the number of electrode process structures, for example, as shown in fig. 9 and 10, the area occupied by the stacked write transistor Tr0 and read transistor Tr1 in the X direction is 1F, the active area is 1F, the area occupied by the stacked write transistor Tr0 and read transistor Tr1 in the Y direction is 1F, the active area is 1F, and thus the area occupied by the stacked write transistor Tr0 and read transistor Tr1 in the X-Y plane is 2f×2f=4f ² Compared with the prior 6F ² Or a larger footprint, the area occupied by the memory cell 400 presented herein is significantly smaller.

With continued reference to fig. 8 and 9, the gate electrode 108, the gate dielectric layer 107, and the semiconductor layer 106 of the write transistor Tr0 are sequentially stacked in the Z direction perpendicular to the substrate 100, and the first common electrode 104 as the first pole of the write transistor Tr0 and the second common electrode 105 as the second pole of the write transistor Tr0 are arranged in a direction parallel to the substrate 100, and further, the semiconductor layer 106 is in ohmic contact with both the first common electrode 104 and the second common electrode 105, so that a channel formed by the write transistor Tr0 is a horizontal channel parallel to the substrate 100.

It will be appreciated that the first common electrode 104 and the second common electrode 105 are arranged in a direction parallel to the substrate 100, the second common electrode 105 having a first side M1 perpendicular to the substrate 100, the first common electrode 104 being located on a side toward which the first side M1 faces.

In the read transistor Tr1 of the memory cell 400 shown in fig. 8 and 9, the second common electrode 105, which is the second pole of the read transistor Tr1, and the first pole 101 of the read transistor Tr1 are arranged in a direction perpendicular to the substrate 100, so that a channel formed by the read transistor Tr1 is a vertical channel perpendicular to the substrate.

As for the second common electrode 105 and the first electrode 101 of the read transistor Tr1 described above to be arranged in the direction perpendicular to the substrate 100, it is possible that the second common electrode 105 has the second side face M2 parallel to the substrate 100, and the first electrode 101 of the read transistor Tr1 is located on the side toward which the second side face M2 faces, as shown in fig. 8 and 9.

That is, in the process structure of the memory cell of 2T0C given in the present application, the write transistor Tr0 is a planar transistor and the read transistor Tr1 is a vertical transistor.

Referring again to fig. 8, in the read transistor Tr1, the semiconductor layer 102 includes a first semiconductor portion 102-1 and a second semiconductor portion 102-2, the extending direction (along the Z direction of fig. 8 and 9) of the first semiconductor portion 102-1 is perpendicular to the substrate, the extending direction (along the X direction of fig. 8 and 9) of the second semiconductor portion 102-2 is parallel to the substrate, and the first semiconductor portion 102-1 is in contact with the second side surface M2 of the second common electrode 105, the second semiconductor portion 102-2 is in contact with the third side surface M3 of the first electrode 101, where the second side surface M2 is a surface of the second common electrode 105 facing the first electrode 101, and the third side surface M3 is a surface of the first electrode 101 facing the second common electrode 105. That is, the semiconductor layer 102 in the read transistor Tr1 has an L-shaped structure and is in ohmic contact (may also be called as electric coupling) with the second common electrode 105 and the first electrode 101.

Referring to fig. 8 and 9 again, since the semiconductor layer 102 in the read transistor Tr1 has an L-shaped structure, in order to electrically isolate the first common electrode 104 from the second common electrode 105, the first common electrode 104 is electrically isolated from the semiconductor layer 102, and the gate dielectric layer 103 has an L-shaped structure correspondingly.

Fig. 11 is a three-dimensional structure diagram of a memory 300 according to the present application, and includes the memory unit 400 shown in fig. 8 and 9 described above. In fig. 11, the memory 300 is exemplarily shown to include a first-layer memory array and a second-layer memory array, and the first-layer memory array and the second-layer memory array are stacked along a Z-direction perpendicular to the substrate 100. Of course, in alternative embodiments, more layers of memory arrays may be stacked.

As shown in fig. 11, a dielectric layer 500 is required between every two adjacent layers of memory arrays to electrically isolate the adjacent layers of memory arrays so that any memory cell of any layer of memory array can be accessed during read and write.

With continued reference to fig. 11, in any one of the memory arrays, a plurality of memory cells arranged in a first direction (e.g., the X direction of fig. 11) and a plurality of memory cells arranged in a second direction (e.g., the Y direction of fig. 11) perpendicular to the first direction are included. Wherein the write word line WWL extends in the X direction and the read bit line RBL also extends in the X direction, then the gates 108 of the write transistors Tr0 of the plurality of memory cells arranged in the X direction are electrically connected to the write word line WWL extending in the X direction, and the first poles 101 of the read transistors Tr1 of the plurality of memory cells arranged in the X direction are electrically connected to the read bit line RBL extending in the X direction, the write bit line WBL (or the read word line RWL) extends in the Y direction, and the second common electrodes 105 of the plurality of memory cells arranged in the Y direction are electrically connected to the write bit line WBL (or the read word line RWL) extending in the Y direction.

Fig. 12 is a cross-sectional view of another process structure of a memory cell 400 according to the present application. The memory cell shown in fig. 12 is identical to the memory cell 400 shown in fig. 8 and 9 described above in that: the first common electrode 104 is shared by the first pole of the write transistor Tr0 and the gate of the read transistor Tr1, and the second common electrode 105 is shared by the second pole of the write transistor Tr0 and the second pole of the read transistor Tr 1; in addition, the same points include: the channel formed in the write transistor Tr0 is a horizontal channel (as indicated by the arrow-headed broken line drawn on the gate dielectric layer 106 in fig. 12), and the channel formed in the read transistor Tr1 is a vertical channel (as indicated by the arrow-headed broken line drawn on the gate dielectric layer 102 in fig. 12).

The memory cell 400 shown in fig. 12 is different from the memory cell 400 shown in fig. 8 and 9 described above in that: in the read transistor Tr1, the semiconductor layer 102 is in a structure perpendicular to the substrate, and the semiconductor layer 102 is in ohmic contact with the first side surface M1 of the second common electrode 105 and the semiconductor layer 102 is also in contact with the third side surface M3 of the first electrode 101 to form a vertical channel of the read transistor Tr 1. The first side surface M1 and the third side surface M3 are explained above, and are not described herein.

As further shown in fig. 12, in the read transistor Tr1, the semiconductor layer 102 is in contact with the semiconductor layer 106 of the write transistor Tr 0. In order to electrically isolate the first common electrode 104 from the semiconductor layer 102 and electrically isolate the second common electrode 105 from the first electrode 101, as shown in fig. 12, a gate dielectric layer 103 is provided between the first common electrode 104 and the semiconductor layer 102 and between the first common electrode 104 and the first electrode 101, that is, the gate dielectric layer 103 is provided in an L-shaped structure as shown in fig. 12. In addition, in order to electrically isolate the first common electrode 104 from the first electrode 101, a dielectric layer 109 is also provided between the second common electrode 105 and the first electrode 101.

The gate dielectric layer 103 and the dielectric layer 109 may be made of the same dielectric material, or may be made of different dielectric materials, for example, the gate dielectric layer 103 may be made of a material having a relatively high dielectric constant, and the dielectric layer 109 may be made of a material having a relatively low dielectric constant.

Fig. 13 is a cross-sectional view illustrating a further process structure of a memory cell 400 according to the present application. The memory cell shown in fig. 13 is identical to the memory cell 400 shown in fig. 12 described above in that: the first common electrode 104 is shared by the first pole of the write transistor Tr0 and the gate of the read transistor Tr1, and the second common electrode 105 is shared by the second pole of the write transistor Tr0 and the second pole of the read transistor Tr 1; in addition, the same points include: the channel formed in the write transistor Tr0 is a horizontal channel, the channel formed in the read transistor Tr1 is a vertical channel, and the semiconductor layer 102 is in ohmic contact with the first side surface M1 of the second common electrode 105.

Unlike the memory cell 400 shown in fig. 12 described above, the following is: in the read transistor Tr1, the first electrode 101 includes a first portion 101-1 and a second portion 101-2, wherein an extending direction of the first portion 101-1 (in a Z direction of fig. 13) is perpendicular to the substrate 100, and an extending direction of the second portion 101-2 (in an X direction of fig. 13) is parallel to the substrate 100, that is, as shown in fig. 13, the first electrode 101 has an L-shaped structure, and the first portion 101-1 is closer to the second common electrode 105 than the second portion 101-2, and the first portion 101-1 is in contact with the dielectric layer 109.

In the memory cell 400 shown in fig. 12 and 13, both the semiconductor layer 102 in the read transistor Tr1 and the semiconductor layer 106 in the write transistor Tr0 are in contact.

Fig. 14 is a cross-sectional view showing a process structure of another memory cell 400. The memory cell shown in fig. 14 is identical to the memory cell 400 shown in fig. 13 described above in that: the first common electrode 104 is shared by the first pole of the write transistor Tr0 and the gate of the read transistor Tr1, and the second common electrode 105 is shared by the second pole of the write transistor Tr0 and the second pole of the read transistor Tr 1; in addition, the same points include: the channel formed in the write transistor Tr0 is a horizontal channel, the channel formed in the read transistor Tr1 is a vertical channel, and the semiconductor layer 102 is in ohmic contact with the side surface M3 of the second common electrode 105.

Unlike the memory cell 400 shown in fig. 13 described above, the following is: the semiconductor layer 102 in the read transistor Tr1 and the semiconductor layer 106 in the write transistor Tr0 are not in contact, but a gate dielectric layer 103 is provided between the semiconductor layer 102 and the semiconductor layer 106.

Based on the above description of the memory cell 400 of several different structures of fig. 8, 12, 13 and 14, it can be easily seen from the process structural diagram that the write transistor Tr0 and the read transistor Tr1 are directly stacked together due to the common use of two electrodes, so that a wiring layer is not required between the write transistor Tr0 and the read transistor Tr 1. From the technical point of view, the process flow of the whole memory can be simplified, and the structure of the final memory is simplified.

Fig. 15 shows a structure of a conventional 2T0C memory cell that can realize three-dimensional stacking, and the 2T0C memory cell according to fig. 8, 12, 13 and 14 described above is compared with the 2T0C memory cell according to fig. 15, in which in fig. 15, in order to realize electrical connection of the write transistor Tr0 and the read transistor Tr1, a wiring layer needs to be formed between the write transistor Tr0 and the read transistor Tr1, for example, a dielectric layer is formed between the write transistor Tr0 and the read transistor Tr1, and conductive conduction is penetrated in the dielectric layer to electrically connect the write transistor Tr0 and the read transistor Tr1, however, the memory cell according to the present application does not need to provide a conductive path. In this way, the manufacturing process is simplified, the memory structure is simplified, and in addition, the signal intercommunication path between the writing transistor Tr0 and the reading transistor Tr1 can be shortened, so that the signal transmission efficiency is improved, and the reading and writing speed is further improved.

In some alternative process structures, in the 2T0C memory cells described above in relation to fig. 8, 12, 13, and 14, to reduce the probability of conductive material diffusion in the contact regions of the first and second poles (also referred to as source and drain) and the semiconductor layer in the transistor, the fermi pinning problem of the contact can be reduced by inserting an insulating layer at the contact interfaces of the first pole and the semiconductor layer, and the second pole and the semiconductor layer. I.e. the fermi pinning problem is alleviated by an insulating layer, where the thickness of the insulating layer may be 0.1-2 nm.

Materials that can be selected for the respective electrodes of the above-described write transistor Tr0 and read transistor Tr1 are described below.

The materials of the first common electrode 104, the second common electrode 105, the gate electrode 108 and the first electrode 101 are all conductive materials, such as metal materials. In an alternative embodiment, the material of the first and second electrodes 51 and 52 may be one or more of TiN (titanium nitride), ti (titanium), au (gold), W (tungsten), mo (molybdenum), in—ti—o (ITO, indium TiN oxide), al (aluminum), cu (copper), ru (ruthenium), ag (silver), and the like.

The materials of the semiconductor layer 106 and the semiconductor layer 102 may be Si (silicon), poly-Si (p-Si, polysilicon), amorphlus-Si (a-Si, amorphous silicon), in-Ga-Zn-O (IGZO, indium gallium zinc oxide) polynary, znO (zinc oxide), ITO (indium tin oxide), tiO ₂ (titanium dioxide), moS ₂ (molybdenum disulfide), WS ₂ One or more of semiconductor materials such as (tungsten disulfide).

When the storage isWhen the device 300 is a DRAM, the materials of the gate dielectric layer 107 and the gate dielectric layer 103 may be SiO ₂ (silica), al ₂ O ₃ (aluminum oxide), hfO ₂ (hafnium dioxide), zrO ₂ (zirconia) TiO ₂ (titanium dioxide), Y ₂ O ₃ (yttrium oxide) and Si ₃ N ₄ (silicon nitride) and the like.

The material of dielectric layer 109 may be SiO ₂ (silica), al ₂ O ₃ (aluminum oxide), hfO ₂ (hafnium dioxide), zrO ₂ (zirconia) TiO ₂ (titanium dioxide), Y ₂ O ₃ (yttrium oxide) and Si ₃ N ₄ (silicon nitride) and the like.

When the memory 300 is a ferroelectric random access memory FeRAM, the gate dielectric layer 107 and the gate dielectric layer 103 may be selected from ZrO ₂ (zirconia), hfO ₂ (hafnium dioxide), al doped HfO ₂ Si doped HfO ₂ Zr-doped HfO ₂ La doped HfO ₂ Y-doped HfO ₂ One or more of an isoferroelectric material or a material doped with other elements based on the material; the material of dielectric layer 109 may be SiO ₂ (silica), al ₂ O ₃ (aluminum oxide), hfO ₂ (hafnium dioxide), zrO ₂ (zirconia) TiO ₂ (titanium dioxide), Y ₂ O ₃ (yttrium oxide) and Si ₃ N ₄ (silicon nitride) and the like.

Specific preparation methods for preparing a plurality of different memory cell structures are provided, and are explained in detail below.

Fig. 16 is a flow chart of preparing a memory, which specifically includes the following steps:

step S1: a first transistor and a second transistor are formed on a substrate, the first transistor and the second transistor each include a gate, a first pole and a second pole, the first pole of the first transistor is electrically connected to the gate of the second transistor, and the second pole of the first transistor is electrically connected to the second pole of the second transistor.

Step S2: the first control line, the second control line and the third control line are formed, and the gate of the first transistor is electrically connected to the first control line, the first pole of the second transistor is electrically connected to the second control line, and the second pole of the electrically connected first transistor and the second pole of the second transistor are electrically connected to the third control line.

It should be noted that, the steps S1 and S2 are not limited to the process flow, and the step S1 is executed first and then the step S2 is executed. In some alternative process flows, step S1 and step S2 may be performed simultaneously; or part of the flow in the step S2 is performed simultaneously with the step S1; or the partial flow of step S1 is performed simultaneously with step S2.

The specific process flows involved in the steps S2 and S2 are described below with reference to the accompanying drawings.

Fig. 17a to 17e are cross-sectional views illustrating a process structure after each step in a process for manufacturing a memory cell according to the present application is completed.

As shown in fig. 17a, a first conductive layer 001, a first semiconductor material layer 002 and a second conductive layer 003 are sequentially formed over a substrate in a direction perpendicular to the substrate.

The first conductive layer 001 and the second conductive layer 003 may be made of a metal material, for example, one or more of TiN (titanium nitride), ti (titanium), au (gold), W (tungsten), mo (molybdenum), in—ti—o (ITO, indium TiN oxide), al (aluminum), cu (copper), ru (ruthenium), ag (silver), and the like.

The first semiconductor material layer 002 may be Si (silicon), poly-Si (p-Si, polysilicon), amorphos-Si (a-Si, amorphous silicon), in-Ga-Zn-O (IGZO, inGaZn oxide) polynary, znO (zinc oxide), ITO (indium tin oxide), tiO ₂ (titanium dioxide), moS ₂ (molybdenum disulfide), WS ₂ One or more of semiconductor materials such as (tungsten disulfide).

As shown in fig. 17b, a groove 004 is opened in the stacked first conductive layer 001, first semiconductor material layer 002, and second conductive layer 003, and the groove 004 penetrates through the second conductive layer 003, penetrating through a portion of the first semiconductor material layer 002. That is, the groove 004 penetrates only the second conductive layer 003, and does not penetrate the first semiconductor material layer 002.

As shown in fig. 17c, a first dielectric material layer 005 is formed on the bottom and side surfaces of the groove 004, and then a third conductive layer 006 is formed in the remaining space of the groove 004.

The optional materials of the third conductive layer 006 may be referred to the first conductive layer 001 and the second conductive layer 003, which are not described herein.

The first dielectric material layer 005 may be selected from SiO ₂ (silica), al ₂ O ₃ (aluminum oxide), hfO ₂ (hafnium dioxide), zrO ₂ (zirconia) TiO ₂ (titanium dioxide), Y ₂ O ₃ (yttrium oxide) and Si ₃ N ₄ (silicon nitride) and the like.

As shown in fig. 17d, a second semiconductor material layer 007, a second dielectric material layer 008 and a fourth conductive layer 009 are sequentially stacked on the second conductive layer 003 including the first dielectric material layer 005 and the third conductive layer 006.

For optional materials for the second semiconductor material layer 007, the second dielectric material layer 008, and the fourth conductive layer 009 of this process step, reference may be made to the corresponding semiconductor materials, dielectric materials, and conductive materials described above.

As shown in fig. 17e, the through hole 010 is opened such that the through hole 010 penetrates the fourth conductive layer 009, the second dielectric material layer 008, the second semiconductor material layer 007, the third conductive layer 006, the first dielectric material layer 005, the second conductive line layer 003, the first semiconductor material layer 002 and the first conductive layer 001 in this order. Thereby forming a stacked write transistor Tr0 and read transistor Tr1.

Fig. 18a to 18h are cross-sectional views illustrating a process structure after each step is completed in a process for manufacturing another memory cell according to the present application.

As shown in fig. 18a, a first conductive layer 001, a first dielectric material layer 005, and a second conductive layer 003 are sequentially formed over a substrate in a direction perpendicular to the substrate.

As shown in fig. 18b, a slot 004 is opened in the stacked first conductive layer 001, first dielectric material layer 005 and second conductive layer 003, and the slot 004 passes through the second conductive layer 003 and through the first dielectric material layer 005.

As shown in fig. 18c, a first semiconductor material layer 002 is formed on the bottom and side surfaces of the groove 004.

As shown in fig. 18d, the first semiconductor material layer 002 of the bottom surface of the groove 004 is removed.

As shown in fig. 18e, a second dielectric material layer 008 is formed on the bottom surface of the groove 004 and the side surface of the first semiconductor material layer 002, and a third conductive layer 006 is formed in the remaining space of the groove 004.

As shown in fig. 18f, the third conductive layer 006 and the second dielectric material layer 008 over the surface of the second conductive layer 003 are removed.

As shown in fig. 18g, the second semiconductor material layer 007, the third dielectric material layer 011 and the fourth conductive layer 009 are stacked in this order.

As shown in fig. 18h, the through hole 010 is opened such that the through hole 010 penetrates the fourth conductive layer 009, the third dielectric material layer 011, the second semiconductor material layer 007, the third conductive layer 006, the first dielectric material layer 005, the second conductive line layer 003, the first semiconductor material layer 002 and the first conductive layer 001 in this order. Thereby forming a stacked write transistor Tr0 and read transistor Tr1.

Fig. 19a to 19h are cross-sectional views illustrating a process structure after each step is completed in a process for manufacturing another memory cell according to the present application.

As shown in fig. 19a, a first conductive layer 001, a first dielectric material layer 005, and a second conductive layer 003 are sequentially formed over a substrate in a direction perpendicular to the substrate.

As shown in fig. 19b, a groove 004 is opened in the stacked first conductive layer 001, first dielectric material layer 005, and second conductive layer 003, and the groove 004 passes through the second conductive layer 003 and through the first dielectric material layer 005, and through a portion of the first conductive layer 001.

As shown in fig. 19c, a first semiconductor material layer 002 is formed on the bottom and side surfaces of the groove 004.

As shown in fig. 19d, the first semiconductor material layer 002 of the bottom surface of the groove 004 is removed.

As shown in fig. 19e, a second dielectric material layer 008 is formed on the bottom surface of the groove 004 and the side surface of the first semiconductor material layer 002, and a third conductive layer 006 is formed in the remaining space of the groove 004.

As shown in fig. 19f, the third conductive layer 006 and the second dielectric material layer 008 over the surface of the second conductive layer 003 are removed.

As shown in fig. 19g, the second semiconductor material layer 007, the third dielectric material layer 011 and the fourth conductive layer 009 are stacked in this order.

As shown in fig. 19h, the through hole 010 is opened such that the through hole 010 penetrates the fourth conductive layer 009, the third dielectric material layer 011, the second semiconductor material layer 007, the third conductive layer 006, the first dielectric material layer 005, the second conductive line layer 003, the first semiconductor material layer 002 and the first conductive layer 001 in this order. Thereby forming a stacked write transistor Tr0 and read transistor Tr1.

Fig. 20a to 20h are cross-sectional views illustrating a process structure after each step is completed in a process for manufacturing another memory cell according to the present application.

As shown in fig. 20a, a first conductive layer 001, a first dielectric material layer 005, and a second conductive layer 003 are sequentially formed over a substrate in a direction perpendicular to the substrate.

As shown in fig. 20b, a slot 004 is opened in the stacked first conductive layer 001, first dielectric material layer 005 and second conductive layer 003, and the slot 004 passes through the second conductive layer 003 and through the first dielectric material layer 005, and through a portion of the first conductive layer 001.

As shown in fig. 20c, a first semiconductor material layer 002 is formed on the bottom and side surfaces of the groove 004.

As shown in fig. 20d, the first semiconductor material layer 002 near the trench opening is removed from the bottom surface of the trench 004 and the side surface of the trench 004.

As shown in fig. 20e, a second dielectric material layer 008 is formed on the bottom surface of the groove 004 and the side surface of the first semiconductor material layer 002, and a third conductive layer 006 is formed in the remaining space of the groove 004.

As shown in fig. 20f, the third conductive layer 006 and the second dielectric material layer 008 over the surface of the second conductive layer 003 are removed.

As shown in fig. 20g, the second semiconductor material layer 007, the third dielectric material layer 011 and the fourth conductive layer 009 are stacked in this order.

As shown in fig. 20h, the through hole 010 is opened such that the through hole 010 penetrates the fourth conductive layer 009, the third dielectric material layer 011, the second semiconductor material layer 007, the third conductive layer 006, the first dielectric material layer 005, the second conductive line layer 003, the first semiconductor material layer 002 and the first conductive layer 001 in this order. Thereby forming a stacked write transistor Tr0 and read transistor Tr1.

The foregoing gives a corresponding method of making four different structures of memory cells, although in alternative embodiments other methods may be used to make the electrode-shared write and read transistor structures referred to herein.

In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A memory, comprising:

a substrate;

at least one memory cell formed on the substrate, the memory cell comprising:

a first transistor and a second transistor, each of the first transistor and the second transistor comprising a gate, a first pole, and a second pole;

a first control line, a second control line, and a third control line;

wherein a first pole of the first transistor is electrically connected with a gate of the second transistor, a second pole of the first transistor is electrically connected with a second pole of the second transistor, and a gate of the first transistor is electrically connected with the first control line;

the first pole of the second transistor is electrically connected to the second control line, and the second pole of the first transistor and the second pole of the second transistor which are electrically connected to the third control line.
The memory of claim 1, wherein the first transistor and the second transistor are stacked in a direction perpendicular to the substrate.
The memory according to claim 1 or 2, wherein a gate of the second transistor shares a same electrode as a first pole of the first transistor, an electrode shared by the gate of the second transistor and the first pole of the first transistor is a first common electrode, a second pole of the second transistor shares a same electrode as a second pole of the first transistor, and an electrode shared by the second pole of the second transistor and the second pole of the first transistor is a second common electrode.
The memory of claim 3, wherein,

the second common electrode has a first side perpendicular to the substrate and a second side parallel to the substrate;

the first common electrode is positioned on one side of the first side face facing to the first side face;

the first electrode of the second transistor is positioned on the side facing the second side face;

the gate of the first transistor is located on a side of the first and second common electrodes that is remote from the first pole of the second transistor.
The memory of claim 4, wherein the second transistor further comprises a semiconductor layer;

in the second transistor, the semiconductor layer includes a first semiconductor portion and a second semiconductor portion that are in contact with each other, and an extension direction of the first semiconductor portion is perpendicular to the substrate and an extension direction of the second semiconductor portion is parallel to the substrate;

the first semiconductor portion is in contact with the second side, and the second semiconductor portion is in contact with a third side;

the third side is a face of the first electrode of the second transistor facing the second common electrode.
The memory of claim 5 wherein the second transistor further comprises a gate dielectric layer;

the first common electrode and the second common electrode, the first common electrode and the first semiconductor part, and the first common electrode and the second semiconductor part are isolated by the gate dielectric layer.
The memory of claim 4, wherein the second transistor further comprises a semiconductor layer;

in the second transistor, the semiconductor layer includes a first semiconductor portion, an extending direction of which is perpendicular to the substrate;

an end of the first semiconductor portion near the second common electrode is in contact with the first side surface, and an end of the first semiconductor portion near the first electrode of the second transistor is in contact with a third side surface;

the third side is a face of the first electrode of the second transistor facing the second common electrode.
The memory of claim 7 wherein the second transistor further comprises a gate dielectric layer and a dielectric layer;

the first common electrode and the first semiconductor part, the first common electrode and the first electrode of the second transistor are separated by the gate dielectric layer, and the second common electrode and the first electrode of the second transistor are separated by the dielectric layer.
The memory according to claim 7 or 8, wherein the first pole of the second transistor comprises a first portion and a second portion in contact, the first portion extending in a direction perpendicular to the substrate, the second portion extending in a direction parallel to the substrate, the first portion being disposed close to the second common electrode with respect to the second portion.
The memory according to any one of claims 7 to 9, wherein in the first transistor, the semiconductor layer is provided on a side of the first common electrode and the second common electrode away from a first pole of the second transistor;

the first semiconductor portion is in contact with a semiconductor layer of the first transistor; or,

the first semiconductor portion is isolated from the semiconductor layer of the first transistor by a gate dielectric layer.
The memory according to any one of claims 4 to 10, wherein the first transistor further comprises a semiconductor layer and a gate dielectric layer;

in the first transistor, the gate electrode, the gate dielectric layer and the semiconductor layer are arranged on one side of the first common electrode and the second common electrode, which is far away from the first electrode of the second transistor, and the gate electrode, the gate dielectric layer and the semiconductor layer are sequentially stacked along the direction perpendicular to the substrate, and the semiconductor layer is contacted with the first common electrode and the second common electrode.
The memory according to any one of claims 3 to 11, wherein the memory cell has a plurality of;

the first control line and the second control line extend along a first direction parallel to the substrate, the first control line is electrically connected with the gates of the first transistors of the memory cells located in the first direction, and the second control line is electrically connected with the first poles of the second transistors of the memory cells located in the first direction;

the third control line extends along a second direction parallel to the substrate, and is electrically connected with second poles of the second transistors of the memory cells located in the second direction;

the second direction is perpendicular to the first direction.
The memory of any of claims 1-12, wherein the first transistor, the second transistor, the first control line, the second control line, and the third control line are each formed on the substrate using a subsequent process.
The memory according to any of claims 1-13, wherein,

in the writing stage, the first control line is used for receiving a first writing word line control signal so that the first transistor is turned on, and the third control line is used for receiving a writing bit line control signal so as to write logic information into the memory cell.
The memory according to any one of claims 1 to 14, wherein,

in a reading stage, the first control line is used for receiving a second write word line control signal so that the first transistor is turned off, the third control line is used for receiving a read word line control signal, and the second control line is used for outputting a signal to read logic information in the memory cell.
A method of controlling a memory, the memory comprising:

at least one memory cell, the memory cell comprising:

a first transistor and a second transistor, each of the first transistor and the second transistor comprising a gate, a first pole, and a second pole;

a first control line, a second control line, and a third control line;

wherein a first pole of the first transistor is electrically connected with a gate of the second transistor, a second pole of the first transistor is electrically connected with a second pole of the second transistor, and a gate of the first transistor is electrically connected with the first control line;

a first electrode of the second transistor is electrically connected with the second control line, and a second electrode of the first transistor and a second electrode of the second transistor which are electrically connected with the third control line;

The control method comprises the following steps:

in the writing stage, the first control line is used for receiving a first writing word line control signal so that the first transistor is turned on, and the third control line is used for receiving a writing bit line control signal so as to write logic information into the memory cell.
The control method of a memory according to claim 16, characterized in that the control method further comprises:

in a reading stage, the first control line is used for receiving a second write word line control signal so that the first transistor is turned off, the third control line is used for receiving a read word line control signal, and the second control line is used for outputting a signal to read logic information in the memory cell.
The method according to claim 16 or 17, wherein the first transistor and the second transistor are stacked in a direction perpendicular to a substrate.
The method for controlling a memory according to claim 17, wherein,

the gate of the second transistor shares the same electrode as the first pole of the first transistor, and the second pole of the second transistor shares the same electrode as the second pole of the first transistor.
A method of forming a memory, the method comprising:

forming a first transistor and a second transistor on a substrate, wherein the first transistor and the second transistor each comprise a gate electrode, a first electrode and a second electrode, the first electrode of the first transistor is electrically connected with the gate electrode of the second transistor, and the second electrode of the first transistor is electrically connected with the second electrode of the second transistor;

a first control line, a second control line and a third control line are formed, the gate of the first transistor is electrically connected with the first control line, the first pole of the second transistor is electrically connected with the second control line, and the second pole of the first transistor and the second pole of the second transistor which are electrically connected with the third control line.
The method of forming a memory of claim 20, wherein forming the first transistor and the second transistor on the substrate comprises:

the first transistor and the second transistor are stacked in a direction perpendicular to the substrate.
The method of claim 21, wherein the memory is formed by a process of forming a semiconductor device,

in forming the second transistor, comprising:

Forming a first pole of the second transistor;

forming a gate and a second pole on a side of a first pole of the second transistor away from the substrate, the second pole having a first side perpendicular to the substrate, the gate being located on a side of the first side facing;

in forming the first transistor, comprising:

and forming a gate of the first transistor on one side of the gate and the second pole far away from the substrate, wherein the gate of the second transistor and the first pole of the first transistor share the same electrode, and the second pole of the second transistor and the second pole of the first transistor share the same electrode.
An electronic device, comprising:

a processor; and

a memory according to any one of claims 1 to 15, or a memory manufactured by a method of forming a memory according to any one of claims 20 to 22;

wherein the processor and the memory are electrically connected.