WO2023221582A1 - Storage array and preparation method for storage array - Google Patents

Abstract

Embodiments of the present application provide a memory. The memory comprises: a transistor layer, comprising a plate line and multiple transistors arranged in row and column directions, the plate line being connected to first electrodes of multiple transistors in the row direction; a polycrystalline layer that is located above the transistor layer and comprises word lines in the row direction; a capacitor layer that is located above the polycrystalline layer and comprises multiple capacitors arranged in the row and column directions, each capacitor comprising a first electrode plate and a second electrode plate; and a metal layer that is located above the capacitor layer and comprises a first wire, a second wire, and a bit line in the column direction. The plate line is connected to the first wire, the word lines are connected to the second wire, the first electrode plates of the capacitors are connected to the second electrodes of the corresponding transistors, and the second electrode plates of the capacitors are connected to the bit line. According to the technical solution of the present application, the electrodes of the multiple transistors can be connected together by means of the plate line for electrode sharing, thereby simplifying the interconnection line layout in a memory array structure, and improving the arrangement density of capacitors in the capacitor layer.

Description

Storage array and preparation method of storage array

This application claims priority to the Chinese patent application filed with the China Patent Office on May 17, 2022, with the application number 202210531950.1 and the application name "Storage Array and Preparation Method of Storage Array", the entire content of which is incorporated into this application by reference. middle.

Technical field

Embodiments of the present application relate to the field of semiconductor devices, and specifically relate to a memory array and a method for manufacturing the memory array.

Background technique

In the information age, technology continues to evolve, and people pay more and more attention to data storage, constantly pursuing high reliability, high-speed reading, large capacity and low power consumption storage devices. As a new type of non-volatile memory, memory with a transistor and capacitor structure has many advantages in terms of power consumption, cost, read and write speed, erase and write times, and radiation resistance. It is expected to replace traditional flash memory and dynamic random access memory (dynamic random access memory). random-access memory, DRAM).

The area of the capacitor affects memory performance and reliability. With the continuous development of manufacturing processes, the size of memories continues to shrink, and the layout of interconnect lines in the memory array structure has gradually become a bottleneck limiting the area of capacitors.

Therefore, how to increase the arrangement density of capacitors in the capacitor layer is an urgent problem to be solved.

Contents of the invention

Embodiments of the present application provide a memory array and a method for manufacturing the memory array, which can simplify the interconnection line layout in the memory array structure, thereby increasing the arrangement density of capacitors in the capacitor layer.

In a first aspect, a memory array is provided, including: a transistor layer, including a plurality of transistors arranged in a row direction and a column direction, each of the plurality of transistors including a first electrode and a second electrode, so The first electrode is a source and the second electrode is a drain, or the first electrode is a drain and the second electrode is a source; the transistor layer also includes a plate line, and the plate line is connected the first electrodes of the plurality of transistors in the row direction; a polycrystalline layer located on the transistor layer for setting a word line along the row direction; a capacitor layer located on the On the polycrystalline layer, a plurality of capacitors arranged along the row direction and along the column direction are included, each capacitor in the plurality of capacitors includes a first plate and a second plate; a metal layer is located on On the capacitor layer, a bit line, a first conductor line and a second conductor line are provided, and the bit line is along the column direction; the plate line is connected to the first conductor line of the metal layer, and the The word line is connected to the second conductor of the metal layer, the first plate of each capacitor is connected to the second electrode of the corresponding transistor, and the second plate of each capacitor Connected to the bit line of the metal layer.

The plate line (PL) in the embodiment of the present application is located on the transistor layer, and the first electrodes of one or more rows of transistors are shared through the plate line, so there is no need to connect the first electrode of the transistor in each memory unit to The wires of the top metal layer, and the multiple transistors sharing the first electrode in the row direction only need to connect the first electrode of one of the transistors to the wires of the top metal layer to realize the connection between the multiple transistors in the row direction and the wires in the top metal layer. connect. Therefore, the interconnection line layout in the memory array structure is simplified and the arrangement density of capacitors in the capacitor layer is increased.

It should be understood that the memory in this application includes a memory whose basic storage unit is a transistor plus capacitor structure. Alternatively, it may be a non-volatile memory such as a ferroelectric memory, a resistive random access memory, a phase change random access memory or a magnetoresistive random access memory.

It should be understood that the row direction and column direction in this application are relative concepts, referring to two directions that are perpendicular to each other. Those skilled in the art can also reversely apply the row direction and column direction in the technical solution of this application. The specific row and column directions should not be construed as limitations on this application.

It should be understood that due to the symmetry of the source (source, S) and drain (drain, D) of the transistor, the plate line can connect the first electrodes of multiple transistors in the row direction, and can also connect the first electrodes of the transistors in the row direction. the second electrodes of a plurality of transistors.

The first electrodes of the transistors in each row can be connected together through a plate line, that is, the transistors located in the same row share the first electrode. Optionally, a plate line can also connect the first electrodes of two adjacent rows of transistors, that is, the transistors located in two adjacent rows share the first electrode.

It should be understood that the metal layer is the top metal layer, and embodiments of the present application may also include other metal layers, and other metal layers play a conductive role. Board lines and word lines (WL) can be connected to the wires of the top metal layer through conductive media. For example, plate lines and word lines may be connected to wires of the top metal layer through contact holes filled with conductive dielectric and other metal layers.

It should be understood that the memory cell array structure of the memory of this application can be a transistor and one capacitor (1T1C) structure, that is, each memory cell in the memory cell array includes a transistor and a capacitor. Optionally, the embodiments of this application can also be applied to an array structure in which the memory cells are 2T2C and nTmC. This application does not limit this. n and m are integers greater than or equal to 1.

It should be understood that the capacitor may include a first plate, a second plate, and a capacitive dielectric layer located between the first plate and the second plate. The first plate of the capacitor is connected to the second electrode of the corresponding transistor. It should be understood that the corresponding transistor refers to a transistor located in the same memory unit as the capacitor, and may be one transistor or multiple transistors. For example, the first plate of one capacitor can be connected to the second electrode of one or more transistors located in the same memory unit, or the first plates of multiple capacitors can be connected to one or more transistors located in the same memory unit. The second electrode is connected, and the specific connection method is not limited in this application.

It should be understood that the plate line is connected to the first conductor in the top metal layer through the conductive medium, the word line is connected to the second conductor in the top metal layer through the conductive medium, and the second plate of the capacitor is connected to the second conductor in the top metal layer through the conductive medium. bit line connection. It should be understood that bit lines are also wires. The first conductive line, the second conductive line and the bit line do not interfere with each other. The controller accesses the memory array through the first conductor, the second conductor and the bit line.

In the embodiment of the present application, since the first electrodes of one or more rows of transistors are shared through board lines, there is no need to connect the first electrodes of the transistors in each memory unit to the wires of the top metal layer. The transistors sharing the first electrode only need to connect the first electrode of one of the transistors to the wire in the top metal layer to realize the connection between multiple transistors in the row direction and the wire in the top metal layer. Therefore, the interconnection line layout in the memory array structure is simplified and the arrangement density of capacitors in the capacitor layer is increased.

In conjunction with the first aspect, in some possible implementations, the first plate of each capacitor is connected to the second electrode of the corresponding transistor through a first contact hole, and all the electrodes of each capacitor are The second electrode plate is connected to the bit line in the metal layer through a second contact hole, and the first contact hole and the second contact hole include a conductive medium.

It should be understood that the first contact hole and the second contact hole are both through holes filled with conductive medium. They are substantially the same and should not be confused with each other. understood as a limitation on this application. Optionally, the first contact hole and the second contact hole in the embodiment of the present application can also be replaced with other conductive materials or given other names, and the present application does not limit this.

In the embodiment of the present application, since the first electrodes of one or more rows of transistors are shared through board lines, there is no need to connect the first electrodes of the transistors in each memory unit to the wires of the top metal layer through contact holes along the row direction. The multiple transistors sharing the first electrode only need one contact hole to be connected to the wire in the top metal layer to realize the connection between the multiple transistors in the row direction and the wire in the top metal layer. Therefore, compared with the existing solution, the contact holes between the transistor layer and the metal layer are reduced, and the area of the capacitors arranged in the unit area is increased.

In conjunction with the first aspect, in some possible implementations, the first contact hole is perpendicular to the first electrode plate, and the second contact hole is perpendicular to the second electrode plate.

It should be understood that the first plate of each capacitor is connected to the second electrode of the corresponding transistor through a first contact hole perpendicular to the first plate, and the second plate of each capacitor is connected to the second electrode of the corresponding transistor through a first contact hole perpendicular to the second plate. The second contact hole is connected to the bit line (BL) in the metal layer.

In the embodiment of the present application, the first contact hole and the second contact hole are perpendicular to the two plates of the capacitor, which makes the arrangement of the contact holes and the capacitor in the memory more regular and reduces the impact of irregular wiring methods on the memory band. As a result, the area of capacitors arranged per unit area is increased.

With reference to the first aspect, in some possible implementations, it is characterized in that the transistor layer includes P plate lines, the P plate lines are along the row direction, and P is an integer greater than or equal to 2.

It should be understood that the memory cell array stored in the present application may include multiple rows of memory cells, and the first electrodes of the transistors in each row of memory cells are connected together through a plate line.

In the embodiment of the present application, since the first electrodes of one or more rows of transistors are shared through board lines, there is no need to connect the first electrodes of the transistors in each memory cell to the wires of the top metal layer. The transistors sharing the first electrode only need to connect the first electrode of one of the transistors to the wire in the top metal layer to realize the connection between multiple transistors in the row direction and the wire in the top metal layer. Therefore, the interconnection line layout in the memory array structure is simplified and the arrangement density of capacitors in the capacitor layer is increased.

In conjunction with the first aspect, in some possible implementations, at least two of the P plate lines are connected together through plate lines along the column direction.

In the embodiment of the present application, plate lines along the column direction can be used to connect at least two of the P plate lines together, so that the first electrodes of the transistors in multiple rows of memory cells can be connected together to achieve first electrode sharing. Multiple rows of transistors sharing a first electrode only need to connect the first electrode of one of the transistors to a wire in the top metal layer to realize the connection between the multiple rows of transistors and the wires in the top metal layer, thus simplifying the interconnection lines in the memory array structure The layout improves the arrangement density of capacitors on the capacitor layer.

For example, the 0th plate line, the 1st plate line... the Pth plate line in the storage array can be connected using a plate line along the column direction, so that the first of the transistors in all memory cells The electrodes can be connected together to achieve first electrode sharing. The entire memory cell array only needs the first electrode of one transistor to be connected to the wire of the top metal layer, which can realize the physical connection of the transistor layer and the wires in the metal layer of all memory cells, simplifying the interconnection line layout in the memory array structure. The arrangement density of capacitors in the capacitor layer is increased.

Combined with the first aspect, in some possible implementations, the k-th plate line of the P plate lines is connected to the first electrode of the 2k-1th row and the 2k-th row transistor in the row direction, k is An integer greater than or equal to 1 and less than or equal to P.

It should be understood that the memory cell located in the 2kth row and the memory cell located in the 2k+1th row in the memory cell array are The first electrodes of the transistors can be commonly connected to the k-th plate line of the P plate lines, that is, the transistors of two adjacent rows of memory cells are connected together through one plate line.

In the embodiment of the present application, the transistors of two adjacent rows of memory cells are connected together through a plate line, which not only reduces and simplifies the wiring of the plate lines in the row direction, but also requires only the first electrode of the transistors in multiple rows of one of the transistors. One electrode is connected to a wire in the top metal layer to connect multiple rows of transistors to the wires in the top metal layer, simplifying the layout of interconnect lines in the memory array structure and increasing the density of capacitors in the capacitor layer.

With reference to the first aspect, in some possible implementations, the plate lines include active area wiring, and the active area wiring includes forming conductive channels through ion implantation.

It should be understood that the active area is in the transistor layer. The area where the transistors are distributed on the silicon wafer is the active area. A conductive channel is formed in the active area through ion implantation. That is, the first node of the transistor located in the same row in the memory array can be The electrodes are connected together. This method of using the conductive channels in the active area as the interconnection lines of the memory array can reduce the distribution of interconnection lines in the memory.

A second aspect provides a memory, including a storage controller and the storage array described in the first aspect, and the storage controller is electrically connected to the storage array.

The memory controller accesses the memory array described in the first aspect through the first conductor line, the second conductor line and the bit line.

A third aspect provides an electronic device, including a circuit board and the memory described in the second aspect, where the memory is disposed on the circuit board and electrically connected to the circuit board.

In a fourth aspect, a method for manufacturing a memory is provided, including: forming a transistor layer, the transistor layer including a plate line and a plurality of transistors arranged in a row direction and a column direction, each of the plurality of transistors including A first electrode and a second electrode, the first electrode is a source electrode and the second electrode is a drain electrode, or the first electrode is a drain electrode and the second electrode is a source electrode, and the plate line is connected the first electrodes of the plurality of transistors in the row direction; forming a polycrystalline layer on the transistor layer, the polycrystalline layer being used to set a word line, the word line being along the row direction; A capacitor layer is formed on the polycrystalline layer. The capacitor layer includes a plurality of capacitors arranged along the row direction and the column direction. Each capacitor in the plurality of capacitors includes a first plate and a third plate. A diode plate, the first plate of each capacitor is connected to the second electrode of the corresponding transistor; a metal layer is formed on the capacitor layer, and the metal layer is used to set the bit line, the first and a second conductor, the bit line is along the column direction, the bit line is connected to the second plate of each capacitor, the first conductor is connected to the plate line, and the second conductor Connect the word lines.

It should be understood that the transistor layer is located on the semiconductor substrate. Before forming the transistor layer, the surface oxide of the substrate can be first removed, and then the first electrode, the second electrode and the plate line area of the transistor are positioned, and ions are implanted into the designated areas. The first electrode, the second electrode and the plate line area form the first electrode, the second electrode and the plate line of the transistor, wherein the first electrodes of one or more rows of transistors located in the same direction can be connected together through the plate lines.

In the formed polycrystalline layer, gates (G) of transistors in the same row are connected together, that is, word lines of the memory cell array distributed in the polycrystalline layer are formed.

In the embodiment of the present application, since the first electrodes of one or more rows of transistors are shared through board lines, there is no need to connect the first electrodes of the transistors in each memory unit to the wires of the top metal layer. The transistors sharing the first electrode only need to connect the first electrode of one of the transistors to the wire in the top metal layer to realize the connection between multiple transistors in the row direction and the wire in the top metal layer. Therefore, the interconnection line layout in the memory array structure is simplified and the arrangement density of capacitors in the capacitor layer is increased.

In conjunction with the fourth aspect, in some possible implementations, the method further includes: forming a first contact hole and a second Contact holes, the first plate of each capacitor is connected to the second electrode of the corresponding transistor through the first contact hole, and the second plate of each capacitor is connected through the A second contact hole is connected to the bit line in the metal layer, and the first contact hole and the second contact hole include a conductive medium.

It should be understood that the first contact hole and the second contact hole are both through holes filled with conductive medium, and they are substantially the same. The first contact hole and the second contact hole may be formed by drilling holes in a precipitated oxide and then filling them with a conductive medium. It should be understood that an isolating oxide is deposited between the substrate and the top metal layer in the memory.

In the embodiment of the present application, since the first electrodes of one or more rows of transistors are shared through board lines, there is no need to connect the first electrodes of the transistors in each memory unit to the wires of the top metal layer through contact holes along the row direction. The multiple transistors sharing the first electrode only need one contact hole to be connected to the wire in the top metal layer to realize the connection between the multiple transistors in the row direction and the wire in the top metal layer. Therefore, compared with the existing solution, the contact holes between the transistor layer and the metal layer are reduced, and the area of the capacitors arranged in the unit area is increased.

In conjunction with the fourth aspect, in some possible implementations, forming the first contact hole and the second contact hole includes: forming the first contact hole perpendicular to the first plate; forming the first contact hole perpendicular to the first plate; The second contact hole of the second electrode plate.

In the embodiment of the present application, the first contact hole and the second contact hole are perpendicular to the two plates of the capacitor, which makes the arrangement of the contact holes and the capacitor in the memory more regular and reduces the impact of irregular wiring methods on the memory band. As a result, the area of capacitors arranged per unit area is increased.

Combined with the fourth aspect, in some possible implementations, the transistor layer includes P plate lines, the P plate lines are along the row direction, and P is an integer greater than or equal to 2.

It should be understood that the P plate lines are located in the transistor layer. When forming the transistor layer, the plate line area can be determined first, and then a conductive channel is formed by ion implantation into the plate line area. The formed conductive channel is the plate line. The first electrodes of the transistors in each row of memory cells are connected together by a plate line.

In the embodiment of the present application, since the first electrodes of one or more rows of transistors are shared through board lines, there is no need to connect the first electrodes of the transistors in each memory unit to the wires of the top metal layer. The transistors sharing the first electrode only need to connect the first electrode of one of the transistors to the wire in the top metal layer to realize the connection between multiple transistors in the row direction and the wire in the top metal layer. Therefore, the interconnection line layout in the memory array structure is simplified and the arrangement density of capacitors in the capacitor layer is increased.

In conjunction with the fourth aspect, in some possible implementations, at least two of the P plate lines are connected together through plate lines along the column direction.

Optionally, the plate lines along the column direction may be conductive channels formed by ion implantation, or connection lines formed of conductive materials such as metal.

In the embodiment of the present application, plate lines along the column direction can be used to connect at least two of the P plate lines together, so that the first electrodes of the transistors in multiple rows of memory cells can be connected together to achieve first electrode sharing. Multiple rows of transistors sharing a first electrode only need the first electrode of one of the transistors to be connected to the top metal layer to realize the connection between multiple rows of transistors and the wires in the top metal layer, simplifying the interconnection line layout in the memory array structure and improving The arrangement density of capacitors in the capacitor layer.

Combined with the fourth aspect, in some possible implementations, the k-th plate line of the P plate lines is connected to the first electrode of the 2k-1th row and the 2k-th row transistor in the row direction, k is An integer greater than or equal to 1 and less than or equal to P.

It should be understood that the first electrodes of the transistors of the memory unit located in row 2k and the memory unit located in row 2k+1 in the memory cell array may be commonly connected to the k-th plate line of the P plate lines, that is, adjacent Two rows of memory cell transistors connected together via a board wire.

In the embodiment of the present application, the transistors of two adjacent rows of memory cells are connected together through a plate line, which not only simplifies the wiring of the plate lines in the row direction, but also requires only the first electrode of one of the transistors to be shared by multiple rows of transistors. By connecting the electrodes to the wires in the top metal layer, the connection between the multi-row transistors and the wires in the top metal layer can be realized, which simplifies the interconnection line layout in the memory array structure and improves the arrangement density of capacitors in the capacitor layer.

In conjunction with the fourth aspect, in some possible implementations, the plate lines include active area wiring, and the active area wiring includes forming conductive channels through ion implantation.

It should be understood that the active area is in the transistor layer. The area where the transistors are distributed on the silicon wafer is the active area. A conductive channel is formed in the active area through ion implantation. That is, the first node of the transistor located in the same row in the memory array can be The electrodes are connected together. This method of using the conductive channels in the active area as the interconnection lines of the memory array can reduce the distribution of interconnection lines in the memory.

Description of the drawings

FIG. 1 is a schematic diagram of the hierarchical structure of a memory along the bit line direction provided by the prior art.

FIG. 2 is a schematic circuit diagram of a memory array structure provided by the prior art.

FIG. 3 is a schematic diagram of a hierarchical structure of a memory provided by an embodiment of the present application.

FIG. 4 is a schematic diagram of the hierarchical structure of a memory along the bit line direction provided by an embodiment of the present application.

FIG. 5 is a schematic circuit diagram of a memory array structure provided by an embodiment of the present application.

FIG. 6 is a schematic circuit diagram of another memory array structure provided by an embodiment of the present application.

FIG. 7 is a schematic circuit diagram of another memory array structure provided by an embodiment of the present application.

FIG. 8 is a schematic structural diagram of an interconnection line of a memory provided by an embodiment of the present application.

FIG. 9 is a schematic flow chart of a memory preparation process provided by an embodiment of the present application.

FIG. 10 is a schematic circuit diagram of another memory array structure provided by an embodiment of the present application.

FIG. 11 is a schematic diagram of an active area layout provided by an embodiment of the present application.

Figure 12 is a schematic diagram of an ion implantation active region provided by an embodiment of the present application.

Figure 13 is a schematic diagram of a precipitated oxide and polycrystalline layer provided by an embodiment of the present application.

Figure 14 is a schematic diagram of a perforated and deposited capacitor layer provided by an embodiment of the present application.

FIG. 15 is a schematic diagram of drilling and depositing a metal layer according to an embodiment of the present application.

FIG. 16 is a schematic diagram of the hierarchical structure along the bit line direction of another memory provided by an embodiment of the present application.

FIG. 17 is a schematic structural diagram of an interconnection line of another memory provided by an embodiment of the present application.

FIG. 18 is a schematic diagram of the hierarchical structure of a memory along the metal layer line direction provided by an embodiment of the present application.

FIG. 19 is a schematic circuit diagram of another memory array structure provided by an embodiment of the present application.

Detailed ways

With the continuous evolution of technology in the information age, people are paying more and more attention to data storage, and are constantly pursuing high reliability, high-speed reading, large capacity and low power consumption storage devices. As a new type of non-volatile memory, memory with a transistor and capacitor structure has many advantages in terms of power consumption, cost, read and write speed, erase and write times, and radiation resistance. It is expected to replace traditional flash memory and dynamic random access memory.

Common capacitors include ferroelectric capacitors, but traditional ferroelectric materials based on perovskite structures (lead zirconate titanate, tantalum (strontium bismuth phosphate, etc.) have complex chemical compositions, low compatibility with complementary metal-oxide semiconductor (CMOS) processes, and ferroelectric devices prepared with such materials have obvious size effects and cannot be further miniaturized and integrated into Advanced process nodes, so it can only be used in some small-capacity memories. It should be understood that the size effect refers to the effect that when the size of a material is reduced to a certain extent, its properties undergo a sudden change.

In recent years, the discovery of hafnium-based ferroelectric materials has greatly reduced the size of ferroelectric devices, and hafnium-based materials have good compatibility with advanced CMOS processes, attracting extensive research by researchers. Ferroelectric random-access memory (FRAM) among commonly used ferroelectric memories is composed of a transistor and a capacitor (one transistor and one capacitor, 1T1C). It is similar to DRAM in structure and reading and writing methods, and corresponds to The array structure and layout structure are also similar. During the preparation process of new hafnium-based ferroelectric materials, the annealing process requires high temperatures, exceeding 500°C. Therefore, the ferroelectric capacitor structure needs to be integrated at the front end of the process. Ferroelectric capacitors are generally arranged between the drain and the metal. Above the contact holes of the layer, the metal layer is connected above the ferroelectric capacitor.

In a memory with a transistor plus capacitor structure, the area of the capacitor affects the performance and reliability of the memory. As device sizes continue to shrink, the layout of interconnect lines in memory array structures has gradually become a bottleneck limiting capacitor area. FIG. 1 is a schematic diagram of the hierarchical structure of a memory along the bit line direction provided by the prior art. The transistor 110 includes a source S, a drain D and a gate G, and the capacitor includes an upper plate 133 , a lower plate 131 and a capacitive dielectric layer 132 . The interconnection lines included in the memory array structure of the prior art solution are word lines WL, bit lines BL and plate lines PL, where PL and BL are distributed in the metal layer. The BL shown in Figure 1 is distributed in the metal layer 140, and the PL is distributed in Metal layer 142. PL is connected to the upper plate 133 of the capacitor through the contact hole 152, the lower plate 131 of the capacitor is connected to the source S of the transistor 110 through the contact hole 151, and the drain D of the transistor 110 is connected through the contact hole 151, the contact hole 152, and the metal Layer 141 and metal layer 142 are connected to BL located on the top metal layer 140, and the gate G of transistor 110 is connected to the word line WL of the memory array.

FIG. 2 is a schematic circuit diagram of a memory array structure provided by the prior art. Figure 2 is a schematic circuit diagram corresponding to the memory shown in Figure 1. The memory array includes 4×2=8 memory cells. The interconnection lines of the memory array include WL, PL and BL, WL is connected to the gates of the transistors of the memory cells in the same row, PL is connected to the upper plate 133 of the capacitor of the memory cells in the same row, and BL is connected to the drains of the transistors of the memory cells in the same column. , the source of the transistor is connected to the lower plate 131 of the capacitor located in the same memory cell. Access to any individual memory cell of the memory array can be achieved using interconnect lines. Among them, WL can choose to turn on the transistor of the corresponding memory unit, and then combines PL and BL to realize access and storage of the selected memory unit.

In the existing technology, PL and BL need to use contact holes to realize the physical connection between the wires and the transistor layer in the metal layer. Corresponding to each memory cell, two different contact holes, BL and PL, need to be distributed, and the capacitor layer is distributed in the metal layer. and the transistor layer, so the distribution of contact holes limits the layout of the capacitors in the capacitor layer, which also limits the area of the capacitors, that is, the arrangement density of the capacitors is greatly restricted. Therefore, how to improve the capacitor arrangement density of the capacitor layer is an urgent problem to be solved.

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts should fall within the scope of protection of this application.

It should be understood that the drawings in this application are not necessarily drawn to scale, and the straight lines or right angles in the figures may appear to be less than perfect straight lines or right angles during the integrated circuit manufacturing process. Memory locales may have surface topology or other non-smoothness issues due to practical limitations of the processing equipment and technology used.

FIG. 3 is a schematic diagram of a hierarchical structure of a memory provided by an embodiment of the present application.

From bottom to top, the hierarchical structure is a transistor layer 210 - a polycrystalline layer 220 - a capacitor layer 230 - a metal layer 240. The transistor layer 210 includes a plurality of transistors arranged in the row direction and the column direction, each transistor includes a first electrode and a second electrode, the first electrode is a source electrode and the second electrode is a drain electrode, or the first electrode is a drain electrode. pole and the second electrode is the source. The plate line PL is distributed on the transistor layer 210 and connects the first electrodes of the plurality of transistors in the row direction. Polycrystalline layer 220 is used to set word lines WL, WL along the row direction. The capacitor layer 230 includes a plurality of capacitors arranged in the row direction and the column direction, and each capacitor includes an upper plate and a lower plate. The metal layer 240 is located on the top layer and is used to set the bit lines BL along the column direction. PL and WL are connected to the wires in the metal layer 240 through the conductive medium 250, the lower plate of the capacitor in the capacitor layer 230 is connected to the second electrode of the corresponding transistor through the conductive medium 250, and the upper plate is connected to the metal layer through the conductive medium 250. BL connection in 240.

Figure 4 is a schematic diagram of the hierarchical structure of a memory along the bit line direction provided by an embodiment of the present application. The hierarchical structure from bottom to top is substrate 300 - transistor layer 210 - polycrystalline layer 220 - capacitor layer 230 - metal layer 240. . In the embodiment of the present application, a plurality of transistors 310 are distributed in the transistor layer 210, the word line WL is located in the polycrystalline layer 220, a plurality of capacitors 330 are distributed in the capacitor layer 230, and the bit line BL is located in the top metal layer 240. The transistor 310 includes a source S, a drain D and a gate G, and the capacitor 330 includes an upper plate 333 , a lower plate 331 and a capacitive dielectric layer 332 . It should be understood that the marked positions of WL, PL, and BL in the figure are the hierarchical positions of the distribution of each interconnection line.

It should be understood that the memory cell shown in FIG. 4 is a 1T1C structure, that is, each memory cell includes a transistor 310 and a capacitor 330. The lower plate 331 of the capacitor is connected to the drain D of the transistor through the contact hole 351, the upper plate 333 of the capacitor is connected to the bit line BL of the metal layer 240 through the contact hole 352, and the sources S of the transistors located in two adjacent rows They are connected together by the plate line PL, that is, the sources S of the transistors in two adjacent rows are shared. The gates G of the transistors in the same row are connected through the word line WL.

It should be understood that the contact hole 351 and the contact hole 352 are both through holes filled with conductive media. They are substantially the same and should not be understood as a limitation of the present application.

It should be understood that the structure of FIG. 4 is only an example and may also include multiple metal layers. Only the top metal layer 240 is used to arrange the bit line BL, and the other metal layers play a conductive role. The source S of the transistor 310 in the memory cell is connected to the top metal layer 240 through the contact hole 351, the contact hole 352 and other metal layers.

It should be understood that considering the symmetry of the transistor, the source S and the drain D in the embodiment of the present application can be interchanged without affecting their functions. Only one of the forms is listed in the embodiment.

Below, this application will describe in detail the structure and preparation method of the memory of this application based on the hierarchical structure schematic diagram shown in FIG. 4 .

FIG. 5 is a schematic circuit diagram of a memory array structure provided by an embodiment of the present application.

Exemplarily, the memory cell array shown in Figure 5 includes M rows×N columns of memory cells, M word lines, N bit lines, P row direction plate lines and one column direction plate line LPL, M, N and P are both integers greater than or equal to 2. The interconnection lines of the memory cell array include WL, PL and BL, and each memory cell is connected to a BL, a PL and a WL. Individual memory cells can be accessed at will using interconnect lines. Among them, WL can choose to turn on the transistor of the corresponding memory unit, and then combine PL and BL to access and store the selected memory unit.

Each memory cell in the memory cell array shown in FIG. 5 includes a crystal 310 and a capacitor 330. Among them, the memory cell located in the i-th row of the memory cell array is connected to the i-th word line of M word lines, and the memory cell located in the j-th column of the memory cell array is connected to the j-th bit line of N bit lines. superior. The lower plate 331 of the capacitor 330 located in the i-th row and j-th column memory cell in the memory cell array is connected to the drain D of the transistor 310 located in the same memory cell, The upper plate 333 is connected to the j-th bit line. i is an integer greater than or equal to 0 and less than M, j is an integer greater than or equal to 0 and less than N. The source S of the transistor of the memory unit located in the 2k-1th row of the memory cell array and the memory unit located in the 2kth row may be jointly connected to the kth plate line of the P plate lines, k is greater than or equal to 1 and An integer less than or equal to P. In this way, the sources S of the transistors in two adjacent rows of memory cells are connected together to achieve source sharing.

Multiple plate lines PL along the row direction in the memory cell array may be connected together by plate lines LPL along the column direction. Taking the memory cell array shown in Figure 5 as an example, all P plate lines in the same direction as the word lines in the memory cell array can be connected using a plate line LPL along the column direction, so that all the memory cells in the memory cell array The sources of transistors can be connected together to achieve source sharing. The entire memory cell array only needs one contact hole to connect the board line to the wire of the top metal layer 240, thereby realizing the physical connection of the wires in the transistor layer 210 and the metal layer 240, reducing the PL contact holes required for the memory cell.

Alternatively, the plate lines LPL along the column direction may not be used to connect multiple plate lines PL along the row direction, and only the sources of the transistors in two adjacent rows may be shared. For example, the sources S of the transistors in the memory cells in rows 1 and 2 are commonly connected to PL1, so that the two rows of memory cells only need one contact hole to connect the board wire to the wire of the top metal layer 240. The physical connection of the wires in the transistor layer 210 and the metal layer 240 can be realized, reducing the required PL contact holes of the memory cell, that is, reducing the restrictions on the capacitor layer 230. During layout layout, the capacitor area can be increased while keeping the area of the memory cell unchanged.

Optionally, at least two plate lines PL along the row direction can also be connected together through a plate line LPL along the column direction. For example, the plate lines PL1 and PL2 can be connected together through the plate line LPL1 along the column direction, and the plate lines PL3 to PL8 can be connected together through the plate line LPL2 along the column direction, so that the transistors in the multi-row memory cells The sources S can be connected together to achieve source sharing, reducing the PL contact holes required for the memory cell.

FIG. 6 is a schematic circuit diagram of another memory array structure provided by an embodiment of the present application. Optionally, the source of the transistor 310 located in the i-th row of memory cells in the memory cell array is connected to the i-th plate line of the P plate lines, so that the transistors in the memory cells located in the same row can achieve source sharing.

Optionally, at least two plate lines along the row direction in the memory array as shown in Figure 6 can also be connected using one plate line along the column direction, so that the sources of the transistors in multiple rows of memory cells can be connected to Together, source sharing is achieved, reducing the PL contact holes required for memory cells.

FIG. 7 is a schematic circuit diagram of another memory array structure provided by an embodiment of the present application. Taking FIG. 7 as an example, the reading and writing mechanism of the memory array according to the embodiment of the present application is explained. Among them, the memory cell 11 and the memory cell 12 are located in the first row of the memory cell array and share the word line WL1. Memory unit 21 and memory unit 22 are located in the second row of the memory cell array and share word line WL2. Memory cell 11 and memory cell 21 are located in the first column of the memory cell array and share bit line BL1. Memory cell 12 and memory cell 22 are located in the second column of the memory cell array and share bit line BL2. Storage unit 11, storage unit 12, storage unit 21 and storage unit 22 share the plate line PL.

Taking the memory shown in Figure 7 as a ferroelectric memory as an example, the capacitive dielectric layer 332 between the upper and lower plates of the ferroelectric capacitor is a ferroelectric capacitor, and the storage unit 11, storage unit 12, storage unit 21 and storage unit 22 are ferroelectric. storage unit. The ferroelectric memory cell uses the polarization state of the ferroelectric capacitor to store "0" or "1", where the ferroelectric polarization is upward (the ferroelectric polarization direction points to BL) is recorded as "0", and the polarization is downward (ferroelectric polarization is pointing to BL). The direction points to PL) is recorded as "1".

The operation of writing "1" to the ferroelectric memory unit 11: WL1 is connected to a high level, the transistor in the ferroelectric memory unit 11 is turned on, BL1 is connected to a low level, and PL is connected to a high level, so that the iron in the ferroelectric memory unit 11 can be A potential difference forms on both sides of the capacitor. At the same time, since WL1 turns on the transistors in the ferroelectric memory unit 12 at the same time, in order to avoid rewriting other ferroelectric memory cells, To store the data in the unit, you need to set BL2 to high level and WL2 to low level. In this way, the potential difference between BL1 and PL will change the polarization direction of the ferroelectric capacitor in storage unit 11 to point to PL (the ferroelectric polarization direction is downward). Note that The stored data is "1".

The operation of writing "0" to ferroelectric memory unit 11: WL1 is connected to high level, the transistor in ferroelectric memory unit 11 is turned on, BL1 is connected to high level, PL is connected to low level, WL2 and BL2 are both connected to low level, As a result, a potential difference is formed on both sides of the ferroelectric capacitor in the memory unit 11, the ferroelectric polarization direction points to BL (ferroelectric polarization direction is upward), and the stored data is recorded as "0".

Operations of reading "1" and "0" from the ferroelectric memory cell 11: Data reading requires a sensitive amplifier connected to the BL side to amplify the bit line differential signal. BL1 is first precharged to low level, then WL1 is connected to high level, the transistor in memory unit 11 is turned on, and PL is connected to high level. At the same time, in order to avoid reading the data of other ferroelectric storage cells, BL2 needs to be connected to High level, WL2 is connected to low level, so that there is no potential difference in the ferroelectric capacitors in other ferroelectric memory cells. The polarization direction of the ferroelectric capacitor is flipped to read "0", and "1" is read out without flipping. Through different changes in the voltage of the corresponding bit line BL, the sensitive amplifier distinguishes the read data "0" or "1".

In the memory unit in the embodiment of the present application, the drain of the transistor is connected to the lower plate 331 of the ferroelectric capacitor, and the read and write operations are performed by applying a potential difference on both sides of the ferroelectric capacitor. As can be seen from Figure 7, by applying a voltage between PL and BL, read and write operations can be performed on the ferroelectric cell.

It should be understood that when the memory is in the data retention state, each WL, PL, and BL is at a low level, the transistor in the storage unit is turned off, and the capacitor maintains the storage state.

FIG. 8 is a schematic structural diagram of an interconnection line of a memory provided by an embodiment of the present application.

The word lines in the memory array can be wired using the conductive polycrystalline layer 220 in the CMOS process to connect the gates of the transistors in the same row together.

The plate line PL in the memory array can be wired using the active area 350 to connect the sources of one or more rows of transistors in the array together. It should be understood that the active area 350 is the area where transistors are distributed on the transistor layer 210, ie, the silicon wafer. A conductive channel is formed in the active region 350 through ion implantation, that is, the sources of the transistors of one or more rows of memory cells in the memory array can be connected together. This method of using the conductive channels in the active area 350 as the interconnection lines of the memory cell array can reduce the interconnection wiring distribution of the metal layer.

The bit lines BL in the memory cell array can be made of any conductive material, including metals and metal alloys.

In this embodiment of the present application, each memory cell includes a transistor 310 and a capacitor 330 . Taking the capacitor 330 as a ferroelectric capacitor as an example, the transistor 310 is coupled to the ferroelectric memory by sharing its drain with one plate of the ferroelectric capacitor, and can be used for read and write operations on the ferroelectric capacitor. Among them, the contact hole 351 ensures the physical connection between the drain D of the transistor and the lower plate 331 of the ferroelectric capacitor, and the contact hole 352 ensures the physical connection between the upper plate 333 of the ferroelectric capacitor and the metal layer 240 . The ferroelectric material used in ferroelectric capacitors can be one of the new materials that exhibit ferroelectric behavior in thin dimensions, such as doped hafnium oxide materials (doped zirconium, silicon, lanthanum, germanium, yttrium, aluminum, lanthanum, strontium, One or more of neodymium, lutetium, scandium, gold, nitrogen and other elements) or III-V group ferroelectric materials (including aluminum scandium nitride AlScN, aluminum yttrium nitride AlYN, gallium scandium nitride GaScN or indium scandium nitride One or more materials such as InScN).

In the memory array in the embodiment of the present application, the active areas 350 of the transistors in each two adjacent rows have overlapping portions, that is, the sources of the two transistors in the same column in the two adjacent rows are shared, and then through the lateral active area The area wiring connects all the sources of the transistors in two adjacent rows in the memory array together, so that the sources of the transistors in the two adjacent rows are shared. It should be understood that the plurality of plate lines PL connecting different rows in FIG. 8 can be connected together through the active area 350 in or at the periphery of the memory cell array, and the plate lines used as memory cell accesses are drawn out at the periphery of the array.

In order to facilitate understanding of the schematic diagram of the interconnection line structure in FIG. 8 according to the embodiment of the present application, the storage structure of FIG. 8 will be described in detail below. The process of preparing the reservoir.

FIG. 9 is a schematic flow chart of a memory preparation process provided by an embodiment of the present application. FIG. 10 is a schematic circuit diagram of another memory array structure provided by an embodiment of the present application. The memory prepared in Figure 9 corresponds to the circuit diagram shown in Figure 10.

610, active area layout.

First, the surface oxide of the substrate 300 is removed, and the layout of the active area 350 is positioned. FIG. 11 is a schematic diagram of an active area layout provided by an embodiment of the present application. The “艹” area in the figure is the positioned active area 350 , and the remaining blank portions can be regarded as field oxygen areas 360 . It should be understood that the active region 350 can form a conductive channel through ion implantation, and the field oxygen region 360 can play an isolation role.

620, ion implantation realizes source sharing.

FIG. 12 is a schematic diagram of an ion implantation active area provided by an embodiment of the present application. FIG. 12 corresponds to the circuit diagram of the memory shown in FIG. 10 . Ions are implanted into fixed areas of the active region 350, including the source area 420, the drain area 410 and the PL area 430, to form the source S, drain D and PL of the transistor. It should be understood that Figure 11 shows four transistors, two transistors in each column. The middle part of the two transistors in each column is the source S, the two end areas of the two transistors are the drain D, and the middle lateral area in the figure is the plate line PL connecting the sources of the four transistors. In the embodiment of the present application, the plate line PL uses active area wiring to connect the sources of the two rows of transistors in the array together.

It should be understood that forming the source, drain, and PL of the transistor by ion implanting a fixed area of the active region is only an example, and the source, drain, and PL of the transistor can also be formed by other conductive schemes, as long as the PL can connect multiple transistors. The source can be shared by the source.

630, precipitating oxide and polycrystalline layers.

It should be understood that between the source and drain of the transistor is a channel, an oxide is deposited over the channel, and then a polycrystalline layer 220 is deposited to form the gate 510 of the transistor. It should be understood that this oxide is located between the channel and gate 510 . Figure 13 is a schematic diagram of a precipitated oxide and polycrystalline layer provided by an embodiment of the present application. The gate electrodes 510 of the transistors in the same row are connected together, that is, the word line WL of the lateral polycrystalline layer distributed memory cell array.

640, punching holes and depositing capacitor layers.

FIG. 14 is a schematic diagram of a perforated and deposited capacitor layer 230 provided by an embodiment of the present application. After step 630, the oxide is deposited again, and holes are drilled and filled with conductive medium to form contact holes 351. Then, the lower plate 331 of the capacitor, the capacitor dielectric material and the upper plate 333 of the capacitor are deposited sequentially on the top of the contact hole 351 to form multiple capacitors 330 , wherein the deposited capacitor dielectric material will form the capacitor dielectric layer 332 . The plurality of capacitors 330 constitute the capacitor layer 230 .

650, punch holes and deposit metal layers.

FIG. 15 is a schematic diagram of a punching and depositing metal layer 240 provided by an embodiment of the present application. After step 640, the oxide is precipitated again, holes are drilled and filled with conductive medium to form contact holes 352. Then a metal layer 240 is deposited on top of the contact hole 352, and the top metal layer 240 distributes the bit lines BL of the memory cell array.

The interconnection lines of WL, PL, and BL in different layers can be connected to the top metal layer 240, and the interconnection lines arranged in the top metal layer 240 are isolated from each other. Optionally, other metal layers may be connected to the top metal layer 240 . It should be understood that only the top metal layer will distribute the bit line BL, and other metal layers are conductive. FIG. 16 is a schematic diagram of the hierarchical structure along the bit line direction of another memory provided by an embodiment of the present application. The bit line BL is distributed in the top metal layer 240. The plate line PL connected to the source of the transistor in the figure can be connected to the wire of the top metal layer 240 through the contact hole 351, the metal layer 241, the contact hole 352, the metal layer 2422 and the conductive medium. The square filled with black diagonal lines in the figure is the metal layer 2422. It should be understood that The metal layer 2422 is also the metal layer 242. For convenience of description, the metal layer is named the metal layer 2422. This name should not be understood as a limitation of the present application. This conductive medium connects the PL interconnect lines (perpendicular to the BL direction) in metal layer 2422 to metal layer 240 at other locations, not shown in FIG. 16 . It should be understood that FIG. 16 is only for illustration, and the plate line PL and the top metal layer 240 may be connected through multiple metal layers, or directly connected through contact holes without using a metal layer. It should be understood that the contact hole 353 is the same as the contact hole 351 and the contact hole 352, and they are all through holes filled with conductive medium.

FIG. 17 is a schematic structural diagram of an interconnection line of another memory provided by an embodiment of the present application.

The basic memory cell structure in the embodiment of the present application is similar to that of FIG. 8 , except that the active area used to connect the source electrodes of two adjacent rows of transistors is connected to the metal layer line through contact holes. Figure 16 includes two memory cell arrays on the left and right, each memory cell array including 4×3=24 memory cells. For ease of distinction, the active area where the sources of the transistors of two adjacent rows are connected is divided into active areas 610 to 640. The active area 610 is connected to the sources of the transistors in the memory cells in the 1st and 2nd rows of the left memory cell array, and the active area 620 is connected to the sources of the transistors in the 3rd and 4th rows of the left memory cell array, The active area 630 is connected to the sources of the transistors in the memory cells in rows 1 and 2 of the right memory cell array, and the active area 640 is connected to the sources of the transistors in the memory cells in the 3rd and 4th rows of the right memory cell array. The active area 610 and the active area 620 are connected together through the metal layer line LPL1, that is, the sources of the transistors of the left memory cell array are connected together through the metal layer line LPL1. The active area 630 and the active area 640 are connected together through the metal layer line LPL2, that is, the sources of the transistors of the right memory cell array are connected together through the metal layer line LPL2. It should be understood that the metal layer plate line LPL1 and the metal layer plate line LPL2 here refer to the plate lines distributed in the metal layer. For example, the metal layer can be the metal layer 241 in Figure 16 or the metal layer 242 Or metal layer 240. Optionally, the metal layer plate line LPL1 and the metal layer plate line LPL2 can be distributed on the same metal layer or on different metal layers, as long as they can connect multiple row direction plate lines, which is not limited in this application.

In the embodiment of the present application, each of the active areas 610 to 640 connects the sources of two adjacent rows of six transistors together to realize source sharing, and then connects to the metal layer board lines through holes.

It should be understood that in the embodiment of the present application, the active areas 610 to 640 of the memory array are formed with plate lines through ion implantation, and the metal layer plate lines LPL1 and LPL2 may be metal plate lines distributed in the metal layer. In the embodiment of the present application, since the local area source of the memory cell array is shared, there is no need to drill the source of each transistor of each memory cell in the memory cell array. It is only necessary to drill holes outside the memory cell array. For example, in Figure 17, the first two rows of memory cells in the left memory cell array only need one contact hole to connect the sources of the first two rows of memory cells to the metal layer, and the left and right two memory cell arrays only need 4 contact holes. The sources of 24 memory cells can be connected to the metal layer. Therefore, compared with the existing solution, the contact holes between the transistor layer 210 and the metal layer are reduced, and the area of the capacitors arranged in the unit area is increased.

It should be understood that the metal layer plate lines parallel to the direction of the bit lines in the embodiment of the present application are only illustrative. In actual memory arrays, the arrangement direction of the plate lines in the metal layer is not limited. The metal layer plate lines can also be parallel to the word lines. direction, or there is a certain angular distribution with the bit line.

FIG. 18 is a schematic diagram of the hierarchical structure of a memory along the metal layer line direction provided by an embodiment of the present application.

Figure 18 is a schematic diagram of the hierarchical structure of the memory along the metal layer line direction corresponding to the embodiment of Figure 17. The sources of two adjacent rows of transistors are shared and then connected to the top metal layer 240 through the contact hole 351, the metal layer 241 and the contact hole 352. wires in. The plate line LPL is the metal layer plate line LPL1 or the metal layer plate line LPL2. As shown in the figure, the metal layer plate lines LPL are distributed in the metal layer 240 . Alternatively, the metal layer plate lines LPL can also be distributed in the metal layer 241 . The metal layer line LPL can connect the sources of the transistors of rows 1 to 4 of memory cells together.

FIG. 19 is a schematic circuit diagram of another memory array structure provided by an embodiment of the present application.

Figure 19 is a schematic circuit diagram of the memory corresponding to the embodiment of Figure 17, including two left and right memory cell arrays, each memory cell array including 4WL x 3BL = 12 memory cells. PL11 is distributed in the active area 610 and connects the memory cells in row 1 and row 2 of the left memory cell array. PL12 is distributed in the active area 620 and connects the memory cells in the 3rd and 4th rows of the left memory cell array. PL21 is distributed in the active area 630 and connects the memory cells in row 1 and row 2 of the memory cell array on the right side. PL22 is distributed in the active area 640 and connects the memory cells in the 3rd and 4th rows of the memory cell array on the right side. LPL1 connects PL11 and PL12 together to realize source sharing of the left memory cell array. LPL2 connects PL21 and PL22 together to realize source sharing of the memory cell array on the right side.

It should be understood that the array structure in the embodiment of the present application is a 1T1C structure. The embodiment of the present application can also be applied to an array structure in which the memory cells are 2T2C and nTmC. This application is not limited to this.

It should be understood that the memory in the embodiment of the present application includes a memory whose basic memory unit is a transistor plus capacitor (resistance) structure. Alternatively, it may be a non-volatile memory such as a ferroelectric memory, a resistive random access memory, a phase change random access memory or a magnetoresistive random access memory. When arranging array memory cells, the active area distribution interconnection lines can be used to improve the area arrangement of resistive structures and increase the arrangement density of memory devices.

Those of ordinary skill in the art will appreciate that the units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each specific application, but such implementations should not be considered beyond the scope of this application.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with the embodiments of the present invention are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, e.g., the computer instructions may be transferred from a website, computer, server, or data center Transmission to another website, computer, server or data center through wired (such as coaxial cable, optical fiber) or wireless (such as infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more available media integrated. The available media may be magnetic media (such as floppy disks, hard disks, magnetic tapes), optical media (such as optical disks), or semiconductor media (such as solid-state drives (SSD)), etc.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application. should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims (16)

1. A storage array, characterized by including:

   The transistor layer includes a plurality of transistors arranged in the row direction and the column direction, each transistor in the plurality of transistors includes a first electrode and a second electrode, the first electrode is a source electrode and the second electrode is a drain electrode, or the first electrode is a drain electrode and the second electrode is a source electrode;

   The transistor layer further includes a plate line connecting the first electrodes of the plurality of transistors in the row direction;

   A polycrystalline layer, located on the transistor layer, is used to set word lines, and the word lines are along the row direction;

   a capacitor layer, located on the polycrystalline layer, including a plurality of capacitors arranged along the row direction and along the column direction, each capacitor in the plurality of capacitors including a first plate and a second plate ;

   A metal layer, located on the capacitor layer, for arranging bit lines, first conductive lines and second conductive lines, the bit lines being along the column direction;

   The plate line is connected to the first conductor of the metal layer, the word line is connected to the second conductor of the metal layer, and the first plate of each capacitor is connected to the corresponding transistor. The second electrode is connected, and the second plate of each capacitor is connected to the bit line of the metal layer.
2. The memory array according to claim 1, wherein the first plate of each capacitor is connected to the second electrode of the corresponding transistor through a first contact hole, and the first plate of each capacitor is connected to the second electrode of the corresponding transistor through a first contact hole. The second plate is connected to the bit line in the metal layer through a second contact hole, and the first contact hole and the second contact hole include a conductive medium.
3. The memory array according to claim 2, wherein the first contact hole is perpendicular to the first plate, and the second contact hole is perpendicular to the second plate.
4. The memory array according to any one of claims 1 to 3, wherein the transistor layer includes P plate lines, the P plate lines are along the row direction, and P is an integer greater than or equal to 2.
5. The memory array of claim 4, wherein at least two of the P plate lines are connected together through plate lines along the column direction.
6. The memory array according to claim 4 or 5, characterized in that the k-th plate line of the P plate lines is connected to the first electrodes of the 2k-1th and 2kth row transistors in the row direction. , k is an integer greater than or equal to 1 and less than or equal to P.
7. The memory array according to any one of claims 1 to 6, wherein the plate lines include active area wiring, and the active area wiring includes conductive channels formed by ion implantation.
8. A method for preparing a storage array, which is characterized by including:

   A transistor layer is formed, the transistor layer includes a plate line and a plurality of transistors arranged in a row direction and a column direction, each of the plurality of transistors includes a first electrode and a second electrode, the first electrode is The source electrode and the second electrode are drain electrodes, or the first electrode is a drain electrode and the second electrode is a source electrode, and the plate line connects the first electrode of the plurality of transistors in the row direction. an electrode;

   forming a polycrystalline layer on the transistor layer, the polycrystalline layer being used to provide word lines, the word lines being along the row direction;

   A capacitor layer is formed on the polycrystalline layer, the capacitor layer includes rows along the row direction and the column direction. a plurality of capacitors in a column, each capacitor in the plurality of capacitors including a first plate and a second plate, the first plate of each capacitor being connected to the second electrode of a corresponding transistor;

   A metal layer is formed on the capacitor layer. The metal layer is used to provide a bit line, a first conductor line and a second conductor line. The bit line is along the column direction. The bit line is connected to each capacitor. In the second plate, the first conductor is connected to the plate line, and the second conductor is connected to the word line.
9. The method of claim 8, further comprising:

   A first contact hole and a second contact hole are formed, and the first plate of each capacitor is connected to the second electrode of the corresponding transistor through the first contact hole, and all the electrodes of each capacitor are The second electrode plate is connected to the bit line in the metal layer through the second contact hole, and the first contact hole and the second contact hole include a conductive medium.
10. The method of claim 9, wherein forming the first contact hole and the second contact hole includes:

    forming the first contact hole perpendicular to the first electrode plate;

    The second contact hole is formed perpendicular to the second electrode plate.
11. The method according to any one of claims 8 to 10, wherein the transistor layer includes P plate lines, the P plate lines are along the row direction, and P is an integer greater than or equal to 2.
12. The method of claim 11, wherein at least two of the P plate lines are connected together through plate lines along the column direction.
13. The method according to claim 11 or 12, characterized in that the k-th plate line of the P plate lines is connected to the first electrode of the 2k-1th row and the 2k-th row transistor in the row direction, k is an integer greater than or equal to 1 and less than or equal to P.
14. The method according to any one of claims 8 to 13, wherein the plate lines include active area wiring, and the active area wiring includes forming conductive channels through ion implantation.
15. A memory, characterized in that it includes a storage controller and the storage array according to any one of claims 1 to 7, and the storage controller and the storage array are electrically connected.
16. An electronic device, characterized by comprising a circuit board and the memory of claim 15, the memory being disposed on the circuit board and electrically connected to the circuit board.