WO2023077314A1

WO2023077314A1 - Memory, control method for memory, formation method for memory, and electronic device

Info

Publication number: WO2023077314A1
Application number: PCT/CN2021/128485
Authority: WO
Inventors: 黄凯亮; 景蔚亮; 冯君校; 王正波
Original assignee: 华为技术有限公司
Priority date: 2021-11-03
Filing date: 2021-11-03
Publication date: 2023-05-11
Also published as: CN117546624A

Abstract

The embodiments of the present application relate to the technical field of semiconductor memories. Provided are a memory, a control method for a memory, a formation method for a memory, and an electronic device. The present application is mainly used for increasing the integration density of storage cells. The memory comprises a substrate and at least one storage cell, which is integrated on the substrate, wherein the storage cell comprises a first transistor and a second transistor, that is, the storage cell has a 2T0C gain-cell structure. In addition, the storage cell further comprises a first control line, a second control line and a third control line, wherein a first electrode of the first transistor is electrically connected to a gate electrode of the second transistor, a second electrode of the first transistor is electrically connected to a second electrode of the second transistor, a gate electrode of the first transistor is electrically connected to the first control line, a first electrode of the second transistor is electrically connected to the second control line, and the second electrode of the first transistor and the second electrode of the second transistor, which are electrically connected, are both electrically connected to the third control line. That is, the storage density is increased by means of reducing the number of control lines.

Description

Memory, method of controlling and forming method of memory, electronic device

technical field

The present application relates to the technical field of semiconductor storage, and in particular to a memory, a method for controlling the memory, a method for forming the memory, and an electronic device including the memory.

Background technique

In a computing system, dynamic random access memory (DRAM), as a memory structure, can be used to temporarily store the computing data of the central processing unit (CPU), and exchange data with external memories such as hard disks. Data is a very important part of computing systems.

Fig. 1 shows a circuit diagram of one of the memory cells in the existing DRAM, the memory cell includes two transistors, the memory cell formed in this way can be called a 2T0C (here T stands for transistor transistor, C stands for capacitor capacitor) memory cell . Wherein, the two transistors in the 2T0C memory cell shown in FIG. 1 can be respectively referred to as the write transistor Tr0 and the read transistor Tr1; the gate of the write transistor Tr0 is electrically connected to the write word line (write word line, WWL). One of the source and the drain of the transistor Tr0 is electrically connected to the write bit line (write bit line, WBL), and the other of the source and the drain of the write transistor Tr0 is electrically connected to the gate of the read transistor Tr1; One of the source and drain of the transistor Tr1 is electrically connected to a read word line (RWL), and the other of the source and drain of the read transistor Tr1 is electrically connected to a read bit line (RBL). ) electrical connection.

In the memory including the above-mentioned memory cells in FIG. 1 , each memory cell occupies a larger area and has a lower integration density. With the continuous improvement of the amount of data processed by processors, it is necessary to design a memory with higher integration density to meet people's demand for data processing in the information age.

Contents of the invention

The present application provides a memory, a method for controlling the memory, a method for forming the memory, and an electronic device including the memory. The main purpose is to provide a memory that can reduce the occupied space of the storage unit and increase the integration density of the storage unit.

In order to achieve the above object, the embodiments of the present application adopt the following technical solutions:

In a first aspect, the present application provides a memory, which may be a dynamic random access memory (dynamic random access memory, DRAM).

The memory includes a substrate and at least one memory unit integrated on the substrate, the memory unit includes a first transistor and a second transistor, that is to say, the memory unit belongs to a 2TOC gain-cell unit structure; in addition, the memory The unit also includes a first control line, a second control line and a third control line, wherein the first pole of the first transistor is electrically connected to the gate of the second transistor, and the second pole of the first transistor is electrically connected to the gate of the second transistor. The two poles are electrically connected, the gate of the first transistor is electrically connected to the first control line, the first pole of the second transistor is electrically connected to the second control line, and the second pole of the electrically connected first transistor is electrically connected to the first control line of the second transistor. The two poles are electrically connected with the third control line.

The storage unit of the memory provided in this application is a 2T0C gain-cell unit. In the memory cell, not only the first pole of the first transistor is electrically connected to the gate of the second transistor, but also the second pole of the first transistor is also electrically connected to the second pole of the second transistor, and the electrically connected first transistor The second pole of the second transistor and the second pole of the second transistor are then electrically connected to a third control line, where the third control line may be referred to as a write bit line WBL, or may be referred to as a read word line RWL. That is to say, in the memory cell, the write bit line WBL is shared with the read word line RWL, that is, a control line is shared; in addition, each memory cell also includes a first control line as the write word line WWL. line and a second control line as the read bit line RBL. In such a design, each storage unit contains three control lines. Compared with the existing storage unit containing four control lines, the number of control lines can be reduced, and in turn, the area occupied by each storage unit can be reduced by reducing the number of control lines. , increase the storage density of the storage unit, increase the storage capacity, so as to adapt to the amount of computing data of the processor.

In a possible implementation manner, the first transistor and the second transistor are stacked and arranged along a direction perpendicular to the substrate.

It can be understood that in the memory cell provided in this application, the first transistor and the second transistor are vertically stacked on the substrate. In this way, the area occupied by each storage unit on the substrate can be further reduced, for example, the area of each storage unit can be reduced to 4F ² , and a 3-dimensional (3 dimensional, 3D) stacking.

In a possible implementation manner, the gate of the second transistor shares the same electrode with the first pole of the first transistor, and the electrode shared by the gate of the second transistor and the first pole of the first transistor is a first common electrode, The second electrode of the second transistor shares the same electrode with the second electrode of the first transistor, and the electrode shared by the second electrode of the second transistor and the second electrode of the first transistor is a second common electrode. That is to say, in the memory cell, the first electrode of the first transistor and the gate of the second transistor share the same electrode structure, and the second electrode of the first transistor and the second electrode of the second transistor also share the same electrode structure. the same electrode. In this way, the original 2T0C memory cell comprising six electrodes becomes a 2T0C memory cell comprising four electrodes, that is, by reducing the number of electrodes laid out, the area occupied by each memory cell can be further reduced to Improve storage density.

In a possible implementation, the second common electrode has a first side perpendicular to the substrate and a second side parallel to the substrate; the first common electrode is located on the side facing the first side; The first pole of the second transistor is located on the side facing the second side; the gate of the first transistor is located on a side of the first common electrode and the second common electrode away from the first pole of the second transistor. Based on the above description of the arrangement position of the electrodes, it can be seen that in the first transistor, since the first pole and the second pole are arranged in a direction parallel to the substrate, the channel formed in this way can be parallel to the substrate. For the horizontal channel, in the second transistor, since the first pole and the second pole are arranged in a direction perpendicular to the substrate, the channel formed in this way can be a vertical channel perpendicular to the substrate.

In a possible implementation manner, the second transistor further includes a semiconductor layer; in the second transistor, the semiconductor layer includes a first semiconductor portion and a second semiconductor portion that are in contact, and the extension direction of the first semiconductor portion is the same as that of the substrate. The extension direction of the second semiconductor part is parallel to the substrate; the first semiconductor part is in contact with the second side, and the second semiconductor part is in contact with the third side; the third side is that the first pole of the second transistor faces the second side. face of the common electrode.

In the second transistor of this embodiment, the semiconductor layer structure includes two connected parts. It can also be considered that the semiconductor layer structure is an L-shaped structure, wherein the first semiconductor part is in ohmic contact with the second common electrode, and the second The second semiconductor part is in ohmic contact with the first pole of the second transistor, so that the ohmic contact area of the semiconductor layer can be increased to increase the current flow speed, and further, the reading and writing speed can be correspondingly increased.

In a possible implementation manner, the second transistor further includes a gate dielectric layer; between the first common electrode and the second common electrode, between the first common electrode and the first semiconductor part, and between the first common electrode and the second The semiconductor parts are separated by a gate dielectric layer.

In a possible implementation manner, the second transistor further includes a semiconductor layer; in the second transistor, the semiconductor layer includes a first semiconductor portion perpendicular to the substrate; one end of the first semiconductor portion close to the second common electrode is connected to The first side is in contact, and an end of the first semiconductor portion close to the first pole of the second transistor is in contact with the third side; the third side is a surface where the first pole of the second transistor faces the second common electrode.

That is to say, in this embodiment, the semiconductor layer of the second transistor has a linear structure to form the vertical channel of the second transistor.

In a possible implementation manner, the second transistor further includes a gate dielectric layer and a dielectric layer; between the first common electrode and the first semiconductor part, and between the first common electrode and the first electrode of the second transistor are covered by The gate dielectric layer is isolated, and the second common electrode is isolated from the first electrode of the second transistor by the dielectric layer.

In a possible implementation manner, the first electrode of the second transistor includes a first part and a second part that are in contact, the extension direction of the first part is perpendicular to the substrate, and the extension direction of the second part is parallel to the substrate, The first part is arranged closer to the second common electrode relative to the second part.

It can be understood that the first pole of the second transistor here has an L-shaped structure, which can increase the ohmic contact area between the semiconductor layer and the first pole of the L-shaped structure, so as to increase the current speed, thereby increasing the reading and writing speed.

In a possible implementation manner, in the first transistor, the semiconductor layer is arranged on the side of the first common electrode and the second common electrode away from the first pole of the second transistor; The semiconductor layer is in contact; or, the first semiconductor part is separated from the semiconductor layer of the first transistor by a gate dielectric layer.

In a possible implementation manner, the first transistor further includes a semiconductor layer and a gate dielectric layer; in the first transistor, the gate, the gate dielectric layer and the semiconductor layer are arranged One side of the first electrode of the two transistors, and the gate, gate dielectric layer and semiconductor layer are stacked in sequence along the direction perpendicular to the substrate, and the semiconductor layer is in contact with the first common electrode and the second common electrode.

Based on the above description of the structure of the first transistor, it can be seen that in the first transistor, the semiconductor layer is arranged along a direction parallel to the substrate, and furthermore, the channel of the first transistor is a horizontal channel.

In a possible implementation manner, the first transistor, the second transistor, the first control line, the second control line, and the third control line are all formed on the substrate by a back-end process.

Both the first transistor and the second transistor are produced by the back-end process, and the control circuit can be produced by the front-end process. The control circuit may include one or more circuits of a decoder, a driver, a timing controller, a buffer, or an input/output driver, and may also include other functional circuits. The control circuit can control the first control line, the second control line and the third control line in the embodiment of the present application. After the front-end process FEOL is completed, interconnection lines and storage arrays are manufactured through the back-end process BEOL. Fabricating the transistors and control lines through the back-end process can make the circuit density per unit area higher, thereby improving the storage performance per unit area.

In a possible implementation, there are multiple storage units; the first control line and the second control line both extend along a first direction parallel to the substrate, and the first control line is electrically connected to the multiple storage units located in the first direction. The gate of the first transistor of the storage unit, the second control line is electrically connected to the first electrodes of the second transistors of the plurality of storage units located in the first direction; the third control line extends along the second direction parallel to the substrate, The third control line is electrically connected to the second electrodes of the second transistors of the plurality of memory cells located in the second direction; the second direction is perpendicular to the first direction.

That is to say, when a plurality of memory cells are arranged in an array along the first and second directions perpendicular to each other, the first control line and the second control line extend along the same direction, and the third control line extends along the same direction as the first control line. Extend vertically. In the storage array, the first control line, the second control line and the third control line are also arranged in an array.

In a possible implementation manner, in the writing phase, the first control line is used to receive the first write word line control signal, so that the first transistor is turned on, and the third control line is used to receive the write bit line control signal, so that the Logical information is written into memory cells.

In a possible implementation, in the read phase, the first control line is used to receive the second write word line control signal, so that the first transistor is turned off, the third control line is used to receive the read word line control signal, and the second The control lines are used to output signals to read the logic information in the memory cells.

In a second aspect, the present application also provides a memory control method, where the memory includes at least one storage unit, and the storage unit includes a first transistor, a second transistor, a first control line, a second control line, and a third control line; Wherein, both the first transistor and the second transistor include a gate, a first pole and a second pole, the first pole of the first transistor is electrically connected to the gate of the second transistor, and the second pole of the first transistor is connected to the gate of the second transistor. The second pole of the first transistor is electrically connected to the first control line; the first pole of the second transistor is electrically connected to the second control line, and the second pole of the first transistor is electrically connected to the second transistor The second pole is electrically connected to the third control line;

Control methods include:

In the writing stage, the first control line is used to receive the first write word line control signal, so that the first transistor is turned on, and the third control line is used to receive the write bit line control signal, so as to write logic information into the storage unit.

In the memory control method provided in the present application, since the second pole of the first transistor is electrically connected to the second pole of the second transistor in the memory, in this case, in one memory cell, three lines for controlling reading and writing are required. Based on this feature, the control line can reduce the area occupied by each storage unit and increase the storage density.

In a possible implementation, the control method further includes: in the read phase, the first control line is used to receive the second write word line control signal, so that the first transistor is turned off, and the third control line is used to receive the read word line A control signal, the second control line is used to output a signal to read logic information in the storage unit.

In a possible implementation manner, the gate of the second transistor shares the same electrode with the first electrode of the first transistor, and the second electrode of the second transistor shares the same electrode with the second electrode of the first transistor.

That is to say, in the memory cell, the first electrode of the first transistor and the gate of the second transistor share the same electrode structure, and the second electrode of the first transistor and the second electrode of the second transistor also share the same electrode structure. the same electrode. In this way, the original 2T0C memory cell comprising six electrodes becomes a 2T0C memory cell comprising four electrodes, that is, by reducing the number of electrodes laid out, the area occupied by each memory cell can be further reduced to Improve storage density.

In a third aspect, the present application also provides a method for forming a memory, the forming method comprising:

Forming a first transistor and a second transistor on the substrate, the first transistor and the second transistor both include a gate, a first pole and a second pole, the first pole of the first transistor is electrically connected to the gate of the second transistor, the second pole of the first transistor is electrically connected to the second pole of the second transistor;

A first control line, a second control line and a third control line are formed, and the gate of the first transistor is electrically connected to the first control line, the first electrode of the second transistor is electrically connected to the second control line, and the electrically connected second The second pole of the first transistor and the second pole of the second transistor are electrically connected with the third control line.

In the forming method of the memory provided in this application, the first transistor, the second transistor, the first control line, the second control line and the third control line form a memory unit, and the prepared memory unit is compared with the existing The storage unit structure reduces the number of control lines for controlling reading and writing, thereby increasing the storage density of the storage unit and improving storage performance.

In a possible implementation manner, forming the first transistor and the second transistor on the substrate includes: stacking and forming the first transistor and the second transistor along a direction perpendicular to the substrate.

That is to say, the first transistor and the second transistor are stacked along a direction perpendicular to the substrate, so that three-dimensional stacking of memory cells on the substrate can be realized to further increase storage density.

In a possible implementation manner, when forming the second transistor, it includes: forming a first pole of the second transistor; forming a gate and a second pole on a side of the first pole of the second transistor away from the substrate, And the second pole has a first side perpendicular to the substrate, and the gate is located on the side facing the first side; when forming the first transistor, it includes: the gate of the second transistor and the second pole away from the substrate One side of one side forms the gate of the first transistor, the gate of the second transistor shares the same electrode with the first pole of the first transistor, and the second pole of the second transistor shares the same electrode with the second pole of the first transistor.

By sharing the same electrode with the first electrode of the first transistor and the gate of the second transistor, the second electrode of the first transistor and the second electrode of the second transistor also share the same electrode, the number of electrodes can be reduced, and the storage capacity can be further improved. density.

In a fourth aspect, the present application further provides an electronic device, including a processor and the memory in any implementation manner of the first aspect, the second aspect, or the third aspect above, and the processor is electrically connected to the memory.

The electronic device provided by the embodiment of the present application includes the memory of the embodiment of the first aspect, the embodiment of the second aspect, and the embodiment of the third aspect, so the electronic device provided by the embodiment of the present application and the memory of the above technical solution can solve the same technical problem , and achieve the same expected effect.

Description of drawings

Fig. 1 is a circuit diagram of a memory cell in a DRAM in the prior art;

FIG. 2 is a circuit diagram of an electronic device provided in an embodiment of the present application;

FIG. 3 is a circuit diagram of a memory provided in an embodiment of the present application;

FIG. 4 is a simplified structural diagram of a memory provided by an embodiment of the present application;

FIG. 5 is a circuit diagram of a storage unit in a memory provided by an embodiment of the present application;

FIG. 6 is a circuit diagram of a memory array formed by a plurality of memory cells in a memory provided by an embodiment of the present application;

FIG. 7 is a positional relationship diagram between a storage unit and a substrate in a memory provided by an embodiment of the present application;

FIG. 8 is a cross-sectional view of a process structure of a memory cell in a memory provided by an embodiment of the present application;

FIG. 9 is a three-dimensional diagram of a process structure of a storage unit in a memory provided by an embodiment of the present application;

FIG. 10 is a simplified top view of multiple storage units in a memory provided by an embodiment of the present application;

FIG. 11 is a process structure diagram of a memory provided in an embodiment of the present application;

FIG. 12 is a cross-sectional view of a process structure of a memory cell in a memory provided by an embodiment of the present application;

FIG. 13 is a cross-sectional view of a process structure of a memory cell in a memory provided by an embodiment of the present application;

14 is a cross-sectional view of a process structure of a memory cell in a memory provided by an embodiment of the present application;

FIG. 15 is a cross-sectional view of a process structure of a memory cell in a conventional memory;

FIG. 16 is a block flow diagram of a memory manufacturing method provided by an embodiment of the present application;

Figures 17a to 17e are cross-sectional views of the corresponding process structure after each step in a memory manufacturing method provided by the embodiment of the present application;

Figures 18a to 18h are cross-sectional views of the corresponding process structure after each step in a memory manufacturing method provided by the embodiment of the present application;

Figures 19a to 19h are cross-sectional views of the corresponding process structure after each step in a memory manufacturing method provided by the embodiment of the present application;

20a to 20h are cross-sectional views of the process structure corresponding to the completion of each step in a memory manufacturing method provided by the embodiment of the present application.

Reference signs:

100-substrate;

200 - interconnection line;

300-storage array;

400 - storage unit;

500 - dielectric layer;

Tr1-read transistor; 101-first pole; 101-1-first part; 101-2-second part; 102-semiconductor layer; 102-1-first semiconductor part; 102-2-second semiconductor part; 103 -gate dielectric layer; 104-gate; 105-second pole; 109-dielectric layer;

Tr0-write transistor; 104-first pole (first common electrode); 105-second pole (second common electrode); 106-semiconductor layer; 107-gate dielectric layer; 108-gate;

001-the first conductive layer;

002-the first semiconductor material layer;

003-the second conductive layer;

004-slot;

005-the first dielectric material layer;

006-the third conductive layer;

007-the second semiconductor material layer;

008-the second dielectric material layer;

009-the fourth conductive layer;

010-through hole;

011 - third layer of dielectric material.

Detailed ways

The following describes the embodiments given in this application with reference to the accompanying drawings.

An embodiment of the present application provides an electronic device including a memory. FIG. 2 is a circuit block diagram of an electronic device 200 provided in an embodiment of the present application. The electronic device 200 can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (personal computer, PC), Servers, workstations, etc. As shown in FIG. 2 , the electronic device 200 includes a bus 205 , and a system on chip (SOC) 210 and a read-only memory (read-only memory, ROM) 220 connected to the bus 205 . The SOC 210 can be used to process data, such as processing application program data, processing image data, and caching temporary data. ROM 220 can be used to save non-volatile data, such as audio files, video files, etc. The ROM 220 can be programmable read-only memory (programmable read-only memory, PROM), erasable programmable read-only memory (programmable read-only memory, EPROM), flash memory (flash memory), etc.

In addition, the electronic device 200 may further include a communication chip 230 and a power management chip 240 . The communication chip 230 can be used to process the protocol stack, or to amplify and filter the analog radio frequency signal, or to realize the above functions at the same time. The power management chip 240 can be used to supply power to other chips.

In one embodiment, the SOC 210 may include an application processor (application processor, AP) 211 for processing application programs, an image processing unit (graphics processing unit, GPU) 212 for processing image data, and a cache data random access memory (random access memory, RAM) 213.

The above-mentioned AP211, GPU212 and RAM213 can be integrated into one die, or respectively integrated into multiple dies, and packaged in a package structure, such as 2.5D (dimension), 3D package , or other advanced packaging technologies. In one embodiment, the above-mentioned AP211 and GPU212 are integrated in one die, RAM213 is integrated in another die, and these two dies are packaged in a package structure, so as to obtain a faster data transmission rate between dies and higher data transfer bandwidth.

FIG. 3 is a circuit block diagram of a memory 300 provided in an embodiment of the present application. The memory 300 may be the RAM 213 shown in FIG. 2 . In one embodiment, the memory 300 may also be a RAM provided outside the SOC 210 . The present application does not limit the location of the memory 300 in the electronic device and the location relationship with the SOC 210 .

Continuing with FIG. 3 , the memory 300 includes a storage array 310 , a decoder 320 , a driver 330 , a timing controller 340 , a buffer 350 and an input/output driver 360 . The storage array 310 includes a plurality of storage units 400 arranged in an array, wherein each storage unit 400 can be used to store 1-bit or multi-bit data. The memory array 310 also includes signal control lines such as word lines (word line, WL) and bit lines (bit line, BL). Each memory cell 400 is electrically connected to the corresponding word line WL and bit line BL. One or more of the above-mentioned word line WL and bit line BL are used to select the memory cell 400 to be read and written in the memory array by receiving the level output by the control circuit, so as to realize data read and write operations.

In the structure of the memory 300 shown in FIG. 3 , the decoder 320 is used to decode the received address to determine the storage unit 400 to be accessed. The driver 330 is used to control the level of the signal line according to the decoding result generated by the decoder 320 , so as to realize the access to the specified storage unit 400 . The buffer 350 is used for caching the read data, for example, first-in-first-out (FIFO) may be used for caching. The timing controller 330 is used for controlling the timing of the register 350 and controlling the driver 330 to drive the signal lines in the memory array 310 . The input/output driver 360 is used to drive transmission signals, such as driving received data signals and driving data signals to be sent, so that the data signals can be transmitted over long distances.

The memory array 310 , decoder 320 , driver 330 , timing controller 340 , buffer 350 and input/output driver 360 may be integrated into one chip, or may be integrated into multiple chips respectively.

The above-mentioned storage array 310 may be a one-layer storage array, or may be a first-layer storage array and a second-layer storage array stacked along the Z direction perpendicular to the substrate as shown in FIG. 4 , or, in some other optional In some embodiments, more layers of storage arrays may be included. When two or more layers of storage arrays are included, such a memory may be referred to as a three-dimensional integrated memory structure.

In the memory structure shown in Figure 4, the control circuit is integrated on the substrate through the front end of line (FEOL) process, and the interconnection and memory are integrated on the substrate through the back end of line (BEOL) process. on the control circuit. The control circuit here can generate control signals, and these control signals can be read and write control signals for controlling the read and write operations of data in the memory.

The memory 300 involved in this application may be a dynamic random access memory (dynamic random access memory, DRAM), or a ferroelectric random access memory (ferroelectric random access memory, FeRAM).

FIG. 5 is a circuit diagram of a storage unit 400 in the memory 300 provided in the present application. As shown in Figure 5, the memory cell 400 belongs to the gain-cell memory cell structure of 2T0C, that is, a write transistor Tr0 (also referred to as a first transistor) and a read transistor Tr1 (also referred to as a first transistor) and a read transistor Tr1 are included in a memory cell 400 is called a second transistor), and the first pole of the write transistor Tr0 is electrically connected to the gate of the read transistor Tr1, and the second pole of the write transistor Tr0 is electrically connected to the second pole of the read transistor Tr1. In addition, the memory cell 400 also includes: a write word line (write word line, WWL) and a read bit line (read bit line, RBL), and another signal line, where the other signal line is connected to the write transistor Tr0 The second pole is electrically connected to the second pole of the read transistor Tr1, and another signal line here can be referred to as a write bit line (write bit line, WBL), or as a read word line (read word line) , RWL); Also, the write word line WWL is electrically connected to the gate of the write transistor Tr0, and the read bit line RBL is electrically connected to the first electrode of the read transistor Tr1.

In this application, the write word line WWL may also be referred to as the first control line for loading a signal to the gate of the write transistor Tr0, and the read bit line RBL may also be referred to as the first control line for loading the gate of the read transistor Tr1. A second control line for loading signals at one pole, the write bit line WBL or the read word line RWL may also be referred to as a third control line for loading signals to the second pole of the write transistor Tr0 and the second pole of the read transistor Tr1 Wire.

Also, in this application, one of the drain or source of the transistor Tr is called the first pole, the corresponding other pole is called the second pole, and the control terminal of the transistor Tr is the gate. pole. The drain and source of the transistor Tr can be determined according to the flow direction of the current. For example, in the writing transistor Tr0 of FIG. 5, when the current flows from left to right, the left end is the drain and the right end is the source; When going from right to left, the right end is the drain and the left end is the source.

In the storage unit 400 provided in the present application, as shown in FIG. 5 , since the second pole of the write transistor Tr0 is electrically connected to the second pole of the read transistor Tr1, the write bit line WBL or the signal control line with the signal control line The read word line RWL is electrically connected. That is to say, the second pole of the writing transistor Tr0 and the second pole of the reading transistor Tr1 can share the control signal line. If designed in this way, a storage unit provided in this application contains three signal lines for controlling reading and writing. Compared with the existing four signal lines for controlling reading and writing, the number of signal lines can be reduced, thereby reducing the number of each The occupied area of the storage unit increases the storage density and storage capacity.

The memory array 310 can be obtained by arranging the memory cells 400 shown in FIG. 5 above in an array, wherein each memory cell 400 has the same circuit structure. For example, in the memory array 310 shown in FIG. 6 , a 4×4 memory array arranged along the perpendicular X direction and the Y direction is exemplarily given. It can also be easily seen from FIG. 6 that since the write transistor Tr0 and the read transistor Tr1 share the write bit line WBL and the read word line RWL, in a memory array containing multiple memory cells, the number of signal control lines can be greatly reduced. Quantity, therefore, will significantly increase the integration density of memory cells.

In some optional implementations, when the storage arrays shown in Figure 6 are stacked along the Z direction shown in Figure 4, three-dimensional stacking can be realized, and the storage capacity can be further improved to adapt to processing with high operating efficiency. device.

Continuing to refer to FIG. 5 and FIG. 6 , the writing operation process and the reading operation process of the 2T0C storage unit 400 will be described respectively.

Write operation process: during the write operation, the voltage of the read bit line RBL is 0, and the read transistor Tr1 does not work; the first write word line control signal is provided to the write word line WWL, and the first write word line control signal controls the write transistor Tr0 conduction. When writing the first logic information, such as "0", the first write bit line control signal is provided to the write bit line WBL (or read word line RWL), and the first write bit line control signal passes through the write transistor Tr0 Write to node N. When writing the second logic information, such as "1", a second write bit line control signal is provided to the write bit line WBL (or read word line RWL), and the second write bit line control signal is written through the write transistor Tr0 Enter node N.

It should be understood that after the write operation is completed, the read transistor Tr0 does not work; the second write word line control signal is provided to the write word line WWL, and the second write word line control signal controls the write transistor Tr0 to turn off. At this time, the potential stored at the node Free from outside influence.

Read operation process: provide a second write word line control signal to the write word line WWL, and the second write word line control signal controls the write transistor Tr0 to turn off; provide read word line control to the read word line RWL (or write bit line WBL) signal, according to the level of the current on the read bit line RBL to judge the stored logic information of the memory cell. When the node N stores the first write bit line control signal, since the first write bit line control signal can control the turn-on of the read transistor Tr1, a read word line is provided on the read word line RWL (or write bit line WBL). When the control signal is used, the read word line RWL (or write bit line WBL) charges the read bit line RBL through the read transistor Tr1, and the voltage on the read bit line RBL rises, so that when the read bit line is detected When the current on the line RBL is large, it can be read that the memory cell stores logic information "0". When the node N stores the second write bit line control signal, since the second write bit line control signal can control the read transistor Tr1 to turn off, the read word is provided on the read word line RWL (or the write bit line WBL) When the line control signal is used, the read word line RWL (or write bit line WBL) will not charge the read bit line RBL through the read transistor Tr1, and the read bit line RBL maintains a voltage of 0V. In this way, when a read When the current on the bit line RBL is small, it can be read that the memory cell stores logic information "1".

In some optional implementation manners, in order to further increase the storage density, in the memory cell 400 involved in the present application, in the simplified schematic diagram of the process structure shown in FIG. The bottom 100 is stacked in a vertical direction. In the embodiment shown in FIG. 7 , the read transistor Tr1 is arranged closer to the substrate 100 than the write transistor Tr0 . In other optional embodiments, the write transistor Tr0 may also be arranged closer to the substrate 100 than the read transistor Tr1 .

In addition, both the write transistor Tr0 and the read transistor Tr1 of the memory unit 400 of the present application belong to a thin film transistor (Thin film transistor, TFT) structure. In combination with the layout shown in FIG. 7, the writing transistor Tr0 and the reading transistor Tr1 of the TFT can be three-dimensionally integrated on the substrate 100. For example, as shown in FIG. 4, they can be formed on the substrate 100 through a subsequent process. By further increasing the integration density, the storage capacity per unit area is increased, thereby improving the storage performance of the memory.

For the structure of the write transistor Tr0 and the read transistor Tr1 , various possible implementation methods are given below, which will be described respectively in conjunction with the accompanying drawings.

Figure 8 shows a sectional view of a realizable process structure of the write transistor Tr0 and the read transistor Tr1, which is a sectional view obtained by cutting parallel to the X-Z plane shown in Figure 7, and Figure 9 shows The three-dimensional structure diagram of Fig. 8 is shown. 8 and 9 together, the write transistor Tr0 includes a first pole 104, a second pole 105, a gate 108, a gate dielectric layer 107 and a semiconductor layer 106 (the semiconductor layer 106 may also be called a channel layer); The read transistor Tr1 includes a first pole 101 , a second pole 105 , a gate 104 , a gate dielectric layer 103 and a semiconductor layer 102 .

It can be seen from the process structure of the memory cell 400 shown in FIG. 8 and FIG. 9 that the first electrode 104 of the write transistor Tr0 and the gate 104 of the read transistor Tr1 share the same electrode, and this shared electrode can be called the first common electrode 104 In addition, the second pole 105 of the write transistor Tr0 and the second pole 105 of the read transistor Tr1 also share the same electrode, and this common electrode can be called the second common electrode 105 .

That is to say, in the stacked write transistor Tr0 and read transistor Tr1 provided in this embodiment, two electrode structures are shared, so that one memory cell 400 only includes four electrode structures in the process structure. Such a process structure can further reduce the area occupied by each memory cell 400 on a plane parallel to the substrate by reducing the number of electrode process structures. For example, as shown in FIG. 9 and FIG. 10 , stacked write transistors The length of the field area occupied by Tr0 and the read transistor Tr1 in the X direction is 1F, and the active area is 1F. The length of the field area occupied by the stacked write transistor Tr0 and the read transistor Tr1 in the Y direction is 1F, and the active area is 1F. Therefore, The stacked write transistor Tr0 and read transistor Tr1 occupy an area of 2F×2F=4F ² in the XY plane. Compared with the existing 6F ² or larger occupied area, the area occupied by the memory cell 400 given in this application is Significantly smaller.

Continuing with FIG. 8 and FIG. 9, the gate 108, the gate dielectric layer 107 and the semiconductor layer 106 of the write transistor Tr0 are sequentially stacked along the Z direction perpendicular to the substrate 100, and the first electrode serving as the first pole of the write transistor Tr0 The common electrode 104 and the second common electrode 105 as the second pole of the write transistor Tr0 are arranged in a direction parallel to the substrate 100, and the semiconductor layer 106 is ohmic with the first common electrode 104 and the second common electrode 105. contact, so that the channel formed by the write transistor Tr0 is a horizontal channel parallel to the substrate 100 .

It can be understood that the first common electrode 104 and the second common electrode 105 are arranged along a direction parallel to the substrate 100, the second common electrode 105 has a first side M1 perpendicular to the substrate 100, and the first common electrode 104 Located on the side facing the first side M1.

In the read transistor Tr1 of the memory unit 400 shown in FIGS. arranged so that the channel formed by the read transistor Tr1 is a vertical channel perpendicular to the substrate.

For the above-mentioned second common electrode 105 and the first pole 101 of the read transistor Tr1 are arranged along the direction perpendicular to the substrate 100, it can be said that, as shown in Figures 8 and 9, the second common electrode 105 has a With the parallel second side M2, the first pole 101 of the read transistor Tr1 is located on the side facing the second side M2.

That is to say, in the process structure of the 2T0C memory cell given in this application, the write transistor Tr0 is a planar transistor, and the read transistor Tr1 is a vertical transistor.

8, in the read transistor Tr1, the semiconductor layer 102 includes a first semiconductor portion 102-1 and a second semiconductor portion 102-2, the extension direction of the first semiconductor portion 102-1 (along the Z direction of FIG. 8 and FIG. 9 ) is perpendicular to the substrate, the extension direction of the second semiconductor portion 102-2 (along the X direction in FIG. 8 and FIG. 9 ) is parallel to the substrate, and the first semiconductor portion 102-1 and the second common electrode 105 The two side faces M2 are in contact, and the second semiconductor part 102-2 is in contact with the third side M3 of the first pole 101. Here, the second side M2 is the face of the second common electrode 105 facing the first pole 101, and the third side M3 is the face of the first pole 101. One pole 101 faces the surface of the second common electrode 105 . That is to say, the semiconductor layer 102 in the read transistor Tr1 has an L-shaped structure, and is in ohmic contact (also called electrical coupling) with the second common electrode 105 and the first electrode 101 .

Referring again to FIG. 8 and FIG. 9, since the semiconductor layer 102 in the read transistor Tr1 has an L-shaped structure, in order to electrically isolate the first common electrode 104 from the second common electrode 105, the first common electrode 104 and the semiconductor layer 102 are electrically isolated. For isolation, the corresponding gate dielectric layer 103 also has an L-shaped structure.

FIG. 11 is a three-dimensional structure diagram of a memory 300 provided in the present application, and includes the storage unit 400 shown in FIGS. 8 and 9 above. In FIG. 11 , it exemplarily shows that the memory 300 includes a first-layer storage array and a second-layer storage array, and the first-layer storage array and the second-layer storage array are along the Z direction perpendicular to the substrate 100. stack. Of course, in an optional implementation manner, more layers of storage arrays can also be stacked.

As shown in FIG. 11 , a dielectric layer 500 needs to be provided between every two adjacent layers of storage arrays to electrically isolate the storage arrays of adjacent layers, so that the memory arrays of any layer can be read and written. Any storage unit is accessed.

Continuing in conjunction with FIG. 11, in any layer of memory array, it includes a plurality of memory cells arranged along the first direction (such as the X direction in FIG. The storage unit arranged in the Y direction). Wherein, the write word line WWL extends along the X direction, and the read bit line RBL also extends along the X direction. Then, the gates 108 of the write transistors Tr0 of the plurality of memory cells arranged along the X direction are all connected with the gates 108 of the write transistors Tr0 extending along the X direction. The write word line WWL is electrically connected, and the first poles 101 of the read transistors Tr1 of the plurality of memory cells arranged along the X direction are all electrically connected to the read bit line RBL extending along the X direction, and the write bit line WBL (or read word line RWL) extends along the Y direction, and the second common electrodes 105 of the plurality of memory cells arranged along the Y direction are all electrically connected to the write bit line WBL (or read word line RWL) extending along the Y direction. connect.

FIG. 12 is a cross-sectional view of a process structure of another memory cell 400 provided in the present application. The storage unit shown in FIG. 12 is the same as the storage unit 400 shown in FIG. 8 and FIG. 9 above: the first pole of the write transistor Tr0 and the gate of the read transistor Tr1 share the first common electrode 104, and the second pole of the write transistor Tr0 pole and the second pole of the read transistor Tr1 share the second common electrode 105; in addition, the same point also includes: the channel formed in the write transistor Tr0 is a horizontal channel (as shown in the gate dielectric in Figure 12 layer 106), the channel formed in the read transistor Tr1 is a vertical channel (like the dotted line drawn on the gate dielectric layer 102 in FIG. 12).

The difference between the memory cell 400 shown in FIG. 12 and the memory cell 400 shown in FIGS. 8 and 9 above is that in the read transistor Tr1, the semiconductor layer 102 is a structure perpendicular to the substrate, and the semiconductor layer 102 and The first side M1 of the second common electrode 105 is in ohmic contact, and the semiconductor layer 102 is also in contact with the third side M3 of the first electrode 101 to form a vertical channel of the read transistor Tr1 . Here, the first side M1 and the third side M3 have been explained above, and will not be repeated here.

Continuing as shown in FIG. 12 , in the read transistor Tr1 , the semiconductor layer 102 is in contact with the semiconductor layer 106 of the write transistor Tr0 . In addition, in order to make the electrical isolation between the first common electrode 104 and the semiconductor layer 102, and the electrical isolation between the second common electrode 105 and the first pole 101, as shown in Figure 12, between the first common electrode 104 and the semiconductor layer 102 A gate dielectric layer 103 is disposed between the first common electrode 104 and the first electrode 101 , that is, as shown in FIG. 12 , the gate dielectric layer 103 is disposed in an L-shaped structure. In addition, in order to electrically isolate the first common electrode 104 from the first pole 101 , a dielectric layer 109 is also disposed between the second common electrode 105 and the first pole 101 .

The gate dielectric layer 103 and the dielectric layer 109 here can choose the same dielectric material, and can also choose different dielectric materials. Materials with low electrical constants.

FIG. 13 is a cross-sectional view of a process structure of another memory cell 400 provided in the present application. The storage unit shown in FIG. 13 is the same as the storage unit 400 shown in FIG. 12 above: the first pole of the write transistor Tr0 and the gate of the read transistor Tr1 share the first common electrode 104, and the second pole of the write transistor Tr0 and the gate of the read transistor Tr1 share the first common electrode 104. The second pole of the transistor Tr1 shares the second common electrode 105; in addition, the same points also include: the channel formed in the write transistor Tr0 is a horizontal channel, and the channel formed in the read transistor Tr1 is a vertical channel channel, the semiconductor layer 102 is in ohmic contact with the first side M1 of the second common electrode 105 .

The difference from the memory cell 400 shown in FIG. 12 is that in the read transistor Tr1, the first pole 101 includes a first part 101-1 and a second part 101-2, wherein the extending direction of the first part 101-1 (along the Z direction) is perpendicular to the substrate 100, and the extension direction of the second part 101-2 (along the X direction in FIG. 13) is parallel to the substrate 100, that is, as shown in FIG. 13, the first pole 101 is L-shaped structure, and the first part 101 - 1 is closer to the second common electrode 105 than the second part 101 - 2 , and the first part 101 - 1 is in contact with the dielectric layer 109 .

In the memory cell 400 shown in conjunction with FIG. 12 and FIG. 13 , the semiconductor layer 102 of the read transistor Tr1 and the semiconductor layer 106 of the write transistor Tr0 are in contact.

FIG. 14 is a cross-sectional view of a process structure of another memory cell 400 provided in the present application. The storage unit shown in FIG. 14 is the same as the storage unit 400 shown in FIG. 13 above: the first pole of the write transistor Tr0 and the gate of the read transistor Tr1 share the first common electrode 104, and the second pole of the write transistor Tr0 and the gate of the read transistor Tr1 share the first common electrode 104. The second pole of the transistor Tr1 shares the second common electrode 105; in addition, the same points also include: the channel formed in the write transistor Tr0 is a horizontal channel, and the channel formed in the read transistor Tr1 is a vertical channel channel, the semiconductor layer 102 is in ohmic contact with the side surface M3 of the second common electrode 105 .

The difference from the memory cell 400 shown in FIG. 13 above is that the semiconductor layer 102 in the read transistor Tr1 and the semiconductor layer 106 of the write transistor Tr0 are not in contact, but a gate dielectric layer is provided between the semiconductor layer 102 and the semiconductor layer 106 103.

Based on the above descriptions of memory cells 400 with several different structures in FIG. 8, FIG. 12, FIG. 13 and FIG. electrode, so that there is no need to provide a wiring layer between the writing transistor Tr0 and the reading transistor Tr1, but the writing transistor Tr0 and the reading transistor Tr1 are directly stacked together. From a process point of view, the process flow of the entire memory can be simplified, and the structure of the final memory can be simplified.

Figure 15 shows the structure of an existing 2T0C storage unit that can realize three-dimensional stacking. The 2T0C storage unit involved in the above-mentioned Figure 8, Figure 12, Figure 13 and Figure 14 of this application, and the 2T0C storage unit involved in Figure 15 In contrast, in FIG. 15, in order to realize the electrical connection between the writing transistor Tr0 and the reading transistor Tr1, a wiring layer needs to be formed between the writing transistor Tr0 and the reading transistor Tr1, for example, a dielectric layer is formed between the writing transistor Tr0 and the reading transistor Tr1. layer, and conduct conduction through the dielectric layer to electrically connect the write transistor Tr0 and the read transistor Tr1, however, the memory cell provided in this application does not need to be provided with a conductive channel. In this way, not only the manufacturing process is simplified, but also the memory structure is simplified. In addition, the signal communication path between the write transistor Tr0 and the read transistor Tr1 can be shortened to improve the signal transmission efficiency, and further increase the read and write speed.

In some optional process structures, in the 2T0C memory cells involved in the above-mentioned FIG. 8, FIG. 12, FIG. 13 and FIG. ) and the probability of conductive material diffusion in the contact area of the semiconductor layer, and reduce the Fermi pinning problem of the contact, an insulating layer can be inserted at the contact interface between the first pole and the semiconductor layer, and the second pole and the semiconductor layer. That is, the problem of Fermi pinning is alleviated through an insulating layer, where the thickness of the insulating layer may be 0.1-2 nm.

The materials that can be selected for the respective electrodes of the above-mentioned writing transistor Tr0 and reading transistor Tr1 will be described below.

The materials of the above-mentioned first common electrode 104, second common electrode 105, gate 108 and first electrode 101 are all conductive materials, such as metal materials. In an alternative embodiment, the materials of the first pole 51 and the second pole 52 can be TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In- One or more of conductive materials such as Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).

The materials of the above-mentioned semiconductor layer 106 and semiconductor layer 102 can be Si (silicon), poly-Si (p-Si, polysilicon), amorphous-Si (a-Si, amorphous silicon), In-Ga-Zn-O ( IGZO (Indium Gallium Zinc Oxide) multi-component compound, ZnO (Zinc Oxide), ITO (Indium Tin Oxide), TiO ₂ (Titanium Dioxide), MoS ₂ (Molybdenum Disulfide), WS ₂ (Tungsten Disulfide) and other semiconductor materials one or more.

When the memory 300 is a dynamic random access memory DRAM, the materials of the gate dielectric layer 107 and the gate dielectric layer 103 can be SiO ₂ (silicon dioxide), Al ₂ O ₃ (aluminum oxide), HfO ₂ (hafnium dioxide ), ZrO ₂ (zirconia), TiO ₂ (titanium dioxide), Y ₂ O ₃ (yttrium trioxide) and Si ₃ N ₄ (silicon nitride) and other insulating materials.

The material of the dielectric layer 109 can be SiO ₂ (silicon dioxide), Al ₂ O ₃ (aluminum oxide), HfO ₂ (hafnium dioxide), ZrO ₂ (zirconia), TiO ₂ (titanium dioxide), Y ₂ O ₃ ( One or more of insulating materials such as diyttrium trioxide) and Si ₃ N ₄ (silicon nitride).

When the memory 300 is a ferroelectric random access memory FeRAM, the gate dielectric layer 107 and the gate dielectric layer 103 can be selected from ZrO ₂ (zirconia), HfO ₂ (hafnium dioxide), Al-doped HfO ₂ , Si Doped with HfO ₂ , Zr doped with HfO ₂ , La doped with HfO ₂ , Y doped with HfO ₂ and other ferroelectric materials or one or more of materials based on the material doped with other elements; the dielectric layer 109 The material can be SiO ₂ (silicon dioxide), Al ₂ O ₃ (alumina), HfO ₂ (hafnium oxide), ZrO ₂ (zirconia), TiO ₂ (titania), Y ₂ O ₃ (yttrium trioxide ) and Si ₃ N ₄ (silicon nitride) and other insulating materials.

The present application provides specific preparation methods for preparing various memory cell structures, which will be explained in detail below.

Fig. 16 is a block diagram of the process of preparing memory provided by the present application, which specifically includes the following:

Step S1: forming a first transistor and a second transistor on the substrate, the first transistor and the second transistor both include a gate, a first pole and a second pole, the first pole of the first transistor and the gate of the second transistor electrically connected, the second pole of the first transistor is electrically connected with the second pole of the second transistor.

Step S2: forming the first control line, the second control line and the third control line, and the gate of the first transistor is electrically connected to the first control line, the first electrode of the second transistor is electrically connected to the second control line, and the electric The connected second poles of the first transistor and the second transistor are electrically connected with the third control line.

It should be noted that the step S1 and step S2 given above are not limited to the process flow, step S1 is executed first, and then step S2 is executed. In some optional process flows, step S1 and step S2 may be performed simultaneously; or part of the process in step S2 may be performed simultaneously with step S1; or part of the process in step S1 may be performed simultaneously with step S2.

The specific technological process involved in the above-mentioned step S2 and step S2 will be introduced below in conjunction with the accompanying drawings.

17a to 17e show cross-sectional views of the process structure after each step in the process of manufacturing a memory cell involved in the present application.

As shown in FIG. 17 a , along the direction perpendicular to the substrate, a first conductive layer 001 , a first semiconductor material layer 002 and a second conductive layer 003 are sequentially above the substrate.

Here, the first conductive layer 001 and the second conductive layer 003 can be made of metal materials, such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In -One or more of conductive materials such as Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).

The first semiconductor material layer 002 here can be Si (silicon), poly-Si (p-Si, polysilicon), amorphous-Si (a-Si, amorphous silicon), In-Ga-Zn-O (IGZO, indium Gallium zinc oxide) compound, ZnO (zinc oxide), ITO (indium tin oxide), TiO ₂ (titanium dioxide), MoS ₂ (molybdenum disulfide), WS ₂ (tungsten disulfide) and other semiconductor materials or Various.

As shown in Figure 17b, a groove 004 is opened in the stacked first conductive layer 001, first semiconductor material layer 002 and second conductive layer 003, and the groove 004 passes through the second conductive layer 003, penetrating through the first semiconductor material layer 002 part. That is to say, the groove 004 only penetrates the second conductive layer 003 and does not penetrate the first semiconductor material layer 002 .

As shown in Fig. 17c, a first dielectric material layer 005 is formed on the bottom and side surfaces of the groove 004, and then a third conductive layer 006 is formed in the remaining space of the groove 004.

Here, the optional material of the third conductive layer 006 can refer to the above-mentioned first conductive layer 001 and second conductive layer 003 , which will not be repeated here.

The first dielectric material layer 005 can be selected from SiO ₂ (silicon dioxide), Al ₂ O ₃ (aluminum oxide), HfO ₂ (hafnium dioxide), ZrO ₂ (zirconia), TiO ₂ (titania), Y ₂ O ₃ (yttrium trioxide) and Si ₃ N ₄ (silicon nitride) and other insulating materials or one or more.

As shown in Figure 17d, on the second conductive layer 003 including the first dielectric material layer 005 and the third conductive layer 006, the second semiconductor material layer 007, the second dielectric material layer 008 and the fourth conductive layer 009 are sequentially stacked .

For the optional materials for the second semiconductor material layer 007 , the second dielectric material layer 008 and the fourth conductive layer 009 in this process step, reference may be made to the above-mentioned corresponding semiconductor materials, dielectric materials and conductive materials.

As shown in Figure 17e, a through hole 010 is opened, so that the through hole 010 sequentially penetrates through the fourth conductive layer 009, the second dielectric material layer 008, the second semiconductor material layer 007, the third conductive layer 006, and the first dielectric material layer 005 , the second wire layer 003 , the first semiconductor material layer 002 and the first conductive layer 001 . Thus, the stacked write transistor Tr0 and read transistor Tr1 are formed.

18a to 18h show cross-sectional views of the process structure after each step in the process of manufacturing another memory cell involved in the present application.

As shown in Fig. 18a, along the direction perpendicular to the substrate, the first conductive layer 001, the first dielectric material layer 005 and the second conductive layer 003 are successively above the substrate.

As shown in Figure 18b, a groove 004 is opened in the stacked first conductive layer 001, first dielectric material layer 005 and second conductive layer 003, and the groove 004 passes through the second conductive layer 003 and through the first dielectric material layer. Material layer 005.

As shown in FIG. 18c , a first semiconductor material layer 002 is formed on the bottom and side surfaces of the groove 004 .

As shown in Fig. 18d, the first semiconductor material layer 002 on the bottom surface of the groove 004 is removed.

As shown in FIG. 18e , a second dielectric material layer 008 is formed on the bottom surface of the groove 004 and side surfaces of the first semiconductor material layer 002 , and a third conductive layer 006 is formed in the remaining space of the groove 004 .

As shown in FIG. 18f, the third conductive layer 006 and the second dielectric material layer 008 on the surface of the second conductive layer 003 are removed.

As shown in FIG. 18g , the second semiconductor material layer 007 , the third dielectric material layer 011 and the fourth conductive layer 009 are stacked in sequence.

As shown in Figure 18h, a through hole 010 is opened so that the through hole 010 sequentially passes through the fourth conductive layer 009, the third dielectric material layer 011, the second semiconductor material layer 007, the third conductive layer 006, and the first dielectric material layer 005 , the second wire layer 003 , the first semiconductor material layer 002 and the first conductive layer 001 . Thus, the stacked write transistor Tr0 and read transistor Tr1 are formed.

19a to 19h show cross-sectional views of the process structure after each step in the process of manufacturing another memory cell involved in the present application.

As shown in Fig. 19a, along the direction perpendicular to the substrate, a first conductive layer 001, a first dielectric material layer 005 and a second conductive layer 003 are sequentially placed above the substrate.

As shown in Figure 19b, a groove 004 is opened in the stacked first conductive layer 001, first dielectric material layer 005 and second conductive layer 003, and the groove 004 passes through the second conductive layer 003 and through the first dielectric material layer. The material layer 005, and the part passing through the first conductive layer 001.

As shown in FIG. 19c , a first semiconductor material layer 002 is formed on the bottom and side surfaces of the groove 004 .

As shown in Fig. 19d, the first semiconductor material layer 002 on the bottom surface of the groove 004 is removed.

As shown in FIG. 19e , a second dielectric material layer 008 is formed on the bottom surface of the groove 004 and side surfaces of the first semiconductor material layer 002 , and a third conductive layer 006 is formed in the remaining space of the groove 004 .

As shown in FIG. 19f, the third conductive layer 006 and the second dielectric material layer 008 on the surface of the second conductive layer 003 are removed.

As shown in FIG. 19g , the second semiconductor material layer 007 , the third dielectric material layer 011 and the fourth conductive layer 009 are stacked in sequence.

As shown in Figure 19h, a through hole 010 is opened so that the through hole 010 sequentially penetrates through the fourth conductive layer 009, the third dielectric material layer 011, the second semiconductor material layer 007, the third conductive layer 006, and the first dielectric material layer 005 , the second wire layer 003 , the first semiconductor material layer 002 and the first conductive layer 001 . Thus, the stacked write transistor Tr0 and read transistor Tr1 are formed.

20a to 20h show cross-sectional views of the process structure after each step in the process of manufacturing another memory cell involved in the present application.

As shown in Fig. 20a, along the direction perpendicular to the substrate, a first conductive layer 001, a first dielectric material layer 005 and a second conductive layer 003 are sequentially formed above the substrate.

As shown in Figure 20b, a groove 004 is opened in the stacked first conductive layer 001, first dielectric material layer 005 and second conductive layer 003, and the groove 004 passes through the second conductive layer 003 and through the first dielectric material layer. The material layer 005, and the part passing through the first conductive layer 001.

As shown in FIG. 20c , a first semiconductor material layer 002 is formed on the bottom and side surfaces of the groove 004 .

As shown in FIG. 20d , the bottom surface of the groove 004 and the first semiconductor material layer 002 close to the opening of the groove are removed from the sides of the groove 004 .

As shown in FIG. 20e , a second dielectric material layer 008 is formed on the bottom surface of the groove 004 and side surfaces of the first semiconductor material layer 002 , and a third conductive layer 006 is formed in the remaining space of the groove 004 .

As shown in Fig. 20f, the third conductive layer 006 and the second dielectric material layer 008 on the surface of the second conductive layer 003 are removed.

As shown in FIG. 20g , the second semiconductor material layer 007 , the third dielectric material layer 011 and the fourth conductive layer 009 are stacked in sequence.

As shown in Figure 20h, a through hole 010 is opened so that the through hole 010 sequentially penetrates through the fourth conductive layer 009, the third dielectric material layer 011, the second semiconductor material layer 007, the third conductive layer 006, and the first dielectric material layer 005 , the second wire layer 003 , the first semiconductor material layer 002 and the first conductive layer 001 . Thus, a stacked write transistor Tr0 and read transistor Tr1 are formed.

The corresponding methods for preparing memory cells with four different structures are given above. Of course, in other optional implementation manners, other methods may also be used to prepare the electrode-sharing write transistor and read transistor structures involved in this application.

In the description of this specification, specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in an appropriate manner.

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims

A memory, characterized in that, comprising:

Substrate;

At least one memory unit formed on the substrate, the memory unit comprising:

a first transistor and a second transistor, each of which includes a gate, a first pole, and a second pole;

a first control line, a second control line and a third control line;

Wherein, the first pole of the first transistor is electrically connected to the gate of the second transistor, the second pole of the first transistor is electrically connected to the second pole of the second transistor, and the first transistor The gate of the grid is electrically connected to the first control line;

The first pole of the second transistor is electrically connected to the second control line, and the electrically connected second pole of the first transistor and the second pole of the second transistor are electrically connected to the third control line .
The memory according to claim 1, wherein the first transistor and the second transistor are stacked in a direction perpendicular to the substrate.
The memory according to claim 1 or 2, wherein the gate of the second transistor shares the same electrode with the first electrode of the first transistor, and the gate of the second transistor shares the same electrode with the first electrode of the first transistor. The electrode shared by the first pole of the transistor is the first common electrode, the second pole of the second transistor shares the same electrode with the second pole of the first transistor, and the second pole of the second transistor shares the same electrode with the second pole of the first transistor. The electrode common to the second electrodes of a transistor is the second common electrode.
The memory according to claim 3, characterized in that,

The second common electrode has a first side perpendicular to the substrate, and has a second side parallel to the substrate;

The first common electrode is located on a side facing the first side;

The first pole of the second transistor is located on the side facing the second side;

The gate of the first transistor is located on a side of the first common electrode and the second common electrode away from the first electrode of the second transistor.
The memory according to claim 4, wherein the second transistor further comprises a semiconductor layer;

In the second transistor, the semiconductor layer includes a first semiconductor portion and a second semiconductor portion in contact, and the extension direction of the first semiconductor portion is perpendicular to the substrate, and the second semiconductor portion The extension direction is parallel to the substrate;

the first semiconducting portion is in contact with the second side, the second semiconducting portion is in contact with a third side;

The third side is a surface where the first electrode of the second transistor faces the second common electrode.
The memory according to claim 5, wherein the second transistor further comprises a gate dielectric layer;

Between the first common electrode and the second common electrode, between the first common electrode and the first semiconductor portion, and between the first common electrode and the second semiconductor portion are all The gate dielectric layer is isolated.
The memory according to claim 4, wherein the second transistor further comprises a semiconductor layer;

In the second transistor, the semiconductor layer includes a first semiconductor portion, and the extending direction of the first semiconductor portion is perpendicular to the substrate;

An end of the first semiconductor portion close to the second common electrode is in contact with the first side, and an end of the first semiconductor portion close to the first electrode of the second transistor is in contact with the third side;

The third side is a surface where the first electrode of the second transistor faces the second common electrode.
The memory according to claim 7, wherein the second transistor further comprises a gate dielectric layer and a dielectric layer;

Between the first common electrode and the first semiconductor part, between the first common electrode and the first electrode of the second transistor are all separated by the gate dielectric layer, and the second common electrode and the first electrode of the second transistor are separated by the dielectric layer.
The memory according to claim 7 or 8, wherein the first electrode of the second transistor includes a first part and a second part that are in contact, the extending direction of the first part is perpendicular to the substrate, The extension direction of the second portion is parallel to the substrate, and the first portion is disposed closer to the second common electrode relative to the second portion.
The memory according to any one of claims 7-9, characterized in that, in the first transistor, the semiconductor layer is arranged on the side of the first common electrode and the second common electrode away from the one side of the first pole of the second transistor;

the first semiconductor portion is in contact with a semiconductor layer of the first transistor; or,

The first semiconductor part is isolated from the semiconductor layer of the first transistor by a gate dielectric layer.
The memory according to any one of claims 4-10, wherein the first transistor further comprises a semiconductor layer and a gate dielectric layer;

In the first transistor, the gate, the gate dielectric layer and the semiconductor layer are arranged on the first common electrode and the second common electrode which are far away from the first pole of the second transistor one side, and the gate, the gate dielectric layer and the semiconductor layer are stacked in sequence along the direction perpendicular to the substrate, and the semiconductor layer is shared with the first common electrode and the second common electrode. electrode contacts.
The memory according to any one of claims 3-11, wherein there are multiple storage units;

Both the first control line and the second control line extend along a first direction parallel to the substrate, and the first control line is electrically connected to a plurality of memory cells located in the first direction. the gate of the first transistor, the second control line is electrically connected to the first poles of the second transistors of the plurality of memory cells located in the first direction;

The third control line extends along a second direction parallel to the substrate, and the third control line is electrically connected to the second transistors of the second transistors of the plurality of memory cells located in the second direction. pole;

The second direction is perpendicular to the first direction.
The memory according to any one of claims 1-12, wherein the first transistor, the second transistor, the first control line, the second control line, the third control The wires are all formed on the substrate by a subsequent process.
The memory according to any one of claims 1-13, characterized in that,

In the writing stage, the first control line is used to receive the first write word line control signal, so that the first transistor is turned on, and the third control line is used to receive the write bit line control signal to write logic information into the storage unit.
The memory according to any one of claims 1-14, characterized in that,

In the read phase, the first control line is used to receive the second write word line control signal, so that the first transistor is turned off, the third control line is used to receive the read word line control signal, and the second control The lines are used to output signals to read the logic information in the memory cells.
A method for controlling a memory, wherein the memory includes:

at least one storage unit, the storage unit comprising:

a first transistor and a second transistor, each of which includes a gate, a first pole, and a second pole;

a first control line, a second control line and a third control line;

Wherein, the first pole of the first transistor is electrically connected to the gate of the second transistor, the second pole of the first transistor is electrically connected to the second pole of the second transistor, and the first transistor The gate of the grid is electrically connected to the first control line;

The first pole of the second transistor is electrically connected to the second control line, and the electrically connected second pole of the first transistor and the second pole of the second transistor are electrically connected to the third control line ;

The control methods include:

In the writing stage, the first control line is used to receive the first write word line control signal, so that the first transistor is turned on, and the third control line is used to receive the write bit line control signal to write logic information into the storage unit.
The control method of the memory according to claim 16, wherein the control method further comprises:

In the read phase, the first control line is used to receive the second write word line control signal, so that the first transistor is turned off, the third control line is used to receive the read word line control signal, and the second control The lines are used to output signals to read the logic information in the memory cells.
The method for controlling a memory according to claim 16 or 17, wherein the first transistor and the second transistor are stacked in a direction perpendicular to the substrate.
The memory control method according to claim 17, wherein:

The gate of the second transistor shares the same electrode with the first pole of the first transistor, and the second pole of the second transistor shares the same electrode with the second pole of the first transistor.
A method for forming a memory, characterized in that the method for forming includes:

A first transistor and a second transistor are formed on a substrate, and each of the first transistor and the second transistor includes a gate, a first pole, and a second pole, and the first pole of the first transistor is connected to the first pole. The gates of the two transistors are electrically connected, and the second pole of the first transistor is electrically connected with the second pole of the second transistor;

A first control line, a second control line and a third control line are formed, and the gate of the first transistor is electrically connected to the first control line, and the first electrode of the second transistor is connected to the second control line. The line is electrically connected, and the electrically connected second pole of the first transistor and the second pole of the second transistor are electrically connected with the third control line.
The method for forming a memory according to claim 20, wherein forming the first transistor and the second transistor on the substrate comprises:

Along a direction perpendicular to the substrate, the first transistor and the second transistor are stacked to form.
The method for forming a memory according to claim 21, wherein:

When forming the second transistor, including:

forming a first electrode of the second transistor;

A gate and a second pole are formed on a side of the first pole of the second transistor away from the substrate, and the second pole has a first side perpendicular to the substrate, the gate on the side facing the first side;

When forming the first transistor, including:

The gate of the first transistor is formed on the side away from the substrate of the gate and the second pole of the second transistor, and the gate of the second transistor is connected to the first pole of the first transistor. share the same electrode, and the second electrode of the second transistor shares the same electrode with the second electrode of the first transistor.
An electronic device, characterized in that it comprises:

processor; and

The memory according to any one of claims 1 to 15, or the memory made by the method for forming a memory according to any one of claims 20 to 22;

Wherein, the processor is electrically connected to the memory.