WO2023197706A1

WO2023197706A1 - Field-effect transistor, memory and electronic device

Info

Publication number: WO2023197706A1
Application number: PCT/CN2023/071187
Authority: WO
Inventors: 黄凯亮; 景蔚亮; 殷士辉; 冯君校; 王正波
Original assignee: 华为技术有限公司
Priority date: 2022-04-15
Filing date: 2023-01-09
Publication date: 2023-10-19
Also published as: CN116978955A

Abstract

Provided in the present application are a field-effect transistor, a memory and an electronic device. The field-effect transistor comprises a laminated structure, a channel layer, a gate oxide layer and a gate electrode, wherein the laminated structure comprises a source electrode, a first isolation dielectric layer and a drain electrode, which are sequentially arranged in a stacked manner, and the laminated structure has a through groove, which penetrates same from an upper surface of the drain electrode to the source electrode; and the channel layer covers side walls and the bottom of the through groove, the gate oxide layer covers side walls and the bottom of the channel layer, and the gate electrode covers side walls of the gate oxide layer. Compared with a planar field-effect transistor, the field-effect transistor is equivalent to spatially rotating two planar field-effect transistors to make channel layers thereof vertical, short-circuiting source electrodes of the two transistors which have the vertical channel layers, and connecting the channel layers thereof to one another. Since the channel layers are vertically distributed, the horizontal projection area of the field-effect transistor can be reduced compared with a planar field-effect transistor.

Description

A field effect transistor, memory and electronic device

Cross-references to related applications

This application claims priority to a Chinese patent application filed with the China Patent Office on April 15, 2022, with application number 202210400028.9 and application title "A field effect transistor, memory and electronic device", the entire content of which is incorporated by reference. in this application.

Technical field

The present application relates to the field of semiconductor technology, and in particular to a field effect transistor, a memory and an electronic device.

Background technique

Memory is a memory device used to store information in modern information technology. Traditional dynamic random access memory (Dynamic Random Access Memory, DRAM) uses complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) logic tubes as the peripheral circuit of the memory unit in the front line. The negative impact is that The consumption of integrated area and the cost increase, and the memory based on the back end of line (BEOL) process can move the peripheral circuits below the memory array, which can significantly reduce the footprint of the memory die.

In BEOL-based memories, back-end integrated thin film field effect transistors (TFTs) are used as gate tubes. Although the area of front-end logic can be saved, the current TFTs are mainly planar as shown in Figure 1. Type transistor, when the characteristic length of photolithography is F, the horizontal projected area of a single TFT can reach 6F ² (3F×2F). The larger area of a single TFT will become one of the bottlenecks limiting the storage density of the memory.

Contents of the invention

The present application provides a field effect transistor, a memory and an electronic device, which are used to provide a field effect transistor with a small horizontal projection area.

In a first aspect, embodiments of the present application provide a field effect transistor, which mainly includes a stacked structure, a channel layer, a gate oxide layer and a gate electrode. The stacked structure may include a source electrode, a first isolation dielectric layer and a drain electrode stacked in sequence, and the stacked structure may have a through groove, and the through groove penetrates from the upper surface of the drain electrode to the source electrode. The channel layer covers the sidewalls and bottom of the trench, the gate oxide layer covers the sidewalls and bottom of the channel layer, and the gate electrode covers the sidewalls of the gate oxide layer. Compared with planar field effect transistors, the field effect transistor provided by this application is equivalent to spatially rotating two planar field effect transistors so that their channel layers are in a vertical direction, and two planar field effect transistors have vertical channels. The sources of the transistors in each layer are short-circuited and the channel layers are connected. This field effect transistor can reduce the horizontal projected area compared to a planar field effect transistor because the channel layer is distributed vertically. In addition, the channel length of the field-effect transistor is defined by the film thickness between the source and drain, so short-channel devices can be realized without advanced manufacturing processes, thereby reducing process difficulty.

For example, in the field effect transistor, the through trench can penetrate part of the source electrode, which can increase the contact area between the channel layer and the source electrode.

It should be noted that in this application, only one gate may be provided in the field effect transistor, and of course, two gates may also be provided, which is not limited here.

For example, in this application, when only one gate is provided in the field effect transistor, the gate can completely fill the area defined by the gate oxide layer, so that when the two drains in the field effect transistor are short-circuited, the field effect transistor can be The transistor's current is twice that of a single planar field-effect transistor.

For example, in the field effect transistor, two gate electrodes are arranged at intervals in the channel. In this way, the channel layers located on the sidewalls on both sides of the trench can each correspond to a gate, and can control two transistors respectively, thereby achieving two transistors in an area close to ^4F2 .

Further, in this application, the channel layer may include an N-type channel region and a P-type channel region, and the N-type channel region and the P-type channel region are respectively located on both sides of the gate. By regional doping or zoned deposition of the material of the channel layer, one channel is made of N-type material and the other channel is made of P-type material. Therefore, the field effect transistor includes two transistors: an N-type transistor and a P-type transistor. In this field effect transistor, two transistors, the N-type transistor and the P-type transistor, share a gate electrode, thereby forming a CMOS inverter.

For example, based on the above field effect transistor, both the channel layer and the gate oxide layer can also extend above the stacked structure. This can increase the contact area between the drain electrode and the channel layer.

Furthermore, the gate can also be extended above the stacked structure to increase the area facing the gate and the channel layer, which can improve the gate's ability to control the field effect transistor, thus improving the performance of the device.

Exemplarily, in the field effect transistor, the stacked structure further includes a second isolation dielectric layer located between the drain electrode and the first isolation dielectric layer, and a second isolation dielectric layer located between the second isolation dielectric layer and the first isolation dielectric layer. Back gate; the channel runs from the upper surface of the drain to the source. The field effect transistor also needs to set up a third isolation dielectric layer between the side wall of the channel and the channel layer, so that the back gate and the channel layer pass through the third The isolation dielectric layer achieves isolation. In this field effect transistor, the added back gate can be used to adjust the carrier concentration of the channel layers on both sides, thereby achieving threshold control and increasing the current, which can lead to performance optimization. Moreover, the introduction of the back gate will not significantly increase the process difficulty and has strong applicability.

It should be noted that in specific implementation, the source and drain of the field effect transistor can be interchanged, and no specific distinction is made.

For example, the source electrode and the drain electrode can be formed of conductive materials such as TiN, Ti, Au, W, Mo, In-Ti-O (ITO), Al, Cu, Ru, Ag, or any combination thereof, where Not limited.

For example, the gate electrode and the back gate electrode may be formed of conductive materials such as metal, such as TiN, Ti, Au, W, Mo, ITO, Al, Cu, Ru, Ag, or any combination thereof.

For example, the gate oxide layer can use insulating materials such as SiO ₂ , Al ₂ O ₃ , HfO ₂ , ZrO _{2 , TiO 2} _, Y ₂ O ₃ , Si ₃ N ₄ or any combination of materials, stacked structures and combinations thereof. The material is formed in a laminated structure, which is not limited here.

For example, the channel layer can be formed of semiconductor materials, such as Si, polycrystalline Si, amorphous Si, In-Ga-Zn-O (IGZO) multicomponent compounds, ZnO, ITO, TiO ₂ , MoS ₂ and other semiconductor materials, or any combination of them.

For example, the first isolation dielectric layer, the second isolation dielectric layer and the third isolation dielectric layer can be formed of insulating materials, such as SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ and other insulating materials, which are not limited here.

In a second aspect, embodiments of the present application also provide a memory, which includes a memory cell array and a gate array corresponding to the memory cell array. In specific implementation, the memory cell array may be stacked above the gate array. The gate array includes a plurality of field effect transistors as described in the first aspect or various embodiments of the first aspect. Since the horizontal projected area of the field effect transistor provided by the embodiment of the present application is small, it can be achieved High-density three-dimensional memory.

It should be noted that this embodiment is only applicable to field effect transistors in which the channel layer is an N-type channel layer or field effect transistors in which the channel layer is a P-type channel layer. That is to say, the field effect transistor whose channel layer includes an N-type channel region and a P-type channel region provided in the above embodiments is not suitable for this memory.

In specific implementation, when the field effect transistor includes a gate, one field effect transistor is used as a strobe in the strobe array, and the current can be increased based on the unit area of 4F ² , so that the current can be increased. Effectively improve reading and writing speed.

In specific implementation, when the field effect transistor includes two gates, one field effect transistor is used as two gates in the gate array. Two strobe tubes can be implemented on a unit area of ^4F2 , thus enabling high-density memory exceeding the unit area of ^4F2 .

In a third aspect, an embodiment of the present application further provides another memory, which includes a memory cell array, and the memory cells in the memory cell array include the above-mentioned field effect transistor provided by the embodiment of the present application. Since the horizontal projected area of the field effect transistor provided by the embodiment of the present application is small, a high-density three-dimensional memory can be realized.

For example, in this memory, the memory unit may include two field effect transistors, the two field effect transistors are a first field effect transistor and a second field effect transistor located on the first field effect transistor, and the first field effect transistor is The gate of the field effect transistor is electrically connected to the source of the second field effect transistor, thereby forming a 2T0C memory cell structure.

Specifically, during the "write" operation, the turn-on of the second field effect transistor is controlled through the gate of the second field effect transistor, and the potential on the drain of the second field effect transistor is passed through the gate of the second field effect transistor. The source is passed to the gate of the first field effect transistor to write data "1" or "0". Subsequently, the second field effect transistor is controlled to turn off through the gate of the second field effect transistor. The potential output by the memory cell will be determined by the amount of charge stored at that node. During the "read" operation, you only need to control the drain of the first field effect transistor, read the current on the source of the first field effect transistor, and judge the state of the memory cell based on the level of the current.

It should be noted that in this embodiment, the same is only applicable to field effect transistors in which the channel layer is an N-type channel layer or field effect transistors in which the channel layer is a P-type channel layer. That is to say, the field effect transistor whose channel layer includes an N-type channel region and a P-type channel region provided in the above embodiments is not suitable for this memory.

It is worth noting that the field effect transistor provided by the embodiment of the present application can be applied not only in memories, but also in other electronic devices, which is not limited here.

In a fourth aspect, embodiments of the present application further provide an electronic device. The electronic device may include a circuit board, and a field effect transistor as described in the first aspect or various embodiments of the first aspect, connected to the circuit board. . The problem-solving principle of this electronic device is similar to that of the aforementioned field-effect transistor. Therefore, the implementation of this electronic device can refer to the implementation of the aforementioned field-effect transistor, and repeated details will not be repeated.

In a fifth aspect, embodiments of the present application further provide an electronic device. The electronic device includes a processor and a memory coupled to the processor. The memory may be the memory described in various implementations of the second or third aspect. . Specifically, the processor can call the software program stored in the memory to execute the corresponding method and realize the corresponding function of the electronic device.

The technical effects that can be achieved by the above-mentioned second aspect to the fifth aspect can be referred to the description of the technical effects that can be achieved by any possible design in the above-mentioned first aspect, and will not be repeated here.

Description of the drawings

Figure 1 is a schematic structural diagram of a planar transistor provided by an embodiment of the present application;

Figure 2 is a schematic structural diagram of a field effect transistor provided by an embodiment of the present application;

Figure 3 is a schematic cross-sectional view of a laminated structure provided by an embodiment of the present application;

Figure 4 is a schematic diagram of the equivalent circuit corresponding to the field effect transistor shown in Figure 3;

Figure 5 is a schematic structural diagram of another field effect transistor provided by an embodiment of the present application;

Figure 6 is a schematic structural diagram of another field effect transistor provided by an embodiment of the present application;

Figure 7 is a schematic diagram of the equivalent circuit corresponding to the field effect transistor shown in Figure 6;

Figure 8 is a schematic structural diagram of another field effect transistor provided by an embodiment of the present application;

Figure 9 is a schematic diagram of the equivalent circuit corresponding to the field effect transistor shown in Figure 8;

Figure 10 is a schematic structural diagram of another field effect transistor provided by an embodiment of the present application;

Figure 11 is a schematic diagram of the equivalent circuit corresponding to the field effect transistor shown in Figure 10;

Figure 12 is a schematic structural diagram of another field effect transistor provided by an embodiment of the present application;

Figure 13 is a schematic structural diagram of another field effect transistor provided by an embodiment of the present application;

Figure 14 is a schematic structural diagram of another field effect transistor provided by an embodiment of the present application;

Figure 15 is a schematic structural diagram of another field effect transistor provided by an embodiment of the present application;

Figure 16 is a schematic structural diagram of another field effect transistor provided by an embodiment of the present application;

Figure 17 is a schematic diagram of the equivalent circuit corresponding to the field effect transistor shown in Figure 16;

Figure 18 is a schematic structural diagram of another field effect transistor provided by an embodiment of the present application;

Figure 19 is a schematic diagram of the equivalent circuit corresponding to the field effect transistor shown in Figure 18;

Figure 20 is a schematic structural diagram of another field effect transistor provided by an embodiment of the present application;

Figure 21 is a schematic diagram of the equivalent circuit corresponding to the field effect transistor shown in Figure 20;

Figure 22 is a schematic structural diagram of another field effect transistor provided by an embodiment of the present application;

Figure 23 is a schematic diagram of the equivalent circuit corresponding to the field effect transistor shown in Figure 22;

Figures 24a to 24e are schematic structural diagrams of the preparation process of a field effect transistor according to an embodiment of the present application;

Figures 25a and 25b are structural schematic diagrams of the preparation process of a field effect transistor according to another embodiment of the present application;

Figures 26a to 26h are structural schematic diagrams of the preparation process of a field effect transistor according to another embodiment of the present application;

Figure 27 is a schematic structural diagram of a memory provided by an embodiment of the present application;

Figure 28 is a schematic circuit structure diagram of a gate array provided by an embodiment of the present application;

Figure 29 is a schematic circuit structure diagram of another strobe array provided by an embodiment of the present application;

Figure 30 is a partial cross-sectional structural schematic diagram of a gate array provided by an embodiment of the present application;

Figure 31 is a schematic diagram of the circuit structure corresponding to the strobe array shown in Figure 30;

Figure 32 is a partial cross-sectional structural diagram of another strobe array provided by an embodiment of the present application;

Figure 33 is a schematic diagram of the circuit structure corresponding to the strobe array shown in Figure 32;

Figure 34 is a schematic structural diagram of a memory unit provided by an embodiment of the present application;

Figure 35 is a schematic diagram of the circuit structure corresponding to the memory unit shown in Figure 34;

Figure 36 is a schematic structural diagram of an electronic device provided by an embodiment of the present application;

Figure 37 is a schematic structural diagram of another electronic device provided by an embodiment of the present application.

Explanation of reference symbols:

1-field effect transistor; 2-circuit board; 10-laminated structure; 11-channel layer; 12-gate oxide layer; 13-gate; V-channel; 01-source; 02-first isolation dielectric Layer; 03-drain; 11n-N-type channel region; 11p-P-type channel region; 04-second isolation dielectric layer; 05-back gate; 14-third isolation dielectric layer; T0-transistor; T0 (n)-N-type transistor; T0(P)-P-type transistor; 100-memory; 200-processor; 110-storage unit array; 120-strobe array; 121-strobe; Ix-control terminal; Ax-the first signal terminal; O-the second signal terminal; BLn-bit line; WLm-word line, 201-memory cell; 1a-the first field effect transistor; 13a-the gate of the first field effect transistor; 01a- The source of the first field effect transistor; 03a - the drain of the first field effect transistor; 1b - the second field effect transistor; 13b - the gate of the second field effect transistor; 01b - the source of the second field effect transistor; 03b-The drain of the second field effect transistor.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be described in further detail below in conjunction with the accompanying drawings.

It should be noted that in this specification, similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be referenced in subsequent drawings. for further definition and explanation.

In the description of this application, it should be noted that the terms "middle", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description. It does not indicate or imply that the device or element referred to must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limitations on this application. The words expressing position and direction described in this application are all explained by taking the accompanying drawings as examples, but they can be changed as needed, and all changes are included in the protection scope of the present invention. The drawings in this application are only used to illustrate relative positional relationships and do not represent true proportions. In addition, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance.

In order to facilitate understanding of the technical methods provided by the embodiments of this application, its application scenarios are first introduced below. The field effect transistor provided by the embodiment of the present application can be applied in a BEOL-based memory. This memory can be used for data storage in electronic devices such as mobile phones, tablets, laptops, wearable devices, and vehicle-mounted devices. Of course, the field effect transistor and memory provided by this application can also be applied to other electronic devices, which are not limited here.

The field effect transistor, memory and electronic equipment in the technical solution of the present application will be described below with reference to the accompanying drawings.

Referring to Figure 2, Figure 2 is a schematic structural diagram of a field effect transistor provided by an embodiment of the present application. The field effect transistor 1 mainly includes a stacked structure 10, a channel layer 11, a gate oxide layer 12 and a gate electrode 13. Referring to Figure 3, Figure 3 is a schematic cross-sectional view of a stacked structure provided by an embodiment of the present application. The stacked structure 10 may include a source electrode 01, a first isolation dielectric layer 02 and a drain electrode that are stacked sequentially along the direction Z. 03, and the laminated structure 10 has a through groove V. The through groove V penetrates from the upper surface of the drain electrode 03 to the source electrode 01 in the stacking direction Z of the laminated structure 10 . Continuing to refer to FIG. 2 , in this field effect transistor 1 , the channel layer 11 covers the sidewalls and bottom of the trench, the gate oxide layer 12 covers the sidewalls and bottom of the channel layer 11 , and the gate electrode 13 covers the gate oxide layer 12 side walls. The equivalent circuit corresponding to the field effect transistor provided by this application is shown in Figure 4. Compared with the planar field effect transistor, the field effect transistor 1 is equivalent to spatially rotating two planar field effect transistors, so that The channel layer is in a vertical direction, and the sources 01 of the two transistors T0 with vertical channel layers are short-circuited, and the channel layers 11 are connected. Because the channel layer of this field effect transistor is distributed vertically, the horizontal projected area can be reduced compared to the planar field effect transistor, and its horizontal projected area can reach 4F ² . In addition, the channel length of the field effect transistor 1 is defined by the thickness of the film layer between the source electrode 01 and the drain electrode 03 (the thickness of the first isolation dielectric layer 02 in Figure 2), so it can achieve short circuit length without advanced manufacturing processes. Channel devices, thereby reducing process difficulty.

Referring to Figure 5, Figure 5 is a schematic structural diagram of another field effect transistor provided by an embodiment of the present application. In this field effect transistor 1, the channel V can penetrate part of the source electrode 01, which can increase the contact area between the channel layer 11 and the source electrode 01.

It should be noted that in this application, only one gate 13 may be provided in the field effect transistor 1 , and of course, two gates 13 may also be provided, which is not limited here.

For example, in this application, as shown in FIGS. 2 and 5 , when only one gate 13 is provided in the field effect transistor 1 , the gate 13 can completely fill the area defined by the gate oxide layer 12 .

Optionally, in this application, when in use, when the two drains 03 in the field effect transistor 1 shown in Figures 2 and 5 are short-circuited, the current of the field effect transistor 1 can be made into a single plane field. effect transistor twice.

For example, see FIG. 6 and FIG. 7 . FIG. 6 is a schematic structural diagram of yet another field effect transistor provided by an embodiment of the present application. FIG. 7 is a schematic equivalent circuit diagram corresponding to the field effect transistor shown in FIG. 6 . In this field effect transistor 1, two gate electrodes 13 are provided at intervals in the channel. In this way, the channel layer 11 located on the sidewalls on both sides of the trench can each correspond to a gate 13, as shown in Figure 7, so that the two transistors T0 can be controlled respectively, achieving two transistors in an area close to ^4F2 .

Further, in this application, on the basis of the field effect transistor 1 shown in FIGS. 2, 5 and 6, as shown in FIGS. 8 and 10, the channel layer 11 may include N-type channel regions 11n and P Type channel region 11p, N-type channel region 11n and P-type channel region 11p are located on both sides of the gate electrode 13 respectively. During specific implementation, one channel region can be made of N-type material and the other channel region can be made of P-type material by regional doping or zoned deposition of the material of the channel layer 11 . Referring to Figures 9 and 11, Figure 9 is a schematic diagram of the equivalent circuit corresponding to the field effect transistor shown in Figure 8. Figure 11 is a schematic diagram of the equivalent circuit corresponding to the field effect transistor shown in Figure 10. In this field effect transistor 1 , including two transistors: N-type transistor T0(n) and P-type transistor T0(P).

Continuing to refer to FIGS. 8 and 9 , in the field effect transistor 1 , the N-type transistor T0(n) and the P-type transistor T0(P) share a gate electrode, thereby forming a CMOS inverter.

For example, based on the above-mentioned field effect transistor, as shown in FIGS. 12 to 15 , both the channel layer 11 and the gate oxide layer 12 can also be extended to the top of the stacked structure 10 , thereby increasing the drain electrode 03 and the gate oxide layer 12 . The contact area of the channel layer 11.

Further, continuing to refer to FIGS. 12 to 15 , the gate 13 can also be extended above the stacked structure 10 to increase the facing area between the gate 13 and the channel layer 11 , thereby increasing the effect of the gate 13 on the field effect transistor. 1’s control capabilities, thereby improving device performance.

Exemplarily, refer to Figures 16 to 23. Figure 16 is a schematic structural diagram of yet another field effect transistor provided by an embodiment of the present application. Figure 17 is a schematic equivalent circuit diagram corresponding to the field effect transistor shown in Figure 16. Figure 18 is Another schematic structural diagram of a field effect transistor provided by an embodiment of the present application. Figure 19 is a schematic equivalent circuit diagram corresponding to the field effect transistor shown in Figure 18. Figure 20 is a structural schematic diagram of another field effect transistor provided by an embodiment of the present application. Schematic diagram. Figure 21 is a schematic diagram of the equivalent circuit corresponding to the field effect transistor shown in Figure 20. Figure 22 is a schematic structural diagram of another field effect transistor provided by an embodiment of the present application. Figure 23 is a schematic diagram corresponding to the field effect transistor shown in Figure 22. Equivalent circuit diagram. In the field effect transistor 1, the stacked structure 10 also includes a second isolation dielectric layer 04 between the drain electrode 03 and the first isolation dielectric layer 02, and a second isolation dielectric layer 04 between the second isolation dielectric layer 04 and the first isolation dielectric layer 02. The back gate 05 between them; the channel runs from the upper surface of the drain 03 to the source 01. The field effect transistor 1 also needs to set a third isolation dielectric layer 14 between the side wall of the channel and the channel layer 11, so that the back gate The gate electrode 05 and the channel layer 11 are isolated by the third isolation dielectric layer 14 . In this field effect transistor 1, the added back gate 05 can be used to adjust the carrier concentration of the channel layer 11 on both sides of the gate 13, thereby achieving threshold control and increasing the current, which can lead to performance optimization. . Moreover, the introduction of the back gate 05 will not significantly increase the process difficulty and has strong applicability.

In order to facilitate understanding of the field effect transistor provided in the embodiment of the present application, the above field effect transistor provided in the embodiment of the present application will be further described below in conjunction with the preparation method.

Embodiment 1

Taking the field effect transistor shown in Figure 12 as an example, combined with Figures 24a to 24e, preparing the field effect transistor may include the following steps:

Referring to Figure 24a, the source electrode 01, the first isolation dielectric layer 02 and the drain electrode 03 are sequentially epitaxially epitaxially formed to form a stacked structure 10.

Referring to FIG. 24b, the through groove V may be formed in the stacked structure 10 through an etching process.

Referring to Figure 24c, a channel layer 11 is formed covering the upper surface of the stacked structure 10, the sidewalls and the bottom of the via V.

Alternatively, when forming the channel layer 11, regional doping or zoned deposition can be used to realize that the channel layer on one side is an N-type channel region and the channel layer on the other side is a P-type channel region.

Referring to Figure 24d, the gate oxide layer 12 covering the channel layer 11 can be formed by atomic layer deposition (ALD) or chemical vapor deposition (Chemical Vapor Deposition, CVD).

Referring to FIG. 24e , the gate electrode 13 filling the area defined by the gate oxide layer 12 and covering the exposed upper surface of the gate oxide layer 12 may be formed by an ALD or CVD method.

In specific implementation, when preparing field effect transistors, multiple field effect transistors are generally formed at the same time. Therefore, multiple field effect transistors need to be isolated through an etching process after formation. For example, the gate electrode 13, the gate oxide layer 12 and the channel layer 11 can be etched through a dry etching process to form the field effect transistor 1 as shown in FIG. 12 to achieve device isolation.

For the preparation method of the field effect transistor shown in FIG. 2, FIG. 5, FIG. 8 and FIG. 13, reference can be made to Embodiment 1, which will not be described again here.

Embodiment 2.

Taking the field effect transistor shown in Figure 14 as an example, combined with Figures 24a to 24d and Figures 25a and 25b, preparing the field effect transistor may include the following steps:

Referring to FIG. 24d, the gate oxide layer 12 covering the channel layer 11 may be formed by ALD or CVD.

Referring to FIG. 25a, the gate electrode 13 covering the sidewalls and bottom as well as the upper surface of the gate oxide layer 12 can be formed by ALD or CVD.

Referring to FIG. 25 b , the gate electrode 13 located at the bottom and part of the upper surface of the gate oxide layer 12 can be removed through an etching process, thereby forming two isolated gate electrodes 13 .

In specific implementation, when preparing field effect transistors, multiple field effect transistors are generally formed at the same time. Therefore, multiple field effect transistors need to be isolated through an etching process after formation. For example, the gate oxide layer 12 and the channel layer 11 can be etched through a dry etching process to form the field effect transistor 1 as shown in FIG. 14 to achieve device isolation.

For the preparation method of the field effect transistor shown in FIG. 6, FIG. 10 and FIG. 15, reference can be made to Embodiment 2, which will not be described again here.

Embodiment 3.

Taking the field effect transistor shown in Figure 20 as an example, combined with Figures 26a to 26h, preparing the field effect transistor may include the following steps:

Referring to Figure 26a, the source electrode 01, the first isolation dielectric layer 02, the back gate 05, the second isolation dielectric layer 04 and the drain electrode 03 are sequentially epitaxially epitaxially formed to form a stacked structure 10.

Referring to FIG. 26b, the through groove V may be formed in the stacked structure 10 through an etching process.

Referring to FIG. 26c, the third isolation dielectric layer 14 covering the upper surface, sidewalls and bottom of the through-trough V can be formed by ALD or CVD.

Referring to FIG. 26d , part of the third isolation dielectric layer 14 can be removed through an etching process, leaving only the third isolation dielectric layer 14 located on the sidewall of the through trench V.

Referring to Figure 26e, a channel layer 11 is formed covering the upper surface of the stacked structure 10, the sidewalls of the third isolation dielectric layer 14 and the surface of the exposed source electrode 01.

Referring to FIG. 26f, the gate oxide layer 12 covering the channel layer 11 may be formed by ALD or CVD.

Referring to FIG. 26g, the gate electrode 13 covering the sidewalls and bottom and the upper surface of the gate oxide layer 12 can be formed by ALD or CVD.

Referring to FIG. 26h, the gate electrode 13 located at the bottom and part of the upper surface of the gate oxide layer 12 can be removed through an etching process, thereby forming two isolated gate electrodes 13.

In specific implementation, when preparing field effect transistors, multiple field effect transistors are generally formed at the same time. Therefore, multiple field effect transistors need to be isolated through an etching process after formation. For example, the gate oxide layer 12 and the channel layer 11 can be etched through a dry etching process to form the field effect transistor 1 as shown in FIG. 20 to achieve device isolation.

For the preparation method of the field effect transistor shown in FIG. 16, FIG. 18 and FIG. 22, reference can be made to Embodiment 3, which will not be described again here.

Correspondingly, this application also provides a memory 100. See Figure 27. Figure 27 is a schematic structural diagram of a memory provided in an embodiment of this application. The memory 100 includes a memory cell array 110 and a gate array 120 corresponding to the memory cell array 110 . In specific implementation, the memory cell array 110 may be stacked above the gate array 120 . As shown in Figures 28 and 29, the gate array 120 includes a plurality of field effect transistors 1 provided by the above embodiments of the present application. Since the horizontal projected area of the field effect transistors provided by the embodiments of the present application is small, it can Realize high-density three-dimensional memory.

In specific implementation, referring to Figures 28, 30 and 31, when the field effect transistor 1 includes a gate 13, one field effect transistor 1 is used as a gate 121 in the gate array 120, so that The current can be increased based on the unit area of 4F ² , which can effectively increase the reading and writing speed.

Referring to Figure 30, the gate 13 of the field effect transistor 1 is the control terminal Ix of the strobe 121 (x is 0, 1, 2, 3,...), and the drain 03 of the field effect transistor 1 is the control terminal Ix of the strobe 121. The first signal terminal Ax (x is 0, 1, 2, 3,...), the source electrode 01 of the field effect transistor 1 is the second signal terminal O of the strobe 121 .

For example, in this application, in the gate array 120, multiple rows of field effect transistors 1 can be arranged in one row. In each row of field effect transistors 1, the sources 01 of multiple field effect transistors 1 can be set as an integrated structure, that is, multiple field effect transistors 1 share the source 01, and the gates 13 of different field effect transistors 1 are controlled separately. The drain 03 of the field effect transistor 1 is controlled individually.

In specific implementation, referring to FIG. 29 , FIG. 32 and FIG. 33 , when the field effect transistor 1 includes two gates 13 , one field effect transistor 1 serves as two gates 121 in the gate array 120 . Two strobe tubes can be implemented in a unit area of 4F ² , thereby achieving a high-density memory exceeding the unit area of 4F ² .

Referring to Figure 32, the two gates 13 of the field effect transistor 1 are respectively the control terminals Ix of the two corresponding strobes 121 (x is 0, 1, 2, 3,...), and the two gates 13 on both sides of the field effect transistor 1 The drains 03 are respectively the first signal terminals Ax of the two corresponding strobes 121 (x is 0, 1, 2, 3,...), and the source 01 of the field effect transistor 1 is the two strobes 121 The shared second signal terminal O.

For example, in this application, in the gate array 120, multiple rows of field effect transistors 1 can be arranged in one row. In each row of field effect transistors 1, the sources 01 of multiple field effect transistors 1 can be set as an integrated structure, that is, multiple field effect transistors 1 share the source 01, and the gates 13 of different field effect transistors 1 are controlled separately. The drain electrode 03 of the field effect transistor 1 is controlled respectively, and the two gate electrodes 13 of the same field effect transistor 1 are controlled respectively, and the two drain electrodes 03 of the same field effect transistor 1 are controlled respectively.

For example, referring to Figures 28 and 29, the strobe array 120 also includes a plurality of bit lines BLn and a plurality of word lines WLm. Each word line WLm is connected to the control terminals of a plurality of strobes 121. Each bit line The line BLn is connected to the common second signal terminals of the plurality of strobe tubes 121 .

In specific implementation, the first signal end of each gate tube is generally connected to a memory unit in the memory unit array. This application does not limit the structure of the memory unit, for example, it is a ferroelectric memory unit.

During specific implementation, the field effect transistor provided by the embodiment of the present application can be applied not only to the gate transistor in the memory, but also to the memory cell in the memory.

Correspondingly, an embodiment of the present application also provides a memory, which includes a memory cell array, and the memory cells in the memory cell array include the above-mentioned field effect transistor provided by the embodiment of the present application. Since the horizontal projected area of the field effect transistor provided by the embodiment of the present application is small, a high-density three-dimensional memory can be realized.

For example, referring to Figures 34 and 35, in this memory, the memory unit 201 may include two field effect transistors 1a and 1b. The two field effect transistors 1a and 1b are respectively the first field effect transistor 1a and the first field effect transistor 1a. The second field effect transistor 1b is on the field effect transistor 1a, and the gate electrode 13a of the first field effect transistor 1a is electrically connected to the source electrode 01b of the second field effect transistor 1b, thereby forming a 2TOC memory cell structure.

Specifically, referring to Figure 35, during the "write" operation, the turn-on of the second field effect transistor 1b is controlled through the gate 13b of the second field effect transistor 1b, and the drain electrode 03b of the second field effect transistor 1b is The potential is transferred to the gate electrode 13a of the first field effect transistor 1a through the source electrode 01b of the second field effect transistor 1b, thereby realizing the writing of data "1" or "0". Subsequently, the second field effect transistor 1b is controlled to be turned off through the gate electrode 13b of the second field effect transistor 1b. The potential output by memory cell 201 will be determined by the amount of charge stored at that node. During the "read" operation, you only need to read the current on the source 01a of the first field effect transistor 1a by controlling the drain 03a of the first field effect transistor 1a, and determine the state of the memory cell 201 based on the level of the current. Can.

Correspondingly, referring to FIG. 36 , an embodiment of the present application also provides an electronic device, which may include a circuit board 2 and a field effect transistor 1 connected to the circuit board 2 . The problem-solving principle of this electronic device is similar to that of the aforementioned field-effect transistor. Therefore, the implementation of this electronic device can refer to the implementation of the aforementioned field-effect transistor, and repeated details will not be repeated.

Correspondingly, embodiments of the present application also provide an electronic device. Referring to FIG. 37 , the electronic device includes a processor 200 and a memory 100 coupled to the processor. The memory 100 can be any memory provided in the above embodiments of the present application. Specifically, the processor 200 can call the software program stored in the memory 100 to execute the corresponding method and realize the corresponding function of the electronic device.

Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. In this way, if these modifications and variations of the present application fall within the scope of the claims of the present application and equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

A field effect transistor, characterized in that it includes: a stacked structure, a channel layer, a gate electrode and a gate oxide layer; wherein:

The laminated structure includes a source electrode, a first isolation dielectric layer and a drain electrode that are stacked in sequence, and the laminated structure has a through groove, and the through groove penetrates from the upper surface of the drain electrode to the source electrode. ;

The channel layer covers the sidewalls and bottom of the through groove;

The gate oxide layer covers the sidewalls and bottom of the channel layer;

The gate electrode covers the sidewalls of the gate oxide layer.
The field effect transistor of claim 1, wherein the gate electrode fills a region defined by the gate oxide layer.
The field effect transistor according to claim 1, characterized in that two gate electrodes spaced apart are provided in the through groove.
The field effect transistor according to any one of claims 1 to 3, wherein the channel layer and the gate oxide layer also extend above the stacked structure.
The field effect transistor of claim 4, wherein the gate also extends above the stacked structure.
The field effect transistor of claim 4 or 5, wherein the stacked structure further includes a second isolation dielectric layer located between the drain electrode and the first isolation dielectric layer, and a second isolation dielectric layer located between the drain electrode and the first isolation dielectric layer. a back gate between the second isolation dielectric layer and the first isolation dielectric layer;

The field effect transistor further includes a third isolation dielectric layer located between the via sidewall and the channel layer.
The field effect transistor according to any one of claims 1 to 6, wherein the channel layer includes an N-type channel region and a P-type channel region, and the N-type channel region and the P-type Channel regions are located on both sides of the gate electrode.
A memory, characterized in that it includes a memory cell array and a gate array corresponding to the memory cell array, and the gate array includes a plurality of field effects according to any one of claims 1 to 7. transistor.
A memory, characterized in that it includes a memory cell array, and the memory cells in the memory cell array include the field effect transistor according to any one of claims 1-7.
The memory of claim 9, wherein each of the memory cells includes two field effect transistors, and the two field effect transistors are a first field effect transistor and a first field effect transistor located next to the first field effect transistor. a second field effect transistor on the first field effect transistor, and the gate electrode of the first field effect transistor is electrically connected to the source electrode of the second field effect transistor.
An electronic device, characterized by comprising a processor and a memory according to any one of claims 8-10 coupled with the processor.
An electronic device, characterized by comprising a circuit board and a field effect transistor according to any one of claims 1 to 7 connected to the circuit board.