WO2024066560A1

WO2024066560A1 - Storage array, memory and electronic device

Info

Publication number: WO2024066560A1
Application number: PCT/CN2023/103329
Authority: WO
Inventors: 孙莹; 黄凯亮; 景蔚亮; 王正波; 廖恒
Original assignee: 华为技术有限公司
Priority date: 2022-09-27
Filing date: 2023-06-28
Publication date: 2024-04-04
Also published as: CN117835693A

Abstract

The embodiments of the present application provide a storage array, a memory and an electronic device, which relate to the technical field of memories, and can reduce the process complexity and cost of preparing a memory. The storage array comprises a plurality of storage layers formed on a substrate, wherein the plurality of storage layers are stacked in a direction perpendicular to the substrate; each storage layer comprises at least one storage unit; the storage unit comprises a first transistor and a second transistor of an annular structure; the first transistor and the second transistor are arranged in the direction perpendicular to the substrate; a first electrode and a second electrode of each transistor are both distributed in the direction perpendicular to the substrate; and a channel layer of the first transistor and a channel layer of the second transistor are of an annular structure and are perpendicular to the substrate.

Description

Storage array, memory and electronic device

This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on September 27, 2022, with application number 202211182921.5 and application name “A storage array, memory and electronic device”, the entire contents of which are incorporated by reference in this application.

Technical Field

The present application relates to the field of storage technology, and in particular to a storage array, a memory including the storage array, a method for forming the storage array, and an electronic device including the memory.

Background technique

The storage unit of traditional dynamic random access memory (DRAM) consists of a transistor and a capacitor, which is called a 1 transistor 1 capacitor (1T1C) structure. With the continuous development of integrated circuits, the size of transistors continues to shrink, which brings about the inevitable short channel effect, such as increased leakage current and reduced mobility. For this reason, researchers have proposed a 2 transistor 1 capacitor (2T1C) structure memory, which can improve the problems caused by the short channel effect and achieve nanosecond read and write speeds and millisecond storage time.

The 2T0C structure memory based on planar devices requires multi-layer wiring, has a complex manufacturing process, low area utilization, and is difficult to achieve a high integration density storage array. Although the storage density can be increased by continuously stacking vertically, the number of masks required, the manufacturing cost, and the cycle will double for each additional layer of devices, and as the number of stacked layers increases, the alignment accuracy requirements for lithography will also increase.

Summary of the invention

Embodiments of the present application provide a memory array, a memory including the memory array, a method for forming the memory array, and an electronic device including the memory, so as to reduce the process difficulty and cost of the memory manufacturing process.

To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

In a first aspect, an embodiment of the present application provides a memory array, which can be used in a dynamic random access memory (DRAM). The memory array includes a substrate and a plurality of memory layers formed on the substrate, wherein the plurality of memory layers are stacked in a direction perpendicular to the substrate to increase the storage density; each memory layer includes at least one memory cell, wherein the memory cell includes a first transistor and a second transistor arranged in a direction perpendicular to the substrate, wherein the first transistor and the second transistor both include a gate, a first pole, a second pole and a channel layer, and the gate, the first pole, the second pole and the channel layer of the first transistor and the second transistor are all annular and perpendicular to the substrate.

The first electrode and the second electrode of the first transistor are distributed in a direction perpendicular to the substrate, and the channel layer of the first transistor surrounds the gate of the first transistor and connects the first electrode and the second electrode of the first transistor distributed in a direction perpendicular to the substrate; the channel layer of the second transistor surrounds the gate of the second transistor and connects the first electrode and the second electrode of the second transistor distributed in a direction perpendicular to the substrate; the gate of the second transistor is away from the surface of the substrate and contacts the second electrode of the first transistor, and can serve as a storage node to store data and information.

In the memory array provided by the embodiment of the present application, each memory cell includes a first transistor and a second transistor, wherein the first and second electrodes of the first and second transistors are distributed in a direction perpendicular to the substrate and are in a ring shape, so that the first and second electrodes can be stacked in a direction perpendicular to the substrate and then the ring-shaped first and second electrodes can be formed by opening a hole, without using a mask to separately prepare the first and second electrodes, thus reducing the number of masks required to prepare each transistor, and in addition, the channel layer and the gate of each transistor are also in a ring shape and are perpendicular to the substrate, the channel layer is arranged around the gate to connect the first and second electrodes distributed in a direction perpendicular to the substrate, and can be formed by opening the inner wall of the hole The channel layer and the gate are formed in sequence by growth or deposition, and there is no need to use a mask for etching. Instead, the area size of each electrode and the channel layer of each transistor can be adjusted by adjusting the size of the opening. Since the transistor with a horizontal channel structure requires multiple masks to prepare the first electrode and the second electrode, the gate and the channel layer in a direction parallel to the substrate, the number of masks required when multiple storage layers are stacked to form a storage array will increase exponentially, and the cost will also be greater. The storage array provided in the embodiment of the present application can reduce the number of masks required in the preparation process of each storage unit, simplify the preparation process, and reduce costs. When preparing a storage array including multiple storage layers, the difficulty and cost of the preparation process can also be reduced.

In a possible implementation, the gate of the first transistor is located on the side of the second electrode away from the substrate; the first electrode of the first transistor is arranged around the gate. The first electrode and the second electrode distributed in a direction perpendicular to the substrate are annular structures, so that the annular first electrode and the second electrode can be formed by stacking the materials of the first electrode and the second electrode in a direction perpendicular to the substrate and then etching the opening, without the need for additional The photomask preparation can reduce the number of photomasks required, and reduce the preparation difficulty and cost.

In one possible implementation, the channel layer of the first transistor is in ohmic contact with the first electrode and the second electrode of the first transistor; the channel layer of the first transistor includes a first part, a second part and a third part; the first part is located between the first electrode of the first transistor and the gate of the first transistor; the third part is located between the second electrode of the first transistor and the gate of the first transistor; and the second part connects the first part and the third part.

In one possible implementation, the gate of the first transistor includes a first gate portion and a second gate portion that are connected, the extension direction of the first gate portion is parallel to the substrate, and the extension direction of the second gate portion is perpendicular to the substrate; the first electrode of the first transistor is located on a side of the first gate portion away from the substrate, the gate of the first transistor includes a first gate portion whose extension direction is parallel to the substrate, and the channel layer is arranged around the gate, so the channel layer will form a concave structure surrounding the outside of the gate, the longer the extension length of the first gate portion of the gate, the deeper the depth of the concave structure formed by the channel layer, and the larger the effective width of the channel layer, so that the on current of the first transistor is larger, which can improve the read and write speed of the memory.

In one possible implementation, the first transistor includes a gate oxide dielectric layer, which is located between the channel layer of the first transistor and the gate of the first transistor. The gate oxide dielectric layer of the first transistor separates the channel layer of the first transistor from the gate of the first transistor. The gate and the channel layer are both annular in shape, so the gate oxide dielectric layer arranged between the gate and the channel layer is also annular in structure, and the axis of the ring is perpendicular to the substrate. Therefore, the gate oxide dielectric layer can also be formed by growing and depositing on the side wall of the opening, thereby reducing the number of masks required and reducing the difficulty and cost of preparation.

In one possible implementation, the first transistor includes a conductive film layer, which is arranged between the channel layer and the first electrode of the first transistor and the second electrode of the first transistor, so as to improve the ohmic contact between the channel layer and the first electrode and the second electrode and increase the on current of the transistor.

In one possible implementation, the gate, the first pole and the second pole of the second transistor are annular, and the axis surrounded is perpendicular to the substrate; the first pole and the second pole of the second transistor surround the gate of the second transistor, wherein the first pole of the second transistor is located on a side away from the substrate, and the second pole of the second transistor is located on a side close to the substrate. The structure of the second transistor is similar to that of the first transistor, and is also a transistor of a vertical channel structure in which the first pole and the second pole are distributed in a direction perpendicular to the substrate, and the first pole and the second pole are arranged around the gate. This multi-layer annular structure along the direction perpendicular to the substrate requires fewer masks during the preparation process and has lower cost. In addition, the structure of the second transistor is similar to that of the first transistor, and the overall structure is annular multi-layer structure. The first transistor and the second transistor can be prepared at the same time during the preparation process without having to prepare one first and then the other, which can reduce the complexity of the preparation process.

In a possible implementation, the gate, the first pole and the second pole of the second transistor are annular, and the axis around them is perpendicular to the substrate; the gate of the second transistor is located on the side of the second pole of the second transistor away from the substrate; the first pole of the second transistor is arranged around the gate of the second transistor. The second transistor has the same structure as the first transistor, and the first transistor and the second transistor can be prepared at the same time during the preparation process, which can reduce the complexity of the preparation process.

In one possible implementation, the channel layer of the second transistor includes a fourth part, a fifth part, and a sixth part connected in sequence; wherein the fourth part of the channel layer of the second transistor is located between the first electrode of the second transistor and the gate of the second transistor, and the channel layer is arranged around the gate, so the channel layer, the gate and other structures can be formed by sequentially growing and depositing on the inner wall of the opening.

In one possible implementation, the gate of the second transistor includes a third gate portion and a fourth gate portion that are connected; the extension direction of the third gate portion is parallel to the substrate, and the extension direction of the fourth gate portion is perpendicular to the substrate; the first electrode of the second transistor is located on the side of the third gate portion away from the substrate; the second electrode of the second transistor is located on the side of the third gate portion facing the substrate, so that the third gate portion of the gate separates the first electrode from the second electrode of the second transistor in a direction perpendicular to the substrate, and the channel layer of the second transistor is arranged around the gate, so that the channel layer will surround the third gate portion to form a concave structure, the longer the extension length of the third gate portion, the deeper the depth of the concave structure, and the larger the effective width of the channel layer, so that the on current of the second transistor is larger, which can improve the reading and writing speed of the memory.

In one possible implementation, the second transistor includes a gate oxide dielectric layer, and the channel layer of the second transistor, the gate oxide dielectric layer of the second transistor and the gate of the second transistor are arranged in a direction parallel to the substrate; the gate oxide dielectric layer of the second transistor separates the channel layer of the second transistor from the gate of the second transistor.

In a possible implementation, the second transistor includes a conductive film layer, and the conductive film layer is disposed between a channel layer of the second transistor and a first electrode of the second transistor and a second electrode of the second transistor, so as to improve ohmic contact.

In one possible implementation, each storage layer also includes a write word line, a write bit line, a read word line and a read bit line; the gate of the first transistor is connected to the write word line, the first electrode of the first transistor is connected to the write bit line, the second electrode of the first transistor is connected to the gate of the second transistor, the first electrode of the second transistor is connected to the read word line, and the second electrode of the second transistor is connected to the read bit line.

In one possible implementation, the write word line is located on a side of the first transistor away from the substrate, and the gate of the first transistor is away from the surface of the substrate and contacts the write word line; the film layer position of the write bit line in a direction perpendicular to the substrate is located in the same layer as the first electrode of the first transistor; the film layer position of the read word line in a direction perpendicular to the substrate is located in the same layer as the first electrode of the second transistor; the film layer position of the read bit line in a direction perpendicular to the substrate is located in the same layer as the second electrode of the second transistor.

In one possible implementation, the storage layer includes multiple storage cells; the write word line and the read word line both extend in a first direction parallel to the substrate; the write bit line and the read bit line both extend in a second direction parallel to the substrate; the write word line is electrically connected to the gates of the first transistors of the multiple storage cells located in the first direction; the write bit line is electrically connected to the first electrodes of the first transistors of the multiple storage cells located in the second direction; the read word line is electrically connected to the first electrodes of the second transistors of the multiple storage cells located in the first direction; and the read bit line is electrically connected to the second electrodes of the second transistors of the multiple storage cells located in the second direction.

In a possible implementation, the write bit line is integrally arranged with the first electrode of the first transistor; the read word line is integrally arranged with the first electrode of the second transistor; and the read bit line is integrally arranged with the second electrode of the second transistor.

In the second aspect, the present application also provides a memory, which includes a controller and a memory array in any of the above implementations, the controller is electrically connected to the memory array, and the controller is used to control the reading and writing of the memory array. In the memory provided by the present application, since the memory array in the above implementation is included, in the memory array, the first transistor and the second transistor are arranged in a direction perpendicular to the substrate, so that the memory cells of this structure can be stacked in a direction perpendicular to the substrate to increase the storage density and improve the storage capacity, and the vertical structure of the memory cells can reduce the number of masks required and reduce the preparation cost.

In a third aspect, an embodiment of the present application also provides a method for manufacturing a memory, the method comprising: forming a second pole of a second transistor, a first pole of a second transistor, a second pole of a first transistor and a first pole of a first transistor in a direction perpendicular to a substrate, the second pole of the second transistor, the first pole of the second transistor, the second pole of the first transistor and the first pole of the first transistor are all annular and perpendicular to the substrate; forming a channel layer of the second transistor and a channel layer of the first transistor, the channel layer of the first transistor and the channel layer of the second transistor are all annular and perpendicular to the substrate, the channel layer of the first transistor connects the first pole and the second pole of the first transistor; the channel layer of the second transistor connects the first pole and the second pole of the second transistor; forming a gate of the second transistor and a gate of the first transistor, the channel layer of the first transistor surrounds the gate of the first transistor; the channel layer of the second transistor surrounds the gate of the second transistor, and the gate of the second transistor is away from the surface of the substrate and contacts the second pole of the first transistor.

In one possible implementation, forming the channel layer of the first transistor includes: forming a first part, a second part and a third part of the channel layer of the first transistor, the first part contacts the first electrode of the first transistor; the third part contacts the second electrode of the first transistor; and the third part connects the first part and the third part.

In one possible implementation, forming the gate of the first transistor includes: forming a first gate portion of the gate, wherein the extension direction of the first gate portion is parallel to the substrate; and forming a second gate portion connected to the first gate portion, wherein the extension direction of the second gate portion is perpendicular to the substrate.

In one possible implementation, forming the channel layer of the second transistor includes: forming a fourth part, a fifth part and a sixth part of the channel layer of the second transistor, the fourth part contacts the first electrode of the second transistor; the sixth part contacts the second electrode of the first transistor; and the fifth part connects the fourth part and the sixth part.

In one possible implementation, forming the gate of the second transistor includes: forming a third gate portion of the gate, wherein the extension direction of the third gate portion is parallel to the substrate; and forming a fourth gate portion connected to the third gate portion, wherein the extension direction of the fourth gate portion is perpendicular to the substrate.

In one possible implementation, the method also includes: forming a write word line, a write bit line, a read word line, and a read bit line; connecting the gate of the first transistor to the write word line, connecting the first electrode of the first transistor to the write bit line, connecting the second electrode of the first transistor to the gate of the second transistor, connecting the first electrode of the second transistor to the read word line, and connecting the second electrode of the second transistor to the read bit line.

In one possible implementation, forming a write word line, a write bit line, a read word line, and a read bit line includes: forming a write word line on a side of a first transistor away from a substrate, and a gate of the first transistor is away from a surface of the substrate and in contact with the write word line; forming a write bit line in a film layer in a direction perpendicular to the substrate and in the same layer as a first electrode of the first transistor; forming a read word line in a film layer in a direction perpendicular to the substrate and in the same layer as a first electrode of the second transistor; and forming a read bit line in a film layer in a direction perpendicular to the substrate and in the same layer as a second electrode of the second transistor.

In one possible implementation, forming a write word line, a write bit line, a read word line and a read bit line further includes: the write bit line is integrally arranged with a first electrode of a first transistor; the read word line is integrally arranged with a first electrode of a second transistor; and the read bit line is integrally arranged with a second electrode of a second transistor.

In a fourth aspect, an embodiment of the present application further provides an electronic device, comprising: a processor and the memory provided in the aforementioned second aspect, wherein the processor and the memory are electrically connected.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of an electronic device provided in an embodiment of the present application;

FIG2 is a schematic diagram of a memory provided in an embodiment of the present application;

FIG3 is a schematic diagram of a three-dimensional structure of a memory provided in an embodiment of the present application;

FIG4 is a simplified circuit diagram of a memory provided in an embodiment of the present application;

FIG5 is a circuit diagram of a storage unit in a memory provided by an embodiment of the present application;

FIG6 is a circuit diagram of a storage unit in a memory provided in an embodiment of the present application;

FIG7 is a circuit diagram of a memory array formed by a plurality of memory cells in a memory provided by an embodiment of the present application;

FIG8 is a schematic diagram of a process structure of a multi-layer storage unit in a memory provided by an embodiment of the present application;

FIG9 is a diagram showing the positional relationship between a storage unit and a substrate in a memory provided by an embodiment of the present application;

FIG10 is a cross-sectional view of a process structure of a memory cell in a memory provided by an embodiment of the present application;

FIG11 is a cross-sectional view of a process structure of another memory cell in a memory provided by an embodiment of the present application;

FIG12a is a cross-sectional view of a process structure of another memory cell in a memory provided by an embodiment of the present application;

FIG12b is a cross-sectional view of a process structure of another memory cell in a memory provided by an embodiment of the present application;

FIG13 is a cross-sectional view of a process structure of another memory cell in a memory provided by an embodiment of the present application;

FIG14 is a cross-sectional view of a process structure of two memory cells stacked according to an embodiment of the present application;

FIG15 is a schematic diagram of the structure of a storage array including a storage layer provided in an embodiment of the present application;

FIG16 is a flowchart of a memory manufacturing method provided in an embodiment of the present application;

17a to 17r are cross-sectional views of corresponding process structures after each step in a memory manufacturing method provided in an embodiment of the present application is completed.

Detailed ways

The embodiment of the present application provides an electronic device. FIG1 is a circuit block diagram of an electronic device 200 provided in the embodiment of the present application. The electronic device 200 may be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc.

As shown in FIG. 1 , the electronic device 200 may include a bus 205 and a system on chip (SOC) 210 connected to the bus 205. The SOC 210 may be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the SOC 210 may include an application processor (AP) 211 for processing applications, a graphics processing unit (GPU) 212 for processing image data, and a first random access memory (RAM) 213 for caching high-speed data. The first RAM 213 may be a static random access memory (SRAM) or an embedded flash (EFlash), etc. The AP 211, GPU 212, and the first RAM 213 may be integrated into a die, or may be separately set in a plurality of dies.

As shown in FIG. 1 , the electronic device 200 may further include a second RAM 220 connected to the SOC 210 via the bus 205. The second RAM 220 may be a dynamic random access memory (DRAM). The second RAM 220 may be used to store volatile data, such as temporary data generated by the SOC 210. The storage capacity of the second RAM 220 is generally greater than that of the first RAM 213, but the reading speed is generally slower than that of the first RAM 213.

In addition, the electronic device 200 may also include a communication chip 230 and a power management chip 240 connected to the SOC 210 through the bus 205. The communication chip 230 can be used for processing the protocol stack, or amplifying and filtering analog radio frequency signals, or realizing the above functions at the same time. The power management chip 240 can be used to power other chips. In one embodiment, the SOC 210 and the second RAM 220 can be packaged in a packaging structure, such as using 2.5D (dimension) or 3D packaging, to obtain a faster data transmission rate between chips.

FIG. 2 is a circuit block diagram of a memory 300 that can be used in an electronic device according to an embodiment of the present application. In the implementation, the memory 300 may be the first RAM 213 as shown in FIG. 1 , or may be the second RAM 220. The application scenario of the memory 300 of the present application is not limited. In a possible implementation, the memory 300 may also be a RAM disposed outside the SOC 210. The present application does not limit the position of the memory 300 in the electronic device and the positional relationship with the SOC 210.

As shown in FIG2 , the memory 300 includes a memory array 31 and a controller 32 for accessing the memory array 31, wherein the controller 32 is used to control the read and write operations of the memory array 31. The memory array 31 here can be a layer of memory array, or it can be a first layer of memory array and a second layer of memory array stacked along the Z direction perpendicular to the substrate as shown in FIG3 , or, in some other optional embodiments, it can include more layers of memory arrays. When two or more layers of memory arrays are included, such a memory can be called a three-dimensional integrated memory structure to increase the storage capacity.

In the memory structure shown in FIG3, the control circuit is integrated on the substrate through the front end of line (FEOL) process, and the interconnection line and the memory are integrated on the control circuit through the back end of line (BEOL) process. The control circuit here can generate control signals, which can be read and write control signals for controlling the read and write operations of data in the memory.

In one embodiment, the memory array 31 in the memory may include a plurality of memory cells 400 arranged in an array as shown in FIG. 4 , wherein each memory cell 400 may be used to store 1 bit (bit) or multiple bits of data. The memory array 31 may also include signal lines such as word lines (WL) and bit lines (BL). Each memory cell 400 is electrically connected to the corresponding word line WL and bit line BL. Different memory cells 400 may be electrically connected via WL and BL. One or more of the above WL and BL are used to select the memory cell 400 to be read or written in the memory array by receiving the control level output by the control circuit, thereby realizing the data read and write operation.

The controller 32 in the memory may include one or more circuit structures of the decoder 320 , the driver 330 , the timing controller 340 , the buffer 350 , or the input/output driver 360 shown in FIG. 4 .

In the memory 300 structure shown in FIG4 , the decoder 320 is used to decode according to the received address to determine the storage unit 400 to be accessed. The driver 330 is used to control the level of the signal line according to the decoding result generated by the decoder 320, so as to achieve access to the specified storage unit 400. The buffer 350 is used to cache the read data, for example, first-in first-out (FIFO) can be used for caching. The timing controller 340 is used to control the timing of the buffer 350, and control the driver 330 to drive the signal line in the storage array 310. The input and output driver 360 is used to drive the transmission signal, such as driving the received data signal and driving the data signal to be sent, so that the data signal can be transmitted over a long distance.

The storage array 310 , decoder 320 , driver 330 , timing controller 340 , buffer 350 and input/output driver 360 may be integrated into one chip or may be integrated into multiple chips.

The memory 300 involved in the embodiment of the present application may be a dynamic random access memory (DRAM). A conventional DRAM memory cell is composed of a transistor and a capacitor, as shown in FIG5 , which shows a circuit diagram of a memory cell in a memory provided by an embodiment of the present application, wherein a first end of a transistor T of the memory cell is connected to a bit line (BL), and a second end thereof is connected to a first end of a capacitor C. The gate of the transistor T is connected to a word line (WL), and a second end of the capacitor C may be connected to a voltage terminal, which may be connected to a voltage (e.g., a ground voltage or a half-power supply voltage) of a specific level (e.g., a desired voltage level) through a source line (SL).

The storage unit of the 1T1C structure uses the amount of charge stored in the capacitor to store "1" or 0. However, with the continuous development of integrated circuits, the size of transistors has been continuously miniaturized, which has also brought about unavoidable short channel effects, such as increased leakage current of transistors and reduced mobility. When the transistor is in the off state, there is a certain leakage between the source and the drain. The higher the technology node, such as 10nm, 7nm, 5nm and higher technology nodes, the smaller the size of the transistor, and the more obvious the short channel effect. In addition, the projected area of the capacitor is getting smaller and smaller with the miniaturization of the transistor. In order to ensure the stable operation of the 1T1C memory, the capacitor needs to be made higher. The continuous expansion of the capacitor height and the continuous miniaturization of the projected area have also posed great challenges to the etching process.

In order to improve the stability of DRAM, an embodiment of the present application proposes a memory with a 2T0C structure, as shown in Figure 6. Figure 6 shows a circuit diagram of a memory cell 400 in the memory 300 given in an embodiment of the present application. The memory cell 400 belongs to the gain-cell memory cell structure of 2T0C, that is, a memory cell 400 includes two transistors, for example, a first transistor T1 and a second transistor T2.

In addition, the memory 300 further includes four control lines, namely a write word line (WWL), a write bit line (WBL), a read word line (RWL), and a read bit line (RBL).

The gate of the first transistor T1 is connected to WWL, the first electrode of the first transistor T1 is connected to WBL, the second electrode of the first transistor T1 is connected to the gate of the second transistor T2, the connection point between the second electrode of the first transistor T1 and the gate of the second transistor T2 is used as a storage node (save node, SN), the first electrode of the second transistor T2 is connected to RBL, and the second electrode of the second transistor T2 is connected to RWL.

In the memory cell shown in FIG6 , the write bit line WBL may also be referred to as a first control line for loading a signal to the first electrode of the first transistor T1, the read bit line RBL may also be referred to as a second control line for loading a signal to the first electrode of the second transistor T2, the write word line WWL may also be referred to as a third control line for loading a signal to the gate of the first transistor T1, and the read word line RWL may also be referred to as a fourth control line for loading a signal to the second electrode of the second transistor T2.

In the embodiment of the present application, a transistor, such as the first transistor T1 or the second transistor T2 mentioned above, may be an NMOS (N-channel metal oxide semiconductor) tube, or a PMOS (P-channel metal oxide semiconductor) tube. One of the drain or source of the transistor is called the first electrode, and the corresponding other electrode is called the second electrode, and the control end of the transistor is the gate. The drain and source of the transistor can be determined according to the direction of current flow. For example, taking the first transistor T1 shown in Figure 6 as an example, when the current flows from left to right, the first electrode at the left end is the drain, and the second electrode at the right end is the source; on the contrary, when the current flows from right to left, the second electrode at the right end is the drain, and the first electrode at the left end is the source.

The storage array 31 can be obtained by arranging the storage units 400 shown in FIG. 6 in an array, wherein the circuit structure of each storage unit 400 is the same. For example, in the storage array 31 shown in FIG. 7, a 4×4 storage array arranged along the perpendicular X and Y directions is exemplified. In some optional embodiments, when the storage array shown in FIG. 7 is stacked along the Z direction shown in FIG. 3, three-dimensional stacking can be achieved, further improving the storage capacity to adapt to a processor with high operating efficiency.

The write operation process and the read operation process of the 2T0C memory cell 400 shown in FIG. 6 are described below respectively.

Write operation process: During the write operation, the voltage of the read bit line RBL is 0, and the second transistor T2 does not work; a first write word line control signal is provided to the write word line WWL, and the first write word line control signal controls the first transistor T1 to turn on. When writing the first logic information, such as "0", the first write bit line control signal is provided to the write bit line WBL (or the read word line RWL), and the first write bit line control signal is written into SN through the first transistor T1. Therefore, the first transistor T1 is also called a write transistor (write transistor, WTR), and the second transistor T2 is also called a read transistor (read transistor, RTR). When writing the second logic information, such as "1", the second write bit line control signal is provided to the write bit line WBL (or the read word line RWL), and the second write bit line control signal is written through the first transistor T1.

It should be understood that after the write operation is completed, the second transistor T2 does not work; a second write word line control signal is provided to the write word line WWL, and the second write word line control signal controls the first transistor T1 to be disconnected. At this time, the potential stored in the node is not affected by the outside world.

Read operation process: provide the second write word line control signal to the write word line WWL, the second write word line control signal controls the first transistor T1 to be disconnected; provide the read word line control signal to the read word line RWL (or write bit line WBL), and judge the logic information stored in the storage unit according to the level of the current on the read bit line RBL. When the node stores the first write bit line control signal, since the first write bit line control signal can control the second transistor T2 to be turned on, when the read word line RWL (or write bit line WBL) provides the read word line control signal, the read word line RWL (or write bit line WBL) charges the read bit line RBL through the second transistor T2, and the voltage on the read bit line RBL increases. In this way, when it is detected that the current on the read bit line RBL is large, it can be read that the storage unit stores the logic information "0". When the node stores the second write bit line control signal, since the second write bit line control signal can control the second transistor T2 to turn off, when the read word line RWL (or write bit line WBL) provides the read word line control signal, the read word line RWL (or write bit line WBL) will not charge the read bit line RBL through the second transistor T2, and the read bit line RBL maintains a 0V voltage. In this way, when it is detected that the current on the read bit line RBL is small, it can be read that the storage cell stores the logic information "1".

In order to improve the retention time of the 2T0C structure memory, the first transistor T1 and the second transistor T2 can use a thin film transistor (TFT) structure. TFT refers to a transistor formed by depositing or growing multiple film layers, and the conductive channel selects an amorphous metal oxide with extremely low leakage or other wide bandgap materials. Since the leakage of TFT is much lower than that of silicon transistors, the current on the RTR gate is greatly reduced through the leakage of WTR, which greatly improves the storage time of the memory. In the "read" operation, you only need to read the current of RTR, and then judge the storage state as "1" or "0" according to the level of the current.

The 2TOC structure memory based on planar devices can improve the storage efficiency by stacking multiple memory cell layers in the direction perpendicular to the substrate. Storage density, for example, FIG8 a shows a schematic diagram of stacking three layers of memory cells (or memory arrays), and FIG8 b shows a cross-sectional schematic diagram along the AA' direction in FIG8 a. The transistors T1 and T2 of each memory cell are arranged in the XY plane, the first electrode and the second electrode of the first transistor T1 are arranged in the XY plane, and the first electrode and the second electrode of the second transistor T2 are also arranged in the XY plane. Since the positions of the first electrode and the second electrode of the first transistor T1 and the second transistor T2 are different, a mask is required to be used when forming the first electrode and the second electrode of the first transistor T1, and a mask is required to be used when forming the first electrode and the second electrode of the second transistor T2, and four masks are required to form the first transistor T1 and the second transistor T2.

In addition, although the storage density can be increased by continuously stacking in the direction perpendicular to the XY plane (i.e., in the Z direction) as shown in FIG8 b, since the two transistors of each storage unit are in the XY plane, and the first electrode and the second electrode of each transistor are distributed in the XY plane, a large number of masks are required when preparing each layer of the storage array, and with each additional layer of stacked storage array, the number of masks required and the preparation cost will increase exponentially, and the production cycle will also double. In addition, as the number of stacked layers increases, the requirements for the alignment accuracy of the lithography will become increasingly greater, and there are problems such as complex preparation process and high risk.

The 2T0C structure memory based on planar devices requires multi-layer wiring, has a complex manufacturing process, and has low area utilization, so it is difficult to achieve a high integration density storage array.

In the memory cell 400 such as that shown in FIG. 6 and FIG. 7 above, the embodiments of the present application provide some memory cell process structures that can improve the storage density, as described below.

Figure 9 simply shows the layout of the first transistor T1 and the second transistor T2 in the memory cell 400. As shown in Figure 9, the first transistor T1 and the second transistor T2 in any memory cell 400 given in the embodiment of the present application are stacked in a direction perpendicular to the substrate 100, rather than being arranged in a parallel direction perpendicular to the substrate 100.

In addition, the first transistor T1 and the second transistor T2 of the memory cell 400 of the present application are both thin film transistor (TFT) structures. Combined with the layout shown in FIG. 9 , the first transistor T1 and the second transistor T2 can form a three-dimensional integration on the substrate 100 .

Referring to FIG. 10 , FIG. 10 shows a cross-sectional view of a possible process structure of a memory cell 400 provided in an embodiment of the present application, wherein the first transistor T1 and the second transistor T2 are arranged in a direction perpendicular to the substrate 100, the first transistor T1 includes a gate 411, a first electrode 412, a second electrode 413, a channel layer 414 and a gate oxide dielectric layer 415, and the second transistor T2 includes a gate 421, a first electrode 422, a second electrode 423, a channel layer 424 and a gate oxide dielectric layer 425. The gate, first electrode, second electrode, channel layer and gate oxide dielectric layer of the first transistor T1 and the second transistor T2 are all annular structures.

The first electrode 412 and the second electrode 413 of the first transistor T1 are sequentially arranged along a direction perpendicular to the substrate 100, and the first electrode 422 and the second electrode 423 of the second transistor T2 are arranged along a direction perpendicular to the substrate 100. In the embodiment of the present application, a pole of the first transistor T1 or the second transistor T2 close to the substrate is referred to as the second pole of the transistor, and a pole away from the substrate is referred to as the first pole of the transistor.

The gate 411, gate oxide dielectric layer 415, channel layer 414, etc. of the first transistor T1 are sequentially stacked in a direction parallel to the substrate, wherein the gate oxide dielectric layer 415 surrounds the gate 411, the channel layer 414 surrounds the gate oxide dielectric layer 415, and the gate oxide dielectric layer 415 is formed of an insulating material, so that the channel layer 414 can be separated from the gate 411. The gate 421, gate oxide dielectric layer 425, channel layer 424, etc. of the second transistor T2 are sequentially stacked in a direction parallel to the substrate, wherein the gate oxide dielectric layer 425 surrounds the gate 421, the channel layer 424 surrounds the gate oxide dielectric layer 425, and the gate oxide dielectric layer 425 is formed of an insulating material, so that the channel layer 424 can be separated from the gate 421.

The first transistor T1 and the second transistor T2 are sequentially arranged in a direction perpendicular to the substrate 100, and the first electrode and the second electrode of the first transistor T1 and the second transistor T2 are both annular and arranged in a direction perpendicular to the substrate 100. Therefore, the two electrodes can be formed by stacking the first electrode and the second electrode materials and then opening holes. There is no need to use a mask to prepare the first electrode 412 and the second electrode 413 of the first transistor T1 and the first electrode 422 and the second electrode 423 of the second transistor T2, respectively, which can reduce the number of masks required to prepare each transistor. In addition, the shape of the channel layer and the gate of each transistor is also annular, and The gate is perpendicular to the substrate, and the channel layer is arranged around the gate to connect the first electrode and the second electrode distributed in the direction perpendicular to the substrate. The channel layer and the gate can be formed in sequence by growing or depositing on the inner wall of the opening. There is no need to use a mask for etching, but the area size of each electrode and the channel layer of each transistor can be adjusted by adjusting the size of the opening. Since the transistor with a horizontal channel structure requires multiple masks to prepare the first electrode and the second electrode, the gate and the channel layer in a direction parallel to the substrate, the number of masks required when multiple storage layers are stacked to form a storage array will increase exponentially, and the cost will also be greater. The storage array provided by the embodiment of the present application can reduce The number of masks required in the preparation process of each storage unit is reduced, the preparation process is simplified, and the cost is reduced. When preparing a storage array including multiple storage layers, the difficulty and cost of the preparation process can also be reduced.

Please continue to refer to Figure 10. The gate 411, the first electrode 412, the second electrode 413, the channel layer 414 and the gate oxide dielectric layer 415 of the first transistor T1 are all annular structures. The axes surrounded by these annular structures are perpendicular to the substrate 100. The first electrode 412 and the second electrode 413 are arranged in a direction perpendicular to the substrate 100. The gate 411 of the first transistor T1 is located on the side of the second electrode 413 away from the substrate. The first electrode 412 surrounds the gate 411. The first electrode 412 and the second electrode 413 do not contact each other. The two are connected through the channel layer 414 surrounding the gate 411. The channel layer 414 is in ohmic contact with the first electrode 412 and the second electrode 413.

Exemplarily, the annular first pole 412 includes a first side M1 parallel to the substrate 100 and a second side M2 perpendicular to the substrate 100; the first side M1 faces the substrate 100 (or faces the second transistor T2), and the second side M2 faces the gate 411. The annular second pole 413 includes a third side M3 parallel to the substrate, the third side M3 is a side surface of the second pole 413 away from the substrate, and the third side M3 faces the gate 411 and the first pole 412.

The channel layer 414 is a channel for carriers in the transistor, also known as a semiconductor layer or a conductive channel layer. The channel layer 414 of the first transistor T1 is in ohmic contact with the first electrode 412 and the second electrode 413 of the first transistor T1. In the embodiment of the present application, the channel layer 414 includes a first part P1, a second part P2 and a third part P3; the first part P1 is located between the first electrode 412 of the first transistor T1 and the gate 411 of the first transistor T1; the third part P3 is located between the second electrode 413 of the first transistor T1 and the gate 411 of the first transistor T1; the second part P2 connects the first part P1 and the third part P3.

10 , the first portion P1 is located between the second side surface M2 of the first electrode 412 of the first transistor T1 and the gate 411 , and the third portion P3 is located between the third side surface M3 of the second electrode 413 of the first transistor T1 and the gate 411 .

When the gate 411 is powered on, there is a gate oxide dielectric layer 415 between the gate 411 and the channel layer 414. The electric field generated by the gate 411 acts on the channel layer 414 to form a conductive channel in the channel layer. Current can flow from the first pole 412 to the second pole 413 through the channel layer 414, or current can flow from the second pole 413 to the first pole 412 through the channel layer 414. The pole from which the current flows out is called the source, and the pole from which the current flows in is called the drain.

The second transistor T2 includes a gate 421 , a first electrode 422 , a second electrode 423 , a channel layer 424 and a gate oxide dielectric layer 425 . The gate 421 , the first electrode 422 , the second electrode 423 , the channel layer 424 and the gate oxide dielectric layer 425 are also annular structures, and the axis around each annular structure is perpendicular to the substrate 100 .

Among them, the surface of the gate electrode 421 of the second transistor T2 away from the substrate 100 is in contact with the second electrode 413 of the first transistor T1, the first electrode 422 and the second electrode 423 are distributed around the gate electrode 411, and the first electrode 422 and the second electrode 423 are distributed in a direction perpendicular to the substrate, the first electrode 422 is located on the side away from the substrate 100, and the second electrode 423 is located on the side close to the substrate 100. The first electrode 422 and the second electrode 423 do not contact each other, and are connected through a channel layer 424 arranged around the gate electrode 421. The channel layer 424 is in ohmic contact with both the first electrode 422 and the second electrode 423.

The channel layer 424 is a channel for carriers in the transistor, also referred to as a semiconductor layer or a conductive channel layer. The channel layer 424 of the second transistor T2 is in ohmic contact with the first electrode 422 and the second electrode 423 of the second transistor T2. In the embodiment of the present application, the channel layer 424 of the second transistor T2 includes a fourth portion P4, a fifth portion P5, and a sixth portion P6; the fourth portion P4 is located between the first electrode 422 of the second transistor T2 and the gate 421 of the second transistor T2; the sixth portion P6 is located between the second electrode 423 of the second transistor T2 and the gate 421 of the second transistor T2; and the fifth portion P5 connects the fourth portion P4 and the sixth portion P6.

The gate oxide dielectric layer 425 is disposed between the channel layer 424 and the gate 421. It can also be considered that the gate oxide dielectric layer 425 surrounds the gate 421, the channel layer 424 surrounds the gate oxide dielectric layer 425, and the first electrode 422 and the second electrode 423 surround the channel layer 424. In this way, the second transistor T2 can form a multi-layer ring structure.

It can be seen that the storage unit 400 provided in the embodiment of the present application includes a first transistor T1 and a second transistor T2, and the first transistor T1 and the second transistor T2 are distributed in a direction perpendicular to the substrate. For the first transistor T1 or the second transistor T2, the first electrode and the second electrode are distributed in a direction perpendicular to the substrate 100, so that there is no need to set a mask for multiple etchings to form the first electrode and the second electrode, and it is only necessary to stack the materials of the first electrode and the second electrode in the direction perpendicular to the substrate 100; the first electrode and the second electrode are distributed in a direction perpendicular to the substrate, so that the channel layer connecting the first electrode and the second electrode can also surround the vertical channel whose axis is perpendicular to the substrate, and the channel layer, the gate oxide dielectric layer and the gate are stacked in sequence, while the traditional transistor with a horizontal channel structure requires more masks to prepare the first electrode, the second electrode, the channel layer and the like structures arranged in a direction parallel to the substrate. In the embodiment of the present application, the first electrode and the second electrode can be formed by stacking electrode materials and then opening holes, and the channel layer, the gate oxide dielectric layer and the gate are formed by opening holes, growth, deposition and other processes. There is no need to use masks to prepare the first electrode and the second electrode respectively, which can reduce the number of masks required. Reduce the difficulty of alignment in the manufacturing process, thereby reducing costs.

In the above example, the structure of the second transistor T2 is different from that of the first transistor T1, and the main difference lies in the difference in the second electrodes of the two transistors. The second electrode 413 of the first transistor T1 is located on the side of the gate 411 close to the substrate 100, while the second electrode 423 of the second transistor T2 is arranged around the gate 421. In another embodiment of the present application, the structure of the second transistor T2 may be the same as that of the first transistor T1.

For example, see FIG11 . The second electrode 423 of the second transistor T2 is located on the side of the gate 421 close to the substrate 100, and the first electrode 422 is disposed around the gate 421. The first electrode 422 and the second electrode 423 are connected by a channel layer 424 surrounding the gate 421, and the channel layer 424 is in ohmic contact with the side of the first electrode 422 facing the gate 421 and the side of the second electrode 423 away from the substrate 100, and the gate oxide dielectric layer 425 is located between the gate 421 and the channel layer 424 to separate the gate 421 from the channel layer 424.

In the above example, it is mentioned that the short channel effect may be caused when the channel width of the transistor is small, but for the memory cell 400 provided in the embodiment of the present application, such a problem can be well overcome. In the memory cell provided in the embodiment of the present application, the first transistor T1 and the second transistor T2 are vertical channel structures, the first pole and the second pole are distributed in a direction perpendicular to the substrate, the channel layer connects the first pole and the second pole, and the larger the interval between the first pole and the second pole, the larger the width of the channel layer, so that the short channel effect can be avoided.

However, in some cases, due to size limitations, the distance between the first electrode and the second electrode of the first transistor T1 and the second transistor T2 cannot be made larger. In this case, an embodiment of the present application provides another implementation method that can increase the effective channel width, increase the on current of the transistor, and avoid the short channel effect.

Based on the storage unit shown in FIG. 10 , referring to FIG. 12 a , the gate 411 of the first transistor T1 includes a first gate portion G1 and a second gate portion G2 in contact, wherein an extension direction of the first gate portion G1 is parallel to the substrate 100, an extension direction of the second gate portion G2 is perpendicular to the substrate 100, and one end of the first gate portion G1 is connected to an end of the second gate portion G2 close to the substrate 100, such that a cross-sectional shape of the gate 411 of the first transistor T1 is L-shaped.

The first electrode 412 of the first transistor T1 is located at a side of the first gate portion G1 away from the substrate 100, and the second electrode 413 of the first transistor T1 is located at a side of the first gate portion G1 close to the substrate 100. It can be considered that the first gate portion G1 of the gate 411 of the first transistor T1 separates the first electrode 412 from the second electrode 413 of the first transistor T1 in a direction perpendicular to the substrate 100.

It can be seen that, since the size of the first transistor T1 cannot be too large, the length of the gate 411 in the direction perpendicular to the substrate 100 cannot be too long. In the memory cell 400 provided in the embodiment of the present application, the first gate portion G1 of the gate 411 of the first transistor T1 can also extend in a direction parallel to the substrate 100. Since the channel layer 414 is arranged around the gate 411, the channel layer 414 will form a concave structure parallel to the substrate 100. The longer the length of the first gate portion G1 of the gate 411 is extended, the deeper the concave structure is. Correspondingly, the greater the channel width of the channel layer 414 of the first transistor T1 is, the greater the on-current of the first transistor T1 is. On the contrary, if the extension length of the first gate portion G1 is shorter, the depth of the concave structure formed by the channel layer 414 is shallower, the channel width of the channel layer 414 is smaller, and the on-current of the first transistor T1 is smaller. Therefore, the effective channel width of the channel layer 414 can be adjusted by adjusting the extension length of the first gate portion G1, thereby improving the read and write performance of the memory.

Based on the concave structure formed by the channel layer 414 of the first transistor T1 , the gate oxide dielectric layer 415 of the first transistor T1 also forms a matching concave structure to achieve electrical isolation between the channel layer 414 of the first transistor T1 and the gate 411 of the first transistor T1 .

Similarly, the gate 421 of the second transistor T2 also includes a portion perpendicular to the substrate 100 and a portion parallel to the substrate 100, wherein the portion extending in a direction parallel to the substrate 100 is the third gate portion G3, and the portion extending in a direction perpendicular to the substrate 100 is the fourth gate portion G4. One end of the third gate portion G3 is connected to the fourth gate portion G4. The first electrode 422 of the second transistor T2 is located at an end of the third gate portion G3 away from the substrate, and the second electrode 423 of the second transistor T2 is located at an end of the third gate portion G3 close to the substrate. In the direction perpendicular to the substrate 100, the third gate portion G3 of the second transistor T2 separates the first electrode 422 from the second electrode 423 of the second transistor T2.

The channel layer 424 of the second transistor T2 surrounds the gate 421 , so the channel layer 424 of the second transistor T2 forms a concave structure at a portion where the third gate portion G3 of the gate 421 of the second transistor T2 extends.

The longer the length of the third gate portion G3 is extended, the greater the depth of the concave structure formed by the channel layer 424 is, so the width of the channel layer 424 is also larger, and the on-current of the second transistor T2 is larger; conversely, if the extension length of the third gate portion G3 is shorter, the depth of the concave structure formed by the channel layer 424 is smaller, so the width of the channel layer 424 is smaller, and the on-current of the second transistor T2 is smaller. Therefore, the channel current can be adjusted by adjusting the extension length of the third gate portion G3 of the gate 421 of the second transistor T2. The width of layer 424.

Exemplarily, the first electrode 422 of the second transistor T2 includes a fourth side M4 perpendicular to the substrate 100 and a fifth side M5 parallel to the substrate 100, wherein the fourth side M4 faces the gate 421, and the fifth side M5 faces the substrate 100. The second electrode 423 of the second transistor includes a sixth side M6 parallel to the substrate 100 and a seventh side M7 perpendicular to the substrate 100. The sixth side M6 is away from the substrate 100, and the seventh side M7 faces the gate 421 of the second transistor T2.

The channel layer 424 of the second transistor T2 includes four parts P4, a fifth part P5 and a sixth part P6. The fourth part P4 is located between the first electrode 422 and the gate 421 of the second transistor T2. In conjunction with FIG12a, the fourth part P4 is in contact with both the fourth side M4 and the fifth side M5 of the first electrode 422; the sixth part P6 is in contact with both the sixth side M6 and the seventh side M7 of the second electrode. The longer the extension length of the third gate part G3 of the gate 421 is, the deeper the depth of the concave structure formed by the channel layer 424 is, that is, the width of the channel layer 424 is large. On the contrary, if the extension length of the third gate part G3 of the gate 421 of the second transistor T2 is shorter, the depth of the concave structure formed by the channel layer 424 is shallower, the channel width of the channel layer 424 is smaller, and the on current of the second transistor T2 is smaller. Therefore, the effective channel width of the channel layer 424 can be adjusted by adjusting the extension length of the first gate part G1 of the gate 421 of the second transistor T2, thereby improving the read and write performance of the memory.

Based on the concave structure formed by the channel layer 424 of the second transistor T2 , the gate oxide dielectric layer 425 of the second transistor T2 also forms a matching concave structure to achieve electrical isolation between the channel layer 424 of the first transistor T1 and the gate 421 of the first transistor T1 .

Of course, referring to FIG. 12 b , based on the structure of the memory cell shown in FIG. 11 , the channel widths of the first transistor T1 and the second transistor T2 can also be increased by forming a concave channel layer structure to avoid the short channel effect.

Since the storage unit structures provided in Figures 10 and 11 have the same working principles and similar structures, the storage unit shown in Figure 10 will be used as an example when introducing the examples of this application later. Of course, it can also be applied to the storage unit provided in Figure 11.

Based on the memory cell structure provided in FIG10 , FIG13 is a cross-sectional view of a process structure of another memory cell provided in an embodiment of the present application. A conductive film layer is further provided in the first transistor T1 and the second transistor T2. In the first transistor T1, the conductive film layer 416 is used to connect the first electrode 412 and the second electrode 413 of the first transistor T1, thereby improving the ohmic contact and increasing the on-current of the first transistor T1. In the second transistor T2, the conductive film layer 426 is used to connect the first electrode 422 and the second electrode 423 of the second transistor T2, thereby improving the ohmic contact and increasing the on-current of the second transistor T2.

Referring to FIG. 14 , FIG. 14 shows a schematic diagram of a memory cell stack. The memory array provided by the embodiment of the present application can be stacked in a direction perpendicular to the substrate 100 to increase the storage density. Different memory layers in the Z direction are separated by an insulating medium, so that any memory cell of any layer of the memory array can be accessed during the reading and writing process without affecting the data reading and writing of other layers of the memory array. The insulating medium can be aluminum oxide (AlOx).

FIG15 is a simplified schematic diagram of a three-dimensional structure diagram of a memory 300 provided in the present application. In FIG15 , it is exemplarily shown that the memory 300 includes a layer of memory array. Of course, in an optional embodiment, more layers of memory arrays can also be stacked in a direction perpendicular to the substrate.

As shown in FIG15 , any layer of the storage array includes a plurality of storage cells arranged along a first direction. In order to distinguish these storage cells, they are respectively identified as storage cells MC1 to MC4. For example, the storage cells MC1 and MC2 shown in FIG15 are arranged in the first direction, and the storage cells MC3 and MC4 are arranged in the first direction. Any layer of the storage array also includes a plurality of storage cells arranged along a second direction. For example, as shown in FIG15 , the storage cells MC1 and MC3 are arranged in the second direction, and the storage cells MC2 and MC4 are arranged in the second direction, wherein the first direction is perpendicular to the second direction. Here, the first direction may refer to the X direction shown in the figure, and the second direction may refer to the Y direction shown in the figure.

The storage array also includes a plurality of write word lines, write bit lines, read word lines and read bit lines, wherein the write word lines and read word lines extend along a first direction, for example, WWL1 shown in FIG. 15 extends along the first direction and WWL2 extends along the first direction; RWL1 extends along the first direction and RWL2 extends along the first direction; the write bit lines and read bit lines extend along a second direction, for example, as shown in FIG. 15, WBL1 extends along the second direction and WBL2 extends along the second direction; RBL1 extends along the first direction and RBL2 extends along the second direction.

The write word line is electrically connected to the gates of the first transistors T1 of the plurality of memory cells located in the first direction, for example, as shown in FIG15 , WWL1 is connected to the gates of the first transistors T1 of MC1 and MC2; the write bit line is electrically connected to the first electrodes of the first transistors T1 of the plurality of memory cells located in the second direction, for example, WBL1 is connected to the first electrodes of the first transistors T1 of MC1 and MC3; the read word line is electrically connected to the first electrodes of the second transistors T2 of the plurality of memory cells located in the first direction, for example, RWL2 is connected to the first electrodes of the second transistors T2 of MC1 and MC2; the read bit line is electrically connected to the second electrodes of the second transistors T2 of the plurality of memory cells located in the second direction, for example, RBL2 is connected to the second electrodes of the second transistors T2 of MC2 and MC4.

In other words, the gate of the first transistor T1 is connected to the write word line, the first electrode of the first transistor T1 is connected to the write bit line, the first electrode of the second transistor T2 is connected to the read word line, and the second electrode of the second transistor T2 is connected to the read bit line. Of course, in each memory cell, the second electrode of the first transistor T1 of the memory cell is connected to the gate of the second transistor T2.

The write word line is located on a side of the first transistor T1 away from the substrate 100, and the gate 411 of the first transistor T1 is away from the surface of the substrate 100 and contacts the write word line. For example, as shown in FIG15, WWL2 contacts the gate 411 of the first transistor T1. The film layer position of the write bit line in the direction perpendicular to the substrate 100 is located in the same layer as the first electrode 412 of the first transistor T1. For example, as shown in FIG15, WBL2 is located in the same layer as the first electrode 412 of the first transistor T1. The film layer position of the read word line in the direction perpendicular to the substrate 100 is located in the same layer as the first electrode 422 of the second transistor T2; for example, as shown in FIG15, RWL2 is located in the same layer as the first electrode 422 of the second transistor T2; the film layer position of the read bit line in the direction perpendicular to the substrate 100 is located in the same layer as the second electrode 423 of the second transistor T2. For example, as shown in FIG15, RBL2 is located in the same layer as the second electrode 423 of the second transistor T2.

In some possible implementations, the write bit line and the first electrode of the first transistor T1 are formed of the same material, and the write bit line is integrally arranged with the first electrode 412 of the first transistor T1, or the write bit line can also serve as the first electrode of the first transistor T1; the read word line and the first electrode of the second transistor T2 are formed of the same material, and the read word line and the first electrode 422 of the second transistor T2 are integrally arranged, or the read word line can also serve as the first electrode of the second transistor T2; the read bit line and the second electrode 423 of the second transistor T2 are formed of the same material, and the read bit line and the second electrode 423 of the second transistor T2 are integrally arranged, or the read bit line can also serve as the second electrode of the second transistor T2.

The following introduces the materials that can be selected for the first transistor T1, the second transistor T2, the write word line, the write bit line, the read word line, and the read bit line.

Among them, the materials of the write bit line, the read bit line, and the read word line are the same; the materials of the write word line and the write bit line are different, or in other words, the materials of the first electrode 412 of the first transistor T1, the first electrode 422, and the second electrode 423 of the second transistor T2 are the same and different from the material of the write word line. The write word line and the write bit line are two materials with a higher selective etching ratio. Since the write word line is connected to the gate of the first transistor T1, and the gate of the first transistor T1 is located on the side away from the substrate, that is to say, the first transistor T1 and the second transistor T2 are both located in the space between the write word line and the substrate, in order to avoid affecting the write word line when preparing the first transistor T1, the second transistor T2 and other control lines, the materials of the write word line and the write bit line, the read word line, the read bit line, etc. are different, for example, they can be two materials with a higher selective etching ratio, so that they can not affect each other during etching.

The second electrode 413 of the first transistor T1 contacts the gate 421 of the second transistor T2 . The second electrode 413 of the first transistor T1 can be used as the SN of the memory cell. The second electrode 413 of the first transistor T1 is made of the same material as the write word line.

The gate 411 of the first transistor T1 and the gate 421 of the second transistor T2 are ring structures, and the axes they surround are perpendicular to the substrate 100. The materials used to prepare the gate 411 of the first transistor T1 and the gate 421 of the second transistor T2 can be the same as the material of the write word line, or the same as the material of the read bit line. Of course, the materials used to prepare the gate 411 of the first transistor T1 and the gate 421 of the second transistor T2 can be different from the material of the write word line or the read bit line.

Exemplarily, the write line, the second electrode 423 of the first transistor T1, the gate 411 of the first transistor T1, and the gate 421 of the second transistor T2 are metal materials or other conductive materials, for example, titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (Wu), molybdenum (Mo), indium tin oxide (ITO), indium zinc oxide (IZO), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag) and the like, or any combination thereof.

The write bit line, read word line, and read bit line can be made of metal materials or other conductive materials, for example, titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (Wu), molybdenum (Mo), indium tin oxide (ITO), indium zinc oxide (IZO), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag) and other materials or any combination thereof, but the materials of the write bit line, read word line, and read bit line are different from those of the write word line.

The gate oxide dielectric layer is _an insulating material, such as silicon dioxide ( _SiO2 ), aluminum oxide ( _Al2O3 ), hafnium oxide ( _HfO2 ), zirconium dioxide ( _ZrO2 ), titanium dioxide ( _TiO2 ), yttrium oxide ( _Y2O3 ), silicon _nitride ( _Si3N4 ) and other insulating materials, or aluminum (Al) doped hafnium oxide ( _HfO2 ), silicon (Si) doped hafnium oxide ( _HfO2 ), zirconium ( _Zr ) doped hafnium oxide ( _HfO2 ), lanthanum doped hafnium oxide ( _HfO2 ), yttrium (Y) doped hafnium oxide ( _HfO2 ) and other ferroelectric materials, or any combination thereof, laminated structure and laminated structure of combined materials, etc.

The material of the channel layer can be silicon-based semiconductor materials such as silicon (Si), polycrystalline silicon (poly-Si), amorphous silicon (amorphous-Si), or metal oxides such as indium trioxide (In ₂ O ₃ ), zinc oxide (ZnO), gallium trioxide (Ga ₂ O ₃ ), indium tin oxide (ITO), titanium dioxide (TiO ₂ ), indium gallium zinc oxide (In-Ga-Zn-O), indium tin zinc oxide (In-Sn-Zn-O), etc. Two-dimensional semiconductor materials such as multi-component compounds, graphene, molybdenum disulfide (MoS ₂ ), black phosphorus, or any combination thereof.

The above-mentioned conductive film layers 416 and 426 can be heavily doped conductive materials, for example, they can be indium gallium zinc oxide (IGZO) with a high indium (In) content, indium oxide (InOx), zinc oxide (ZnO), C-axis aligned crystalline indium gallium zinc oxide (CAAC IGZO), indium tin oxide (ITO), etc.

In addition, in combination with Figure 3 and Figure 14, the storage unit provided in the embodiment of the present application can further improve the storage density by stacking layers in a direction perpendicular to the substrate (such as the Z direction in the figure), and different storage layers _are isolated by a dielectric layer. The dielectric layer here is made of an insulating material, for example, it can be silicon dioxide ( _SiO2 ), aluminum oxide ( _Al2O3 ), hafnium dioxide ( _HfO2 ), zirconium dioxide ( _ZrO2 ), titanium dioxide ( _TiO2 ), _yttrium oxide ( _Y2O3 ), silicon _nitride ( _Si3N4 ) and other insulating materials or any combination of them, laminated structure and laminated structure of combined materials.

In addition, the embodiment of the present application also provides a method for forming a memory array. FIG. 16 exemplarily shows a schematic diagram of a process for preparing the memory array provided in the embodiment of the present application.

Step S1: forming a first transistor and a second transistor in a direction perpendicular to a substrate, wherein the first transistor and the second transistor both include a gate, a first electrode, a second electrode, and a channel layer connecting the first electrode and the second electrode; wherein the first electrode and the second electrode of the first transistor are arranged in a direction perpendicular to the substrate, the channel layer of the first transistor is annular, and the axis surrounded by the channel layer of the first transistor is perpendicular to the substrate; the gate of the second transistor is away from the surface of the substrate and contacts the second electrode of the first transistor; the first electrode and the second electrode of the second transistor are arranged in a direction perpendicular to the substrate, the channel layer of the second transistor is annular, and the axis surrounded by the channel layer of the second transistor is perpendicular to the substrate.

Step S2: forming a write bit line, a write word line, a read bit line and a read word line, and the gate of the first transistor is electrically connected to the write word line, the first electrode of the first transistor is electrically connected to the write bit line, the first electrode of the second transistor is electrically connected to the read word line, and the second electrode of the second transistor is electrically connected to the read bit line.

It should be noted that the above-mentioned steps S1 and S2 are not limited to the process flow in which step S1 is performed first and then step S2. In some optional process flows, step S1 and step S2 may be performed simultaneously; or part of the process in step S2 may be performed simultaneously with step S1; or part of the process in step S1 may be performed simultaneously with step S2.

Exemplarily, step S1 includes:

S1a: The second electrode of the first transistor, the first electrode of the second transistor, the second electrode of the first transistor and the first electrode of the first transistor are formed in a direction perpendicular to the substrate. The second electrode of the second transistor, the first electrode of the second transistor, the second electrode of the first transistor and the first electrode of the first transistor are all ring-shaped and perpendicular to the substrate.

In the embodiment of the present application, the first electrode of the first transistor, the second electrode, the first electrode of the second transistor, and the second electrode are perpendicular to the substrate and are distributed in a direction perpendicular to the substrate. Therefore, the first electrode of the first transistor, the second electrode, and the first electrode of the second transistor can be formed by stacking the materials of the first electrode and the second electrode and then opening a through hole. There is no need to use a mask to prepare the first electrode and the second electrode of the first transistor and the second transistor respectively. This can reduce the number of masks required and reduce the difficulty and cost of the preparation process.

S1b: forming a channel layer of a second transistor and a channel layer of a first transistor, wherein the channel layer of the first transistor and the channel layer of the second transistor are both annular and perpendicular to the substrate, and the channel layer of the first transistor connects the first electrode and the second electrode of the first transistor; and the channel layer of the second transistor connects the first electrode and the second electrode of the second transistor.

Exemplarily, forming the channel layer of the second transistor includes: forming the fourth part, the fifth part and the sixth part of the channel layer of the second transistor, the fourth part contacts the first electrode of the second transistor; the sixth part contacts the second electrode of the first transistor; the fifth part connects the fourth part and the sixth part.

Exemplarily, forming the channel layer of the first transistor includes: forming a first part, a second part and a third part of the channel layer of the first transistor, the first part contacts the first electrode of the first transistor; the third part contacts the second electrode of the first transistor; the third part connects the first part and the third part.

The channel layer of the first transistor and the channel layer of the second transistor can be prepared at the same time.

S1c: forming a gate oxide dielectric layer of the second transistor and a gate oxide dielectric layer of the first transistor.

S1d: forming the gate of the second transistor and the gate of the first transistor, the channel layer of the first transistor surrounds the gate of the first transistor; the channel layer of the second transistor surrounds the gate of the second transistor, and the gate of the second transistor is away from the surface of the substrate and contacts the second electrode of the first transistor.

Exemplarily, forming the gate of the first transistor includes: forming a first gate portion of the gate, the extension direction of the first gate portion A second gate portion connected to the first gate portion is formed, and an extending direction of the second gate portion is perpendicular to the substrate.

Exemplarily, forming the gate of the second transistor includes: forming a third gate portion of the gate, wherein the extension direction of the third gate portion is parallel to the substrate; and forming a fourth gate portion connected to the third gate portion, wherein the extension direction of the fourth gate portion is perpendicular to the substrate.

Here, the extension lengths of the first gate portion of the gate of the first transistor and the third gate portion of the gate of the second transistor can be adjusted as required.

Exemplarily, forming a write word line, a write bit line, a read word line, and a read bit line includes:

A write word line is formed on a side of the first transistor away from the substrate, and a gate of the first transistor is in contact with the write word line on a surface away from the substrate; a write bit line is formed in a film layer in a direction perpendicular to the substrate and in the same layer as the first electrode of the first transistor; a read word line is formed in a film layer in a direction perpendicular to the substrate and in the same layer as the first electrode of the second transistor; and a read bit line is formed in a film layer in a direction perpendicular to the substrate and in the same layer as the second electrode of the second transistor.

The specific process flow involved in the above-mentioned step S1 and step S2 is introduced below in conjunction with the accompanying drawings.

17a to 17m are schematic cross-sectional views of the process structure after each step in the process of manufacturing a storage array according to an embodiment of the present application is completed.

As shown in FIG. 17 a , a stacked structure of a first conductive layer 002 and a first sacrificial layer 003 is sequentially formed on the substrate 100 along a direction perpendicular to the substrate 100 .

The first conductive layer 002 here can be a metal material, such as titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (Wu), molybdenum (Mo), indium tin oxide (ITO), indium zinc oxide (IZO), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag) and any other materials or any combination thereof.

The material of the first sacrificial layer 003 here may be silicon oxide, such as SiOx.

As shown in FIG17b, a groove 004 is formed on the stacked first conductive layer 002 and the first sacrificial layer 003, and then an insulating medium 005 is filled in the groove 004. For example, as shown in FIG17c, the material of the insulating medium 005 may be SiNx, and after the insulating medium 005 is backfilled, a process such as chemical mechanical polishing (CMP) is used for planarization.

As shown in FIG17d, a second conductive layer 006, a first insulating dielectric layer 007, a second sacrificial layer 008, a third sacrificial layer 009 and a third conductive layer 010 are sequentially deposited on the stacked first conductive layer 002 and the first sacrificial layer 003. Then, a groove 011 is etched again to the first insulating dielectric layer 007. Then, referring to FIG17e, an insulating dielectric 012 is backfilled in the groove 011. The material of the insulating dielectric 012 can be the same as that of the insulating dielectric 005. After the insulating dielectric 012 is backfilled, a planarization process is performed using a process such as chemical mechanical polishing (CMP).

As shown in FIG. 17 f , a second insulating dielectric layer 013 and a fourth conductive layer 014 are sequentially deposited on the third conductive layer 010 . The fourth conductive layer 014 is made of a different material from the first conductive layer 002 , the second conductive layer 006 , and the third conductive layer 010 .

As shown in FIG17g, a through hole is opened so that the through hole passes through the fourth conductive layer 014, the second insulating dielectric layer 013, the third conductive layer 010, the third sacrificial layer 009, the second sacrificial layer 008 and the first insulating dielectric layer 007, the second conductive layer 006, the first sacrificial layer 003 and the first conductive layer 002 in sequence. As shown in FIG17g, the structure shown in FIG17g has two holes, namely hole 015 and hole 016, each hole corresponds to a storage unit, so the structure shown in FIG17g can prepare two storage units distributed along a direction parallel to the substrate.

As shown in FIG. 17h , the second sacrificial layer 008 is removed. For example, the second sacrificial layer 008 can be removed from the opened holes 15 and 16 by using a wet etching process.

After removing the second sacrificial layer 008 , a conductive material is grown in the cavity formed by removing the second sacrificial layer 008 to form a fifth conductive layer 017 . Here, the fifth conductive layer 017 may be made of a metal material, and the metal material of the fifth conductive layer 017 may be the same as that of the fourth conductive layer 014 .

As shown in FIG17i, the third sacrificial layer 009 and the first sacrificial layer 003 are partially removed (or completely removed), and then the first conductive layer 002, the second conductive layer 006, and the third conductive layer 010 are partially removed. Here, the third sacrificial layer 009 and the first sacrificial layer 003 can be partially removed (or completely removed) by a process such as wet etching, and then the first conductive layer 002, the second conductive layer 006, and the third conductive layer 010 are partially removed. Since the first conductive layer 002, the second conductive layer 006, and the third conductive layer 010 can be made of the same material, the same etchant can be used to partially remove the first conductive layer 002, the second conductive layer 006, and the third conductive layer 010, and the degree of etching can be adjusted by controlling the length of the etching time.

After partially removing (or completely removing) the third sacrificial layer 009 and the first sacrificial layer 003, and then partially removing the first conductive layer 002, the second conductive layer 006, and the third conductive layer 010, the internal apertures of the original holes 015 and 016 are enlarged, and are separated into upper and lower parts by the fifth conductive layer 017 and the first insulating dielectric layer 007 in the direction perpendicular to the substrate. Taking hole 015 as an example, it is divided into 015a and 015b, wherein the space of 015a is used to form the first transistor T1, and the space of 015b is used to form the second transistor T2.

In addition, in this step, the longer the time for etching the third sacrificial layer 009 and the first sacrificial layer 003 is, the more parts of the third sacrificial layer 009 and the first sacrificial layer 003 are corroded, so that the deeper the groove formed by removing the third sacrificial layer 009 and the first sacrificial layer 003 is, the deeper the concave structure formed when the channel layer and the gate oxide dielectric layer are formed in the subsequent process is. By controlling the length of time for etching the third sacrificial layer 009 and the first sacrificial layer 003, the depth of the concave structure formed in the channel layer can be adjusted. For example, the longer the time for etching the third sacrificial layer 009 and the first sacrificial layer 003 is, the deeper the depth of the concave structure formed in the channel layer is, the larger the width of the conductive channel is, and the larger the on-current of the transistor is.

Of course, in this step, the third sacrificial layer 009 and the first sacrificial layer 003 may not be etched, so that the gates of the first transistor T2 and the second transistor T2 will form a structure vertical to the substrate 100, and the channel layer and the gate oxide dielectric layer will not form a concave structure.

Referring to FIG. 17j, a semiconductor material layer 018 and a gate oxide dielectric layer 019 are sequentially grown in a cavity (e.g., 015a shown in FIG. 17i) formed by partially removing the third sacrificial layer 009 and the third conductive layer 010. A semiconductor material layer 020 and a gate oxide dielectric layer 021 are sequentially grown in a cavity (e.g., 015b shown in FIG. 17i) formed by partially removing the first conductive layer 002, the first sacrificial layer 003, and the second conductive layer 006.

For example, semiconductor material and gate oxide dielectric material can be sequentially deposited in the holes 015 and 016 shown in the figure using an atomic layer deposition (ALD) process to form a semiconductor material layer 018 and a gate oxide dielectric layer 019, as well as a semiconductor material layer 020 and a gate oxide dielectric layer 021.

The semiconductor material layer 018 is used to form the channel layer of the first transistor T1, and the gate oxide dielectric layer 019 is used to form the gate oxide dielectric layer of the first transistor T1; the semiconductor material layer 020 is used to form the channel layer of the second transistor T2, and the gate oxide dielectric layer 021 is used to form the gate oxide dielectric layer of the second transistor T2.

Among them, the material of the semiconductor material layers 018 and 020 can be silicon-based semiconductor materials such as silicon (Si), polycrystalline silicon (poly-Si), amorphous silicon (amorphous-Si), or metal oxides such as indium trioxide (In ₂ O ₃ ), zinc oxide (ZnO), gallium trioxide (Ga ₂ O ₃ ), indium tin oxide (ITO), titanium dioxide (TiO ₂ ), multi-component compounds such as indium gallium zinc oxide (In-Ga-Zn-O), indium tin zinc oxide (In-Sn-Zn-O), graphene, molybdenum disulfide (MoS ₂ ), black phosphorus and other two-dimensional semiconductor materials or any combination thereof. The material of the gate oxide dielectric layers 019 and 021 may be an insulating material, such as silicon dioxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ), titanium dioxide (TiO ₂ ), yttrium oxide (Y ₂ O ₃ ), silicon nitride (Si ₃ N ₄ ) and other insulating materials, or aluminum (Al) doped hafnium oxide (HfO ₂ ), silicon (Si) doped hafnium oxide (HfO ₂ ), zirconium (Zr) doped hafnium oxide (HfO ₂ ), lanthanum doped hafnium oxide (HfO ₂ ), yttrium (Y) doped hafnium oxide (HfO ₂ ) and other ferroelectric materials, or any combination thereof, laminated structure, and laminated structure of combined materials, etc.

As shown in Fig. 17k, a portion of the semiconductor material layer 018 is etched, and then a gate oxide dielectric layer 019 is deposited again. In this way, when forming the gate of the first transistor T1, the semiconductor material layer 018 is prevented from contacting the gate, and when forming the gate of the second transistor T2, the semiconductor layer 020 is prevented from contacting the gate.

As shown in Figure 17l, after the first insulating dielectric layer 007 and the second insulating dielectric layer 013 are partially removed, a part of 019 of the gate oxide dielectric layer (such as the part within the dotted box in the figure) will be protruding or suspended, and a part of 021 of the gate oxide dielectric layer (such as the part within the dotted box in the figure) will be protruding or suspended.

As shown in FIG. 17 m , the protruding or suspended portions of the gate oxide dielectric layer 019 and the gate oxide dielectric layer 021 are removed.

As shown in FIG17n, the gate material is filled in the hole using the ALD process. For example, the gate material 022 and the gate material 023 can be grown and filled through the hole 015 and the hole 016 shown in FIG17e. Exemplarily, the gate material 022 and the gate material 023 can be titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (Wu), molybdenum (Mo), indium tin oxide (ITO), indium zinc oxide (IZO), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag) and other materials or any combination thereof. Among them, the gate material 022 is used to form the gate of the first transistor T1, and the gate material 023 is used to form the gate of the second transistor T2.

As shown in FIG17o, after filling the gate material 022 and the gate material 023, they are etched back and then the insulating dielectric material 024 is filled in the hole, thereby forming a first transistor T1 and a second transistor T2 distributed in a direction vertical to the substrate 100, and the first transistor T1 and the second transistor T2 are both ring structures.

As can be seen from Figures 17a to 17o, the present application exemplarily provides a schematic diagram of a process for manufacturing a memory cell, wherein the first transistor and the second transistor of any memory cell are manufactured simultaneously, rather than manufacturing one transistor first and then the other transistor.

In addition, the process for making a memory cell provided in the embodiment of the present application only requires opening a hole in the stacked structure, and then performing etching, deposition, backfilling and other processes in the hole to form the memory cell, thereby reducing the number of masks and alignment steps required for preparing a horizontally structured transistor, and reducing the difficulty of the process.

From FIG. 17a to FIG. 17o, it can be seen that the two memory cells arranged along the X direction are separated by the insulating medium 005 and 012. However, the gates of the first transistors T1 of the two memory cells are connected to the WWL extending along the X direction, and the first electrodes of the second transistors T2 of the two memory cells are connected to the RWL extending along the X direction.

In addition, after forming a layer _of memory cells, an insulating medium may be grown on the layer of memory cells, where the insulating medium may be an insulating material such as _SiO2 , _Al2O3 , _HfO2 , _ZrO2 , _TiO2 , _Y2O3 , _Si3N4 , or _any combination of these materials, a laminated structure, and a laminated structure of the combined materials. Then another layer of memory cells is formed in the Z direction, and two adjacent layers _of memory cells in the Z direction may be separated by the insulating medium, thereby realizing three-dimensional stacking of the memory array.

From Figures 17a to 17o, it can be seen that the first conductive layer 002 is used to form the second electrode and the read word line of the second transistor T2, so the second electrode of the second transistor T2 and the read word line are located in the same layer and can be arranged as a whole; the second conductive layer 006 is used to form the first electrode and the read bit line of the second transistor T2, so the first electrode of the second transistor T2 and the read bit line are located in the same layer and can be arranged as a whole; the fifth conductive layer 017 is used to form the second electrode of the first transistor T1, the third conductive layer 010 is used to form the first electrode and the write bit line of the first transistor T1, so the first electrode of the first transistor T1 and the write bit line are located in the same layer and can be arranged as a whole, and the fourth conductive layer 014 is used to form the write word line, so the write word line is located on the side of the first transistor T1 away from the substrate.

Among them, the first conductive layer 002, the second conductive layer 006, and the third conductive layer 010 are made of the same conductive material, and the fourth conductive layer 014 and the fifth conductive layer 017 are made of the same conductive material, and the materials are different from those of the first conductive layer 002, the second conductive layer 006, and the third conductive layer 010. Therefore, the structure of the first transistor is slightly different from that of the second transistor.

For the first transistor T1, the second electrode 413 is located on the side of the gate 411 close to the substrate, while for the second transistor T2, the second electrode 423 is arranged around the gate 421. The reason for this difference is that the material of the second electrode 413 of the first transistor T1 is different from the material of the second electrode 423 of the second transistor T2, that is, the material of the first conductive layer 002 is different from that of the fifth conductive layer 017. However, the fifth conductive layer 017 will eventually form the second electrode of the first transistor T1, and the third conductive layer 010 will form the first electrode of the first transistor. The material of the fifth conductive layer 017 is different from that of the third conductive layer 010, that is, the material of the first electrode and the second electrode of the first transistor T1 are different, which will result in different contact resistances between the first electrode and the second electrode of the first transistor T1, which may affect the performance of the first transistor T1.

In addition, in a possible implementation, the material of the first conductive layer 002 may also be the same as that of the fifth conductive layer 017, that is, the material of the fifth conductive layer 017 and the first conductive layer 002 is the same, and the material of the second conductive layer 006 and the third conductive layer 010 is the same, so that the structure of the second electrode of the second transistor T2 is the same as that of the second electrode of the first transistor T1, and finally the second transistor T2 can form a channel layer, a gate oxide dielectric layer and a gate with the same structure as the first transistor T1, referring to FIG. 17p, in the memory cell formed in this way, the first transistor T1 and the second transistor T2 have the same structure, that is, the memory cell structure provided in FIG. 11 in the aforementioned example. However, similarly, such a preparation process will result in different materials for the first electrode and the second electrode of the first transistor T1, and different materials for the first electrode and the second electrode of the second transistor T2, resulting in that the performance of the first transistor T1 and the second transistor T2 will be affected.

In another implementation of the embodiment of the present application, the material of the first electrode or the second electrode of the transistor can be replaced based on the structure prepared as shown in Figure 17n or Figure 17p so that the material of the first electrode and the second electrode of the transistor are the same.

For example, referring to FIG. 17q, one possible implementation method is to completely remove the fifth conductive layer 017 based on the structure prepared in FIG. 17n, fill the space formed by removing the fifth conductive layer 017 with the same conductive material as the third conductive layer 010, and finally etch back, and then fill the hole with insulating dielectric material 024, thereby forming a first transistor T1 and a second transistor T2 distributed in a direction perpendicular to the substrate 100, wherein the first electrode and the second electrode of the first transistor T1 formed in this way are made of the same material.

Alternatively, referring to FIG. 17r, based on the structure prepared in FIG. 17p, the fifth conductive layer 017 and the first conductive layer 002 are completely removed (the material of the first conductive layer 002 here is the same as that of the fifth conductive layer 017), and then the space where the fifth conductive layer 017 and the first conductive layer 002 are removed is filled with a conductive material that is the same as that of the third conductive layer 010, and then the hole is filled with an insulating dielectric material 024, thereby forming a first transistor T1 and a second transistor T2 distributed in a direction perpendicular to the substrate 100, wherein the first electrode of the first transistor T1 formed in this way is made of the same material as that of the second electrode, and the first electrode of the second transistor T2 is made of the same material as that of the second electrode.

In other possible implementations of the present application, the materials of the first electrode and the second electrode of the transistor may be made the same in other ways, which is not limited in the embodiments of the present application.

In the description of the embodiments of the present application, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

A storage array, comprising:

substrate;

A plurality of storage layers are formed on the substrate, wherein the plurality of storage layers are stacked along a direction perpendicular to the substrate;

Each of the storage layers includes at least one storage unit, the storage unit includes a first transistor and a second transistor, and the first transistor and the second transistor are arranged in a direction perpendicular to the substrate;

The first transistor and the second transistor each include a gate, a first electrode, a second electrode, and a channel layer connecting the first electrode and the second electrode, wherein the gate, the first electrode, the second electrode, and the channel layer are all annular and perpendicular to the substrate;

The first electrode and the second electrode of the first transistor are arranged in a direction perpendicular to the substrate, the channel layer of the first transistor is perpendicular to the substrate, and the channel layer of the first transistor surrounds the gate of the first transistor; the gate of the second transistor is away from the surface of the substrate and contacts the second electrode of the first transistor;

The first electrode and the second electrode of the second transistor are arranged in a direction perpendicular to the substrate, the channel layer of the second transistor is perpendicular to the substrate, and the channel layer of the second transistor surrounds the gate of the second transistor.
The storage array according to claim 1, characterized in that

The gate of the first transistor is located at a side of the second electrode of the first transistor away from the substrate;

The first electrode of the first transistor is arranged around the gate.
The memory array according to claim 1 or 2, characterized in that the channel layer of the first transistor is in contact with both the first electrode and the second electrode of the first transistor;

The channel layer of the first transistor includes a first portion, a second portion and a third portion;

The first portion is located between the first electrode of the first transistor and the gate of the first transistor;

The third portion is located between the second electrode of the first transistor and the gate of the first transistor;

The second portion connects the first portion and the third portion.
The memory array according to any one of claims 1 to 3, characterized in that the gate of the first transistor comprises a first gate portion and a second gate portion connected to each other, an extension direction of the first gate portion is parallel to the substrate, and an extension direction of the second gate portion is perpendicular to the substrate;

The first electrode of the first transistor is located at a side of the first gate portion away from the substrate.
The storage array according to any one of claims 1 to 4 is characterized in that the first transistor further includes a gate oxide dielectric layer, the gate oxide dielectric layer is located between the channel layer of the first transistor and the gate of the first transistor, and the gate oxide dielectric layer of the first transistor separates the channel layer of the first transistor from the gate of the first transistor.
The memory array according to any one of claims 1 to 5, characterized in that the first transistor further comprises a conductive film layer, and the conductive film layer is arranged between the channel layer and the first electrode of the first transistor and the second electrode of the first transistor.
The memory array according to any one of claims 1 to 6, wherein an axis surrounded by the gate of the second transistor, the first electrode, and the second electrode is perpendicular to the substrate;

The first electrode and the second electrode of the second transistor surround the gate of the second transistor, wherein the first electrode of the second transistor is located on a side away from the substrate, and the second electrode of the second transistor is located on a side close to the substrate.
The memory array according to any one of claims 1 to 6, wherein the gate, the first electrode and the second electrode of the second transistor are ring-shaped, and the axis around which they are surrounded is perpendicular to the substrate;

The gate of the second transistor is located at a side of the second electrode of the second transistor away from the substrate;

The first electrode of the second transistor is arranged around the gate of the second transistor.
The memory array according to claim 7 or 8, characterized in that the channel layer of the second transistor is in contact with both the first electrode and the second electrode of the second transistor, and the channel layer of the second transistor includes a fourth portion, a fifth portion and a sixth portion;

wherein the fourth portion of the channel layer of the second transistor is located between the first electrode of the second transistor and the gate of the second transistor;

The sixth portion of the channel layer of the second transistor is located between the second electrode of the second transistor and the second crystal between the grids of the tube;

The fifth portion connects the fourth portion and the sixth portion.
The memory array according to any one of claims 7 to 9, characterized in that the gate of the second transistor comprises a third gate portion and a fourth gate portion connected;

The extension direction of the third gate portion is parallel to the substrate, and the extension direction of the fourth gate portion is perpendicular to the substrate;

The first electrode of the second transistor is located at a side of the third gate portion away from the substrate;

The second electrode of the second transistor is located at a side of the third gate portion facing the substrate.
The storage array according to any one of claims 7 to 10 is characterized in that the second transistor further includes a gate oxide dielectric layer, the gate oxide dielectric layer of the second transistor is located between the channel layer of the second transistor and the gate of the second transistor, and the gate oxide dielectric layer of the second transistor separates the channel layer of the second transistor from the gate of the second transistor.
The storage array according to any one of claims 7 to 11, characterized in that the second transistor further comprises a conductive film layer, and the conductive film layer is arranged between the channel layer of the second transistor and the first electrode of the second transistor and the second electrode of the second transistor.
The memory array according to any one of claims 1 to 12, characterized in that each of the memory layers further comprises a write word line, a write bit line, a read word line and a read bit line;

The gate of the first transistor is connected to the write word line, the first electrode of the first transistor is connected to the write bit line, the second electrode of the first transistor is connected to the gate of the second transistor, the first electrode of the second transistor is connected to the read word line, and the second electrode of the second transistor is connected to the read bit line.
The memory array according to claim 13, wherein the write word line is located on a side of the first transistor away from the substrate, and a surface of the gate of the first transistor away from the substrate contacts the write word line;

The film layer position of the write bit line in a direction perpendicular to the substrate is located in the same layer as the first electrode of the first transistor;

The film layer position of the read word line in a direction perpendicular to the substrate is located in the same layer as the first electrode of the second transistor;

The film layer position of the read bit line in a direction perpendicular to the substrate is located in the same layer as the second electrode of the second transistor.
The storage array according to claim 13 or 14, characterized in that the storage layer comprises a plurality of storage units;

The write word line and the read word line both extend in a first direction parallel to the substrate; the write bit line and the read bit line both extend in a second direction parallel to the substrate;

The write word line is electrically connected to the gates of the first transistors of the plurality of memory cells located in the first direction;

The write bit line is electrically connected to the first electrodes of the first transistors of the plurality of the memory cells located in the second direction;

The read word line is electrically connected to the first electrodes of the second transistors of the plurality of memory cells located in the first direction;

The read bit line is electrically connected to second electrodes of second transistors of a plurality of memory cells located in the second direction.
The memory array according to any one of claims 13 to 15, wherein the write bit line is integrally provided with the first electrode of the first transistor;

The read word line is integrally arranged with the first electrode of the second transistor;

The read bit line is integrally arranged with the second electrode of the second transistor.
A memory, comprising:

The storage array according to any one of claims 1 to 16;

A controller is electrically connected to the storage array, and is used to control the reading and writing of the storage array.
A method for manufacturing a memory, characterized in that the manufacturing method comprises:

A second electrode of a second transistor, a first electrode of a second transistor, a second electrode of a first transistor and a first electrode of a first transistor are formed in a direction perpendicular to the substrate, wherein the second electrode of the second transistor, the first electrode of the second transistor, the second electrode of the first transistor and the first electrode of the first transistor are all ring-shaped and perpendicular to the substrate;

A channel layer of the second transistor and a channel layer of the first transistor are formed, and the channel layer of the first transistor and the channel layer of the first transistor are The channel layers of the second transistors are all ring-shaped and perpendicular to the substrate, the channel layer of the first transistor connects the first electrode and the second electrode of the first transistor; the channel layer of the second transistor connects the first electrode and the second electrode of the second transistor;

The gate of the second transistor and the gate of the first transistor are formed, and the channel layer of the first transistor surrounds the gate of the first transistor; the channel layer of the second transistor surrounds the gate of the second transistor, and the gate of the second transistor is away from the surface of the substrate and contacts the second electrode of the first transistor.
The method according to claim 18 is characterized in that forming the channel layer of the first transistor includes: forming a first part, a second part and a third part of the channel layer of the first transistor, the first part is in contact with the first electrode of the first transistor; the third part is in contact with the second electrode of the first transistor; the third part connects the first part and the third part.
The method according to claim 18 or 19, characterized in that forming the gate of the first transistor comprises:

forming a first gate portion of the gate, wherein an extension direction of the first gate portion is parallel to the substrate;

A second gate portion connected to the first gate portion is formed, and an extending direction of the second gate portion is perpendicular to the substrate.
The method according to any one of claims 18 to 20, characterized in that forming the channel layer of the second transistor comprises:

The fourth, fifth and sixth parts of the channel layer of the second transistor are formed, the fourth part is in contact with the first electrode of the second transistor; the sixth part is in contact with the second electrode of the first transistor; and the fifth part connects the fourth part and the sixth part.
The method according to any one of claims 18 to 21, characterized in that forming the gate of the second transistor comprises:

forming a third gate portion of the gate, wherein an extension direction of the third gate portion is parallel to the substrate;

A fourth gate portion connected to the third gate portion is formed, and an extending direction of the fourth gate portion is perpendicular to the substrate.
The method according to any one of claims 18 to 22, characterized in that the method further comprises:

forming a write word line, a write bit line, a read word line and a read bit line;

The gate of the first transistor is connected to the write word line, the first electrode of the first transistor is connected to the write bit line, the second electrode of the first transistor is connected to the gate of the second transistor, the first electrode of the second transistor is connected to the read word line, and the second electrode of the second transistor is connected to the read bit line.
The method according to claim 23, wherein forming the write word line, the write bit line, the read word line and the read bit line comprises:

The write word line is formed on a side of the first transistor away from the substrate, and a surface of the gate of the first transistor away from the substrate is in contact with the write word line;

Forming the write bit line in a film layer in a direction perpendicular to the substrate and in a same layer as the first electrode of the first transistor;

forming the read word line in a film layer in a direction perpendicular to the substrate and in a same layer as the first electrode of the second transistor;

The read bit line is formed in a film layer in a direction perpendicular to the substrate and in the same layer as the second electrode of the second transistor.
The method according to claim 23 or 24, characterized in that the forming of the write word line, the write bit line, the read word line and the read bit line further comprises:

The write bit line is integrally arranged with the first electrode of the first transistor;

The read word line is integrally arranged with the first electrode of the second transistor;

The read bit line is integrally arranged with the second electrode of the second transistor.
An electronic device, comprising: a processor and the memory as claimed in claim 17, wherein the processor and the memory are electrically connected.