WO2023197769A1

WO2023197769A1 - Cmos inverter, storage chip, memory and electronic device

Info

Publication number: WO2023197769A1
Application number: PCT/CN2023/079223
Authority: WO
Inventors: 孙莹; 黄凯亮; 王昭桂; 景蔚亮; 王正波; 廖恒
Original assignee: 华为技术有限公司
Priority date: 2022-04-15
Filing date: 2023-03-02
Publication date: 2023-10-19
Also published as: CN116978909A

Abstract

The present application provides a CMOS inverter, a storage chip, a memory and an electronic device. In the CMOS inverter, a support portion is located on the surface of a substrate and is provided with a first vertical sidewall and a second vertical sidewall which are opposite to each other, a film-like first channel structure extends along the first vertical sidewall, and a second channel structure is provided on the second vertical sidewall, such that the occupied area can be reduced. A common drain is electrically connected to the first channel structure and the second channel structure separately, a first source is electrically connected to the first channel structure, and the first source and the common drain are arranged at intervals. The second source is electrically connected to the second channel structure, and the second source and the common drain are arranged at intervals. To control ON/OFF of the first channel structure and the second channel structure, a common gate is separately spaced apart from the first channel structure and the second channel structure by means of a gate dielectric layer. The first channel structure and the second channel structure have opposite carrier types, and the formed two transistors comprise one PMOS and one NMOS.

Description

A CMOS inverter, memory chip, memory and electronic device

Cross-references to related applications

This application requires the priority of the Chinese patent application submitted to the China Patent Office on April 15, 2022, with the application number 202210400163.3 and the application title "A CMOS inverter, memory chip, memory and electronic device", and its entire content incorporated herein by reference.

Technical field

The present application relates to the technical field of electronic products, and in particular to a CMOS inverter, memory chip, memory and electronic device.

Background technique

In recent years, for large-capacity, high-speed and low-power storage, the industry has proposed three-dimensional integrated memory, on-chip integrated memory, BEOL (Back End Of Line) memory, new memory based on new materials, and gain-cell (gain stage) structured memory and other solutions. Among them, the 2T0C structure gain-cell memory can achieve nanosecond-level read and write speeds and millisecond-level storage times, and its area is only one-third of SRAM (Static Random-Access Memory). . In order to improve the storage duration and storage capacity, some people have proposed to prepare 2T0C structure memory based on TFT (Thin Film Transistor, thin film transistor). On the one hand, taking advantage of the ultra-low leakage of TFT greatly improves the retention time of 2T0C memory and reduces dynamic power consumption; on the other hand, taking advantage of the low process temperature of TFT, three-dimensional memory integration can be achieved and can also be applied to BEOL realizes three-dimensional system integration.

However, as the storage density of Dynamic Random Access Memory (DRAM) continues to increase, the integration requirements for memory peripheral circuits are also getting higher and higher. In order to save the area occupied by front-end peripheral circuits, in the BEOL process The realization of CMOS (Complementary Metal-Oxide-Semiconductor, complementary metal oxide semiconductor) integration is called the potential trend of current development. At present, TFT technology based on low-temperature oxide semiconductor (oxide semiconductor, OS) can already realize stable and excellent performance NMOS (N-type Metal Oxide Semiconductor, N-channel metal oxide semiconductor) devices. However, due to the inherent characteristics of oxide semiconductor The conductive mechanism makes it difficult to implement a stable PMOS (P-type Metal Oxide Semiconductor, P-channel metal oxide semiconductor) device. If only NMOS is integrated, there will always be one transistor in a normally open state, and the static power consumption will be large. At the same time, with the development of Moore's Law, the size of devices continues to shrink. In order to ensure that transistor devices maintain excellent electrical performance while shrinking, people have proposed three-dimensional structure CMOS devices.

The CMOS inverter device in the DRAM peripheral circuit is formed by the metal interconnection of planar structure transistors prepared in the front-end process. As the storage density increases, the number of front-end transistors continues to increase, which brings greater challenges to the front-end. Integrated area consumption and cost pressure. For example, in a three-dimensional CMOS inverter based on LTPO (Low Temperature Polycrystalline Oxide) as a conductive channel, p-type and n-type conductive channels are stacked vertically to form a CMOS inverter device; due to The conductive channel has a planar structure, resulting in low space utilization. To further reduce the device area, high-precision photolithography technology is required.

Contents of the invention

This application provides a CMOS inverter, memory chip, memory and electronic device, which are used to reduce the area occupied by the CMOS inverter and improve space utilization.

In a first aspect, a CMOS inverter is provided. The CMOS inverter includes: a substrate, a support part, a first channel structure, a second channel structure, a first source, a second source, and a common gate. electrode, a gate dielectric layer and a common drain; the support portion is located on the surface of the substrate and has first vertical sidewalls and second vertical sidewalls arranged oppositely, and the film-like first channel structure extends along the first vertical sidewall, The second channel structure is disposed on the second vertical side wall and only occupies a space equivalent to the film thickness of the first channel structure in the direction parallel to the substrate, which can reduce the area occupied by the CMOS inverter; the common drain Both ends are electrically connected to the first channel structure and the second channel structure respectively. The first source is electrically connected to the first channel structure and is spaced apart from the common drain. The second source is electrically connected to the second channel structure. Electrically connected and spaced apart from the common drain; in order to control the on and off of the first channel structure and the second channel structure, the common gate is spaced apart from the first channel structure and the second channel structure respectively through the gate dielectric layer . The first source electrode, the first channel structure, the common gate electrode, the gate dielectric layer and the common drain electrode form a transistor, and the second source electrode, the second channel structure, the common gate electrode, the gate dielectric layer and the common drain electrode form another transistor. A transistor, and the first channel structure and the second channel structure have opposite carrier types, therefore, the two transistors formed include a PMOS and an NMOS.

In a specific implementation, the surface of the first vertical side wall is a plane, which is beneficial to reducing the process difficulty of forming a film on the first vertical side wall and its surface.

In a specific implementation, in order to increase the extension area of the first channel to increase its gate control capability and effective channel width, the first vertical sidewall has a plurality of first trenches spaced apart along the vertical direction. Groove, the portion of the first channel structure corresponding to each first groove extends along the inner wall of the first groove.

In a specific implementation, the surface of the second vertical side wall is a plane, and the second channel structure is in the shape of a film and extends along the surface of the second vertical side wall, which is beneficial to reducing the distance between the second vertical side wall and the second vertical side wall. The process difficulty of the channel structure.

In a specific implementation, the second vertical sidewall has a plurality of second grooves spaced apart along the vertical direction, and at least part of the second channel structure is distributed in each second groove to accommodate at least part of the second channel structure.

In a specific implementation, the second channel structure includes a plurality of nanowires, the plurality of nanowires are at least partially disposed in the plurality of second trenches on a one-to-one basis, and the nanowires do not occupy additional space outside the support portion. , reduce the occupied area.

In a specific implementation, the first channel structure is made of n-type semiconductor channel material, and each nanowire in the second channel structure is a p-type nanowire, which is beneficial to the formation of n-type nanowires. A stable n-type first channel structure film, while p-type nanowires have better stability.

In a specific implementation, in order to increase the extension area of the first channel to increase its gate control capability and effective channel width, the second channel is film-shaped and extends along the second vertical sidewall, And the portion corresponding to each second groove extends along the inner wall of the second groove.

In a specific implementation, when the second vertical sidewall has a plurality of first grooves spaced apart along the vertical direction, the plurality of first grooves and the plurality of second grooves are one-to-one; this In this case, the support part may include a plurality of first insulating dielectric layers and a plurality of second insulating dielectric layers stacked alternately on the substrate along a vertical direction, and the second insulating dielectric layer and the first insulating dielectric layer are made of different materials. ; The two vertical sides of each second insulating dielectric layer with smaller hardness can be used to form the first trench and the second trench respectively with the first insulating dielectric layer with larger hardness on both sides in the vertical direction. The above structural form is conducive to reducing the process difficulty and can be achieved by wet selective etching.

In a specific implementation, when the surface of the first vertical sidewall is planar, the support portion includes a plurality of first insulating dielectric layers and a plurality of second insulating dielectric layers alternately stacked on the substrate along a vertical direction, The second insulating dielectric layer and the An insulating dielectric layer is made of different materials; a vertical side of each second insulating dielectric layer and the first insulating dielectric layer on both sides in the vertical direction form a first trench. The above structural form is conducive to reducing process difficulty, which can be achieved by wet selective etching. During wet selective etching, the etching selectivity ratio of the second insulating dielectric layer is greater than the etching selectivity ratio of the first insulating dielectric layer. .

In order to gate two transistors simultaneously, the selection of the common gate can take many forms. In a specific implementation, the common gate includes an inner gate, the gate dielectric layer includes an inner gate dielectric layer, the inner gate is located between the first channel structure and the second channel structure, and is connected to the inner gate dielectric layer through the inner gate dielectric layer. The first channel structure and the second channel structure are spaced apart; and/or the common gate includes an outer gate, the gate dielectric layer includes an outer gate dielectric layer, and the outer gate is located on a side of the first channel structure away from the second channel structure. side, and a side of the second channel structure away from the first channel structure, and is spaced apart from the first channel structure and the second channel structure respectively through the outer gate dielectric layer. The above three solutions can all achieve gate control of the first channel structure and the second channel structure.

In a specific implementation, when the common gate includes both an inner gate and an outer gate, the inner gate and the outer gate are electrically connected to achieve a full gate structure with strong gate control capability.

In a specific implementation, when the surface of the first vertical sidewall and the surface of the second vertical sidewall are both planar, the inner gate is disposed on the substrate to form a support part; using the inner gate as the support part is beneficial Increase the volume of the inner gate to increase gate control capability.

In a specific implementation, in order to reduce costs, the inner gate is in the form of a thin film and is located between the first channel structure and the support portion to form a back gate structure; and/or, in order to reduce the cost, the outer gate is in the form of a thin film. shape, the outer gate is located on a side of the first channel structure away from the support portion. Moreover, when the above-mentioned thin-film inner gate and outer gate bend and extend along the inner wall of the first trench or the second trench, the overlapping area with the first channel structure or the second channel structure is increased, increasing the To achieve its gate control capability.

In a specific implementation, the inner gate dielectric layer includes a first part and a second part, the first part corresponds to the first channel structure, the second part corresponds to the second channel structure, and the first part and the second part adopt Made of different materials. To separately control the threshold voltage of the two transistors, adjust the symmetry of the two transistors, optimize the performance of the CMOS inverter, and reduce power consumption.

In a specific implementation, the inner gate is electrically isolated from the corresponding parts of the first part and the second part respectively, so as to provide different gate voltages respectively and further adjust the symmetry of the two transistors.

In a second aspect, a memory chip is provided. The memory chip can be used in a memory, such as a dynamic random access memory. The memory chip includes: an upstream device, a downstream device and a CMOS inverter according to any of the above technical solutions. The upstream device The device is electrically connected to the common gate of the CMOS inverter, and the downstream device is electrically connected to the common drain. Compared with using the metal interconnection of planar structure transistors prepared in the previous process to form a CMOS inverter, it can produce a greater cost advantage, and improve space utilization, which is beneficial to improving performance.

In a third aspect, a memory is provided. The memory may be a dynamic random access memory, including a circuit board and the memory chip described in the above technical solution. The memory chip is disposed on the circuit board and is electrically connected to the circuit board. By utilizing the above-mentioned memory chip, higher storage performance can be brought about, and the beneficial effects can be referred to the memory chip of the above-mentioned scheme.

The fourth aspect provides an electronic device. The electronic device can be a terminal device such as a mobile phone or a computer, or an intermediate-level electronic module such as a display panel and a motherboard. The electronic device includes: upstream devices, downstream devices and any of the above technical solutions. In the CMOS inverter, the upstream device is electrically connected to the common gate of the CMOS inverter, and the downstream device is electrically connected to the common drain.

Description of the drawings

Figure 1 shows a circuit diagram of a CMOS inverter provided by an embodiment of the present application;

Figure 2 shows a perspective view of a CMOS inverter provided by an embodiment of the present application;

Figure 3 shows a top view of the CMOS inverter shown in Figure 2;

Figure 4 shows a cross-sectional view of the support part in Figure 1;

Figure 5 shows an A-A cross-sectional view of the CMOS inverter shown in Figure 1;

Figure 6 shows a B-B cross-sectional view of the CMOS inverter shown in Figure 1;

Figure 7 shows a perspective view of another CMOS inverter provided by an embodiment of the present application;

Figure 8 shows an A-A cross-sectional view of the supporting portion of the CMOS inverter shown in Figure 7;

Figure 9 shows a modified structure of the CMOS inverter shown in Figure 7;

Figure 10 shows a perspective view of another CMOS inverter provided by an embodiment of the present application;

Figure 11a shows a schematic diagram of step S101 of preparing the CMOS inverter shown in Figure 2;

Figure 11b shows a schematic diagram of step S102 of preparing the CMOS inverter shown in Figure 2;

Figure 11c shows a schematic diagram of step S103 of preparing the CMOS inverter shown in Figure 2;

Figure 11d shows a schematic diagram of step S104 of preparing the CMOS inverter shown in Figure 2;

Figure 11e shows a schematic diagram of step S105 of preparing the CMOS inverter shown in Figure 2;

Figure 11f shows a schematic diagram of step S106 of preparing the CMOS inverter shown in Figure 2;

Figure 11g shows a schematic diagram of step S107 of preparing the CMOS inverter shown in Figure 2;

Figure 11h shows a schematic diagram of step S108 of preparing the CMOS inverter shown in Figure 2;

Figure 12a shows a schematic diagram of step S201 of preparing the CMOS inverter shown in Figure 7;

Figure 12b shows a schematic diagram of step S202 of preparing the CMOS inverter shown in Figure 7;

Figure 12c shows a schematic diagram of step S203 of preparing the CMOS inverter shown in Figure 7;

Figure 12d shows a schematic diagram of step S204 of preparing the CMOS inverter shown in Figure 7;

Figure 12e shows a schematic diagram of step S205 of preparing the CMOS inverter shown in Figure 7;

Figure 12f shows a schematic diagram of step S206 of preparing the CMOS inverter shown in Figure 7;

Figure 12g shows a schematic diagram of step S207 of preparing the CMOS inverter shown in Figure 7;

Figure 12h shows a schematic diagram of step S208 of preparing the CMOS inverter shown in Figure 7;

Figure 12i shows a schematic diagram of step S209 of preparing the CMOS inverter shown in Figure 7;

Figure 13a shows a schematic diagram of step S206 of preparing the CMOS inverter shown in Figure 9;

Figure 13b shows a schematic diagram of step S207 of preparing the CMOS inverter shown in Figure 9;

Figure 13c shows a schematic diagram of step S208 of preparing the CMOS inverter shown in Figure 9;

Figure 13d shows a schematic diagram of step S209 of preparing the CMOS inverter shown in Figure 9;

Figure 14a shows a schematic diagram of step S301 of preparing the CMOS inverter shown in Figure 10;

Figure 14b shows a schematic diagram of step S302 of preparing the CMOS inverter shown in Figure 10;

Figure 14c shows a schematic diagram of step S303 of preparing the CMOS inverter shown in Figure 10;

Figure 14d shows a schematic diagram of step S304 of preparing the CMOS inverter shown in Figure 10;

Figure 14e shows a schematic diagram of step S305 of preparing the CMOS inverter shown in Figure 10;

Figure 14f shows a schematic diagram of step S306 of preparing the CMOS inverter shown in Figure 10;

Figure 14g shows a schematic diagram of step S307 of preparing the CMOS inverter shown in Figure 10;

Figure 14h shows a schematic diagram of step S308 of preparing the CMOS inverter shown in Figure 10;

Figure 15 shows a schematic diagram of a memory provided by an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be described in further detail below in conjunction with the accompanying drawings.

The components in the drawings of the embodiments of this application are only for showing the working principle of the CMOS inverter, and do not truly reflect the actual size relationship between each part and between the various directions of a certain part.

In addition, in this application, directional terms such as "up" and "perpendicular to the paper surface" are defined relative to the schematically placed directions of the components in the drawings. It should be understood that these directional terms are relative concepts. Relative descriptions and clarifications are used, which may vary accordingly depending on the orientation in which components are placed in the drawings.

In order to facilitate understanding of the CMOS inverter provided in the embodiment of the present application, its application scenarios are briefly described below.

The CMOS inverter can be used in the peripheral circuit of the memory to invert the phase of the input signal by 180 degrees. Specifically, it can be used in the subsequent processes of the memory, but it can also be used in other processes or other electronics other than the memory. module’s integrated circuit. Specifically, its existence form in the integrated circuit may be in the form of array arrangement.

If a three-dimensional CMOS inverter uses LTPO as the conductive channel, since its p-type conductive channel and n-type conductive channel are both planar structures, it will occupy a large planar area and have low space utilization; alternatively, silicon In the technical solution of using nanowires as conductive channels, due to the self-doping effect of metal, it is impossible to prepare efficient and stable NMOS transistors, and it is difficult to realize low-power CMOS logic devices.

In order to solve the above problems, embodiments of the present application provide the following technical solutions.

In order to illustrate the implementation principle of a CMOS inverter, FIG. 1 shows a circuit diagram of a CMOS inverter provided by an embodiment of the present application. Please refer to Figure 1. PMOS 01 and NMOS 02 share a common gate 101 and a common drain 102, but the common gate 101 can be an integrated electrode, or it can include two or more independent electrodes. Each electrode is shared by PMOS 01 and NMOS 02 respectively, and the common gate 101 can be made of metal material or other conductive materials. The input voltage of the common gate 101 is V _in , the output voltage of the common drain 102 is V _out , the first source 103 of the NMOS 02 is connected to the ground GND, that is, connected to the low level V _ss , and the second source 104 of the PMOS 01 Access high level V _dd . When V _in is connected to the high level, NMOS 02 is in the on state, and PMOS 01 is in the off state. Therefore, V _out is at the same potential as the ground GND, and the common drain 102 outputs the ground voltage, that is, the low level V _ss ; when V _in When the low level is connected, NMOS 02 is in the off state, while PMOS 01 is in the on state. Therefore, V _out has the same potential as the high level V _dd , and the common drain 102 outputs the high level V _dd .

Figure 2 shows a perspective view of a CMOS inverter provided by an embodiment of the present application. Figure 3 shows a top view of the CMOS inverter shown in Figure 2. Figure 4 shows a cross-sectional view of the support part in Figure 1. The cross-sectional position can be At AA or BB, the cross-sectional view of the support shown in Figure 4 can be formed. Referring to FIGS. 2 to 4 together, the CMOS inverter provided by the embodiment of the present application includes a substrate 10 and a support portion 20 formed on the substrate 10 . The support portion 20 has oppositely arranged first vertical sidewalls P1 and The second vertical side wall P2, and the top wall P3 connecting the first vertical side wall P1 and the second vertical side wall P2 and located on the side of the support part 20 away from the substrate 10, the meaning of "vertical side wall" refers to The sidewalls extend perpendicular to the direction of the substrate 10, but there may be engineering tolerances. The surface of the first vertical sidewall P1 is a plane perpendicular to the substrate, but the so-called "plane" may not be an absolute plane, but allows for errors that may occur in the process. A plurality of second trenches U2 are formed on the second vertical sidewall P2 and are spaced apart in a direction perpendicular to the substrate 10 . Each second trench U2 extends in a direction perpendicular to the paper surface in FIG. 4 . The direction is parallel to the substrate 10, and the opening is located on the surface of the second vertical sidewall P2.

Specifically, the second trench U2 can be formed through the following structure. The support part 20 includes multiple layers of first insulating dielectric layers 21 and multiple layers of second insulating dielectric layers 22 that are alternately stacked on the substrate 10 along a vertical direction. The “vertical direction” in the embodiment of this application refers to the vertical direction perpendicular to the substrate 10 . In the direction of bottom 10, the "vertical" here may have engineering allowable errors. A specific structure of the support part 20 may be as follows. The support part 20 includes three first insulating dielectric layers 21. A second insulating dielectric layer 22 is provided between each two adjacent first insulating dielectric layers 21. The lowest layer is The first insulating dielectric layer 21 is formed on the substrate 10 .

In the support part 20, each first insulating dielectric layer 21 has opposite vertical side surfaces 21a and 21b, and each second insulating dielectric layer 22 has opposite vertical side surfaces 22a and 22b. The so-called “vertical side surfaces” The meanings all refer to the side surfaces extending in a direction perpendicular to the substrate 10 , and there may be engineering allowable errors. Among them, on the side of the first vertical side wall P1, the vertical side 21a and the vertical side 22a are arranged on the same side and are flush with each other, so that the surface of the first vertical side wall P1 is a plane; on the side of the second vertical side wall P1, the vertical side 21a and the vertical side 22a are arranged on the same side and are flush with each other. The side surface 21b and the vertical side surface 22b are arranged on the same side, and the vertical side surface 22b is lower than the vertical side surface 21b, so as to be concave and cooperate with the first insulating dielectric layer 21 on adjacent sides to form a second trench U2, so that in the second The surface of the vertical side wall P2 forms a plurality of second grooves U2 arranged at intervals. The second insulating dielectric layer 22 and the first insulating dielectric layer 21 can be made of different materials. For example, the hardness of the second insulating dielectric layer 22 is smaller than the hardness of the first insulating dielectric layer 21 to facilitate selective etching by wet methods. When the second vertical sidewall P2 is processed by the etching method, the vertical side 22b of the second insulating dielectric layer 22 is etched faster than the vertical side 21b of the first insulating dielectric layer 21, that is, the etching selectivity of the second insulating dielectric layer 22 is is greater than the etching selectivity ratio of the first insulating dielectric layer 21 to form the above-mentioned second trench U2. The material of the first insulating dielectric layer 21 can be selected from SiOx, SiNx, AlOx, SiON and SiNC and other insulating dielectric layers. The thickness size is between 5nm and 200nm, such as 5nm, 10nm, 30nm, 50nm, 90nm, 100nm, 130nm, 150nm. , 180nm and 200nm, etc.; the material of the second insulating dielectric layer 22 can be selected from among the insulating dielectric layers such as SiOx, SiNx, AlOx, SiON and SiNC, which has a higher etching selection than the first insulating dielectric layer 21, and the thickness size is between Between 5nm and 200nm, such as 5nm, 10nm, 30nm, 50nm, 90nm, 100nm, 130nm, 150nm, 180nm and 200nm, etc.

It should be understood that the number of the first insulating dielectric layer 21 and the second insulating dielectric layer 22 is not limited to the above number, as long as the first insulating dielectric layer 21 and the second insulating dielectric layer 22 are both multi-layered (the so-called " "Multi-layer" refers to the situation of greater than or equal to two layers, such as three layers, four layers, five layers, six layers, seven layers, etc.), and they can be stacked alternately in sequence, but the second insulating dielectric layer 22 should be at least two layers. , the first insulating dielectric layer 21 may have one more layer than the second insulating dielectric layer 22 . At the same time, the formation of the second trench U2 is not limited to the above-mentioned method of alternately stacking insulating dielectric layers of different materials and selective wet etching, as long as the second trench in the above shape can be formed on the surface of the second vertical sidewall P2 U2 is enough.

With reference to FIGS. 2 to 4 , the CMOS inverter includes a first channel structure 107 and a second channel structure 106 . The first channel structure 107 is a thin film structure and extends along the surface of the first vertical sidewall P1. Specifically, it can extend vertically from the substrate 10 to the vertical side 21a of the first insulating dielectric layer 21 on the top layer without additional When the height of the support portion 20 is increased, the effective channel width of the first channel structure 107 is sufficiently increased to increase the on-current of the device; however, it should also be understood that the first channel structure 107 can also only cover the first vertical sidewall P1 part of the surface. The film thickness of the first channel structure 107 may be between 2nm and 50um, such as 2nm, 5nm, 10nm, 20nm, 50nm, 100nm, 500nm, 1um, 10um, 30um, 40um, 50um, etc. The material of the first channel structure 107 is an n-type semiconductor channel material. The n-type semiconductor channel material can be an oxide semiconductor material, for example, Si, poly-Si, amorphous-Si and other silicon-based semiconductors, In ₂ O ₃ , ZnO, Ga ₂ O ₃ , ITO, TiO ₂ and other metal oxides, In-Ga-Zn-O (IGZO) and In-Sn-Zn-O (ISZO) and other multi-component compounds, or graphene, MoS ₂ and Two-dimensional semiconductor materials such as black phosphorus can be one of the above materials, or any combination of two or more of the above materials. Second channel structure 106 It includes multiple p-type nanowires. The p-type nanowires can be silicon nanowires, silicon-germanium nanowires or germanium nanowires. They can be one of the above materials or any combination of the above semiconductor materials. Specifically, the nanowires 106a and 106b in Figure 2 can be used. The number of the above-mentioned nanowires can also be more than two, such as three, four, five, six, etc., as the nanowires are spaced apart along the vertical direction. As the number increases, the channel width of the second channel structure 106 increases, and the number of nanowires corresponds to the plurality of second trenches U2 one-to-one. The plurality of nanowires are arranged one-to-one in the plurality of second trenches U2. In the second trench U2, for example, the nanowire 106a is disposed in the lower second trench U2 and extends along the length direction of the second trench U2. However, the nanowire 106a can also be only partially disposed in the second trench. In U2, it may also be completely located in the second trench U2, and the nanowire 106b is disposed in the upper second trench U2 in the same manner.

The first source electrode 103 and the second source electrode 104 are metal electrodes or electrodes made of other conductive materials, and are exemplarily in the shape of films. The thickness of the first source electrode 103 and the second source electrode 104 is between 20 nm and Between 300nm, such as 20nm, 50nm, 90nm, 150nm, 200nm, 250nm and 300nm, etc., metal materials or conductive materials can be used, such as TiN, Ti, Au, W, Mo, In-Ti-O (ITO), In - One of Zn-O (IZO), Al, Cu, Ru, Ag and Pt, or a combination of any two or more of them. The first source electrode 103 extends along the surface of the first channel structure 107 away from the support part 20 , and may partially extend to the top wall P3 of the support part 20 . The second source electrode 104 extends along the second vertical sidewall P2, and the portion corresponding to the second trench U2 extends along the inner wall of the second trench U2, and is connected with the nanowire 106a and the nanowire 106b in the second trench U2. Contact, where the material used to prepare the second source electrode 104 can also fill the second trench U2, as long as it ensures stable contact with the nanowires 106a and 106b therein; the second source electrode 104 can also be partially extended to the top wall P3, but an appropriate gap must be maintained between the first source electrode 103 and the second source electrode 104 to avoid mutual interference or even short circuit. The first source electrode 103 and the second source electrode 104 can be prepared in the same layer. The contact between the first source electrode 103 and the first channel structure 107, and the contact between the second source electrode 104 and the second channel structure 106 can all adopt ohmic contact to ensure a small contact resistance and facilitate the input of current. and output. The first source 103 is connected to the low level V _ss , and the second source 104 is connected to the high level V _dd .

An insulating layer with a thickness between 0.1nm and 2nm can be introduced at the interface between the first source 103 and the first channel structure 107. The specific thickness of the insulating layer can be 0.1nm, 0.2nm, 0.5nm, 0.8 nm, 1.0nm, 1.2nm, 1.4nm, 1.6nm, 1.8nm and 2nm, etc. The material of the insulating layer can be SiNx, SiOx, HfOx, AlOx, HAO, HZO, ZrOx, Si-doped HfOx and Si-doped HAO and other insulating media to form a semiconductor\insulation layer\metal structure, thereby helping to prevent the metal material of the first source 103 from diffusing in the contact area with the first channel structure 107 of the semiconductor material, thereby reducing the Fermi nail of the contact pricking effect. The above-mentioned insulating layer may also be introduced between the second source 104 and the second channel structure 106 .

Figure 6 shows the BB cross-sectional view of the CMOS inverter shown in Figure 1. Combining Figures 2, 3 and 6, the common drain 102 can also be in the form of a film, and its material and thickness can refer to the first source 103 and second source 104. The common drain 102 is disposed across the first vertical sidewall P1, the second vertical sidewall P2, and the third vertical sidewall P3 between them. The portion of the common drain electrode 102 corresponding to the first vertical side wall P1 extends along the surface of the first source electrode 103 away from the first vertical side wall P1; the portion of the common drain electrode 102 corresponding to the second vertical side wall P2 extends along the second vertical side wall P1. The vertical sidewall P2 extends, and the portion corresponding to the second trench U2 extends along the inner wall of the second trench U2 and is connected to the nanowire 106a and the nanowire 106b in the second trench U2 to form the common drain 102 The material can also fill the second trench U2; the middle part of the common drain 102 extends close to the top wall P3. Moreover, to ensure a small contact resistance, the common drain 102 is in ohmic contact with the first channel structure 107 and the second channel structure 106 respectively. In order to reduce the Fermi pinning effect of the contact, an insulating layer can also be introduced into the common drain 102 and the first channel structure 107 and the second channel structure 106 respectively. The thickness and material of the insulating layer can be referred to the first source electrode mentioned above. 103 is an insulating layer at the interface in contact with the first channel structure 107 .

In the above, the first channel structure 107 and the second channel structure 106 are electrically connected through the common drain 102 and connected to V _out . The common drain electrode 102 and the first source electrode 103 are spaced apart along the extension direction of the nanowire 106a, and are also spaced apart from the second source electrode 104 along the above-mentioned direction. The common drain electrode 102 can also be spaced apart from the first source electrode 103 and the second source electrode 104 respectively. The source electrode 104 is prepared in the same layer.

FIG. 5 shows a cross-sectional view AA of the CMOS inverter shown in FIG. 1 , combined with FIG. 2 , FIG. 3 and FIG. 5 . The CMOS inverter also includes a gate dielectric layer 105. The gate dielectric layer 105 includes an outer gate dielectric layer 105a. The common gate 101 includes an outer gate 101a. The outer gate 101a is in the shape of a film, and its material can be a metal material or other conductive material. Such as TiN, Ti, Au, W, Mo, ITO, IZO, Al, Cu, Ru, Ag and Pt, etc. It can also be any combination of two or more of the above materials. The thickness of the outer gate 101a ranges between 10nm and 300nm, such as 10nm, 20nm, 50nm, 90nm, 150nm, 200nm, 250nm and 300nm, etc. The gate dielectric layer 105 can be made of insulating materials, such as SiOx, SiNx, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , TiO ₂ and Y ₂ O ₃ , etc., or it can be a combination or stack of any two or more of the above materials. layer materials or combined laminated materials.

Along the extension direction of the nanowire 106a, the outer gate 101a and the outer gate dielectric layer 105a are located between the first source electrode 103 and the common drain electrode 102, and between the second source electrode 104 and the common drain electrode 102; the outer gate dielectric layer 105a extends along the surface of the first channel structure 107 away from the support portion 20, the top wall P3 and the second vertical sidewall P2, and the portion corresponding to the second trench U2 extends along the inner wall of the second trench U2, the outer gate 101a Extends along the surface of the outer gate dielectric layer 105a away from the support part 20, so that the outer gate 101a is located on the side of the first channel structure 107 away from the second channel structure 106, and the second channel structure 106 is away from the first channel One side of the structure 107, and are spaced apart from the first channel structure 107 and the second channel structure 106 (such as nanowires 106a and nanowires 106b) through the outer gate dielectric layer 105a, so as to realize that the outer gate 101a is respectively connected to the first channel structure 107 and the second channel structure 106. The electrical isolation of the channel structure 107 and the second channel structure 106 is used to control the on/off of the first channel structure 107 and the second channel structure 106, thereby controlling the common gate 101 to be connected to the first source 103 and the first source 103 respectively. The connection between the two sources 104.

In addition, the height of the support portion 20 in the vertical direction can also be increased to provide space for increasing the effective channel width of the first channel structure 107 and the second channel structure 106 in the vertical direction, thereby increasing the on-current of the device.

Among them, the outer gate 101a, the outer gate dielectric layer 105a, the first channel structure 107, the first source 103 and the common drain 102 form the first transistor (that is, NMOS 02). The outer gate 101a, the outer gate dielectric layer 105a, and the The two-channel structure 106, the second source electrode 104 and the common drain electrode 102 form a second transistor (ie, PMOS 01). How the outer gate 101a specifically controls the on-off of the first channel structure 107 and the second channel structure 106 will not be described in detail here. The basic principles of the switching of the first transistor and the second transistor can be referred to the common knowledge in the art.

In the above CMOS inverter, since the first channel structure 107 is in the shape of a film and extends along the surface of the first vertical sidewall P1, it only occupies the film thickness of the first channel structure 107 in the direction parallel to the substrate 10 size space, and the second channel structure 106 is distributed in the second trench U2 of the second vertical sidewall P2 in the form of nanowires, and does not occupy additional space outside the support part 20. Therefore, the above first channel structure The difficulty of the preparation process of 107 and the second channel structure 106 has not changed significantly, but it can realize the CMOS of heterogeneous integrated three-dimensional fork (back-to-back) structure while occupying a small space in the direction parallel to the substrate 10 device. Moreover, in this CMOS inverter, the first channel structure 107 in the NMOS 02 is prepared in the form of a thin film instead of in the form of a nanowire. In the process of preparing n-type nanowires, two materials with different carriers need to be doped simultaneously. The formed n-type nanowires have poor stability and poor performance. The process of preparing a thin film as the first channel structure 107 In this way, the above-mentioned repeated doping of different types of carriers can be avoided, and there is no self-doping effect of metal. The n-type film of the first channel structure 107 formed can exist stably and has good performance. However, the embodiment of the present application does not rule out the solution that the first channel structure 107 is a p-type channel material and the second channel structure 106 is an n-type nanowire, as long as the first channel structure 107 and the second channel structure 106 are ensured With opposing carrier classes The so-called "opposite carrier type" means that one uses electrons as majority carriers and the other uses holes as majority carriers to form n-type channels and p-type channels respectively. In addition, since there are both NMOS 02 and PMOS 01 in this CMOS inverter instead of only one single carrier type transistor, it is beneficial to reduce power consumption. The implementation method of this CMOS inverter is compatible with traditional microelectronics processes and can be applied to back-end processes of memory to achieve heterogeneous integration or stacked integration, effectively reducing costs. This structure can also be applied to the peripheral circuit of the dynamic random access memory through appropriate circuit connections to reduce the circuit area occupied.

In addition, based on the corresponding embodiment of FIG. 2, the following modifications can be made: the second channel structure 106 is also replaced with a thin film structure like the first channel structure 107, and the second vertical sidewall P2 is also a plane, and the second channel structure 106 is also replaced with a thin film structure like the first channel structure 107. The channel structure 106 extends along the surface of the second vertical sidewall P2 and may be symmetrical with the first channel structure 107. Alternatively, the second vertical sidewall P2 still retains the second trench U2, and the second channel structure 106 is consistent with the second trench structure 107. The corresponding part of the trench U2 extends along the inner wall of the second trench U2 to improve the gate control capability of the second channel structure 106. As long as it is ensured that at least part of the second channel structure 106 is located in the second trench U2, all Helps reduce occupied area.

Figure 7 shows a perspective view of another CMOS inverter provided by an embodiment of the present application. Figure 8 shows a cross-sectional view of A-A of the support portion of the CMOS inverter shown in Figure 7. Refer to Figures 7 and 8, and Figure Compared with the corresponding embodiments 2 to 6, the CMOS inverter shown in Figure 7 has the following differences: the vertical side surface 22a of the second insulating dielectric layer 22 is also lower than the vertical side surface 21a of the adjacent first insulating dielectric layer 21, The first trench U1 is recessed and surrounded by the first insulating dielectric layer 21 on both sides. The number of the first trench U1 can be one-to-one with the number of the second trench U2, and each first trench U1 may have the same height as the second trench U2, but the depth may be different or the same. The portion of the first channel structure 107 corresponding to the first trench U1 is recessed into the first trench U1 to form a groove along the first trench U1. The inner wall of one trench U1 is extended, thereby increasing the extension size of the first trench U1 in the vertical direction without increasing the height of the support portion 20, thereby increasing the effective channel width. Correspondingly, the common drain electrode 102, the first source electrode 103, the outer gate 101a and the outer gate dielectric layer 105a all undergo corresponding deformation as the first channel structure 107 is recessed due to the first trench U1. The part of the common drain 102 and the outer gate dielectric layer 105a corresponding to the first trench U1 extends close to the first channel structure 107, which is equivalent to increasing the area of the outer gate 101a facing the first channel structure 107, improving the sensitivity to the first channel structure 107. The gate control capability of a channel structure 107. The common gate 101 also includes an inner gate 101b (also called a back gate electrode). The gate dielectric layer 105 also includes an inner gate dielectric layer 105b. The inner gate 101b is in the form of a film and is located between the first channel structure 107 and the support part 20 between, and between the second channel structure 106 (such as the nanowires 106a and the nanowires 106b) and the support part 20, and is arranged in contact with the surface of the support part 20, specifically in contact with the first vertical sidewall P1, the second vertical sidewall P1, and the second vertical sidewall P1. The sidewall P2 and the top wall P3 extend, and the portions corresponding to the first trench U1 and the second trench U2 extend along the inner walls of the two trenches, and the inner gate dielectric layer 105b extends along the surface of the inner gate 101b away from the support portion 20, The inner gate 101b is spaced apart from the first channel structure 107 and the second channel structure 106 respectively through the inner gate dielectric layer 105b. In the above structure, the inner gate 101b is located between the first channel structure 107 and the second channel structure 106, and is electrically isolated from the first channel structure 107 and the second channel structure 106 respectively by the inner gate dielectric layer 105b. , to increase the gate control capability of the first channel structure 107 and the second channel structure 106 . In addition, since the inner gate 101b also undergoes concave deformation at the first trench U1 along with the first channel structure 107, the area opposite the first channel structure 107 also increases, thereby improving the impact on the first channel structure 107. Gate control capability. In addition, the outer gate 101a and the inner gate 101b can be electrically connected by etching the portion of the inner gate dielectric layer 105b corresponding to the top wall P3 to form a hollow U3, and then depositing a connection layer F of metal or other conductive material in the hollow U3. , forming a full gate structure, this process will not significantly increase the difficulty, can be highly practical, and further improve gate control capabilities. Of course, the outer gate 101a and the inner gate 101b may not be connected and remain independent of each other, so that the first channel structure 107 and the second channel structure 106 are gated through the outer gate 101a and the inner gate 101b respectively.

It should be understood that the embodiment corresponding to FIG. 7 may have the following modifications: for the common gate 101, only the The inner gate 101b or only the outer gate 101a remains; the first vertical side wall P1 and the second vertical side wall P2 maintain the form of the plane in FIG. 2; the entire support part 20 is used as the inner gate 101b.

Figure 9 shows a modified structure of the CMOS inverter shown in Figure 7. The difference between the CMOS inverter shown in Figure 9 and the CMOS inverter shown in Figure 7 is that the inner gate dielectric layer 105b is divided into different The first part 105b' and the second part 105b" are made of material, the first part 105b' is located between the first channel structure 107 and the inner gate 101b to correspond to the first channel structure 107, and the second part 105b" is located Between the second channel structure 106 and the inner gate 101b, corresponding to the second channel structure 106, a CMOS inverter with different gate dielectrics is formed to respectively adjust the threshold voltages of the NMOS 02 and the PMOS 01, and adjust the voltages of the two transistors. Symmetry, optimizes the performance of CMOS inverters and reduces power consumption. As mentioned above, the first part 105b' and the second part 105b" can be prepared by region-by-region doping or region-by-region deposition. The material selection of the two can refer to the material selection of the gate dielectric layer 105 mentioned above, and different materials can be selected according to specific needs. That's it. The part of the inner gate 101b located on the top wall P3 can be etched away, so that the part located on the first vertical sidewall P1 (corresponding to the first part 105b') and the part located on the second vertical sidewall P2 (corresponding to the first part 105b') can be etched away. The two parts (corresponding to 105b") are electrically isolated from each other and provide different gate voltages to further adjust the symmetry of the two transistors.

Figure 10 shows a perspective view of another CMOS inverter provided by the embodiment of the present application. Refer to Figure 10: the support part 20 is made of metal material or other conductive materials and serves as the inner gate 101b of the CMOS inverter. Its specific material Reference may be made to the materials of the outer grid 101a and the inner grid 101b in the previous embodiments. The surfaces of the first vertical side wall P1 and the second vertical side wall P2 that are oppositely arranged in the support part 20 are both flat. Moreover, the inner gate dielectric layer 105b covers the first vertical sidewall P1, the second vertical sidewall P2 and the top wall P3 of the support part 20, the first channel structure 107 and the second channel structure 106 are both thin films, and, A channel structure 107 extends along the surface of the portion of the inner gate dielectric layer 105b corresponding to the first vertical sidewall P1, and the second channel structure 106 extends along the surface of the portion of the inner gate dielectric layer 105b corresponding to the second vertical sidewall P2. , so as to utilize the inner gate dielectric layer 105b to electrically isolate the inner gate 101b from the first channel structure 107 and the second channel structure 106 respectively. The first source electrode 103 extends along the surface of the vertical portion of the first channel structure 107 away from the support portion 20 , and the second source electrode 104 extends along the surface of the vertical portion of the second channel structure 106 away from the support portion 20 . The common drain electrode 102 is spaced apart from the first source electrode 103 and the second source electrode 104 respectively, and extends from the surface of the vertical portion of the first channel structure 107 and the surface of the vertical portion of the second channel structure 106 . The above structure forms a CMOS inverter with a back-gate structure. The first channel structure 107 and the second channel structure 106 are both formed by deposition at the vertical sidewalls on both sides of the inner gate 101b, which is beneficial to reducing the size of the CMOS inverter in the direction parallel to the substrate 10. Improve space utilization.

However, it should be understood that the CMOS inverter shown in Figure 10 can also have the following modifications: add an outer gate 101a and an outer gate dielectric layer 105a, and the outer gate 101a is connected to the first channel structure through the outer gate dielectric layer 105a. 107 and the second channel structure 106 are electrically isolated, and the arrangement method can be referred to Figure 2; the first source electrode 103 and the common drain electrode 102 can also be arranged in the same layer as the first channel structure 107 and maintain contact to further reduce the level. direction (direction parallel to the substrate 10 ), similarly, the second source electrode 104 and the common drain electrode 102 can also be disposed in the same layer as the second channel structure 106 and maintain contact.

The following is a description of the preparation process of the CMOS inverter in each of the above implementations; it should be noted that the dimensional proportions and some structural details of the drawings corresponding to the steps of the following preparation methods may be different from those in Figures 2 to 2 There are certain differences in the structural diagrams in 10, but the following method is only intended to schematically illustrate the preparation process of the CMOS inverter of the corresponding embodiment.

Hereinafter, the preparation steps of the CMOS inverter in the embodiment corresponding to FIG. 2 will be described.

Figure 11a shows a schematic diagram of step S101 of preparing the CMOS inverter shown in Figure 2.

Step S101: Referring to FIG. 11a, the first insulating dielectric layer 21 and the second insulating dielectric layer 22 are alternately deposited on the substrate 10 to form a stacked thin film structure.

Figure 11b shows a schematic diagram of step S102 of preparing the CMOS inverter shown in Figure 2.

Step S102: Referring to FIG. 11b, etch the stacked film structure to form a plurality of first grooves T1 arranged at intervals and penetrating to the substrate 10. The two opposite side walls of each first groove T1 form adjacent The first vertical sidewall P1 of the two CMOS inverters.

Figure 11c shows a schematic diagram of step S103 of preparing the CMOS inverter shown in Figure 2.

Step S103: Referring to Figure 11c, deposit n-type active material through ALD (Atomic Layer Deposition) and other technologies, and use dry etching to remove the n-type active material on the upper surface of the stacked film structure, leaving the third Film-like n-type active layers are formed on the two first vertical sidewalls P1 of a groove T1 to form first channel structures 107 respectively.

Figure 11d shows a schematic diagram of step S104 of preparing the CMOS inverter shown in Figure 2.

Step S104: Referring to FIG. 11d, deposit the first protective layer 110. The first protective layer 110 fills the first groove T1 to protect the first channel structure 107 and the first vertical side P1 in subsequent steps. A protective layer 110 may also cover the upper surface of the laminated film structure.

FIG. 11e shows a schematic diagram of step S105 of preparing the CMOS inverter shown in FIG. 2 .

Step S105: Referring to FIG. 11e, use dry etching to etch the stacked film structure to form a second groove T2 that penetrates to the substrate 10 at intervals between each two adjacent first grooves T1. Two opposite side walls of each second groove T2 respectively form second vertical side walls P2 of two adjacent CMOS inverters. The portion of the laminated film structure between the adjacent first groove T1 and the second groove T2 forms a supporting portion 20 .

Figure 11f shows a schematic diagram of step S106 of preparing the CMOS inverter shown in Figure 2.

Step S106: Referring to FIG. 11f, use a wet selective etching method to selectively form the second insulating dielectric layer 22 on the two second vertical sidewalls P2 of the second groove T2, respectively forming second trenches with a certain depth. U2.

Figure 11g shows a schematic diagram of step S107 of preparing the CMOS inverter shown in Figure 2.

Step S107: Referring to Figure 11g, p-type nanowires (nanowires 106a and nanowires 106b) are self-assembled and grown in the second trench U2, and the nanowires 106a and 106b grow along the inner wall of the corresponding second trench U2. Among them, the material of the p-type nanowire refers to the description of the corresponding embodiment in Figure 2. Taking silicon nanowires as an example, the preparation process is: first prepare indium nanoparticles on the inner wall of the second trench U2, and then cover the inner wall surface A layer of amorphous silicon is added, and the entire structure is heated to above 300°C. The indium nanoparticles are activated and absorb the amorphous silicon, thereby growing crystalline silicon nanowires; during the growth process, the indium nanoparticles move along the second trench. The length direction of U2 moves to grow silicon nanowires extending along the length direction of the second trench U2; in the above process, due to the doping effect of indium, the silicon nanowires grown are p-type silicon nanowires.

Figure 11h shows a schematic diagram of step S108 of preparing the CMOS inverter shown in Figure 2.

Step S108: Referring to FIG. 11h, remove the first protective layer 110 to expose the first channel structure 107, and deposit a metal material (or other conductive material) to form a groove along the first channel structure 107 in the first groove T1. The first source electrode 103 extending on the surface forms a second source electrode 104 connected to the p-type nanowires 106a and 106b in the second groove T2. The first source electrode 103 and the second source electrode 104 have a certain gap at the upper surface of the laminated film structure. Moreover, two adjacent CMOS inverters may share a first source electrode 103. Therefore, the first source electrode 103 is not in a film shape, but fills the first groove T1. Two adjacent CMOS inverters may share a second source 104. Therefore, the two second vertical sidewalls P2 of the second groove T2 are connected to each other at the bottom of the groove, and the second source 104 has The thickness is sufficient to fill the second trench U2 completely and with the nanowires 106a and 106b therein.

It should be noted that the above process does not describe how to prepare the common drain 102, the outer gate dielectric layer 105a, and the outer gate 101a. Before step S108, the outer gate dielectric layer 105a and the outer gate 101a can be sequentially deposited on the support part 20, and then the common drain 102 and the first source are simultaneously prepared on both sides of the outer gate 101a in step S108. 103 and second source 104.

Hereinafter, the preparation steps of the CMOS inverter in the embodiment corresponding to FIG. 7 will be described.

Figure 12a shows a schematic diagram of step S201 of preparing the CMOS inverter shown in Figure 7.

Step S201: Referring to FIG. 12a, the first insulating dielectric layer 21 and the second insulating dielectric layer 22 are alternately deposited on the substrate 10 to form a stacked thin film structure.

FIG. 12b shows a schematic diagram of step S202 of preparing the CMOS inverter shown in FIG. 7 .

Step S202: Referring to FIG. 12b, use a dry etching method to etch the laminated film structure to form a plurality of first grooves T1 arranged at intervals and penetrating to the substrate 10. Between each two adjacent first grooves T1 A second groove T2 is formed between them and penetrates to the substrate 10. The two opposite side walls of each first groove T1 respectively form the first vertical side walls P1 of two adjacent CMOS inverters. Each second The two opposite side walls of the groove T2 respectively form the second vertical side walls P2 of two adjacent CMOS inverters. And use a wet selective etching method to selectively etch the second insulating dielectric layer on the two second vertical sidewalls P2 of the second groove T2 and the two first vertical sidewalls P1 of the first groove T1. 22, respectively form a groove U1 on the first vertical side wall P1, and form a second groove U2 on the second vertical side wall P2.

FIG. 12c shows a schematic diagram of step S203 of preparing the CMOS inverter shown in FIG. 7 .

Step S203: Referring to Figure 12c, deposit a conductive film (can be metal or other conductive material) on the surface of the laminated film structure through ALD and other technologies, and the conductive film covers each first vertical side wall P1 and the first trench thereon The inner wall of the trench U1, as well as the second vertical sidewall P2 and the inner wall of the second trench U2 above it serve as the inner gate 101b. Part of the conductive film on the upper surface of the stacked film structure can also be removed by dry etching, so that the inner gate 101b of each CMOS inverter is divided into two parts, respectively for the first channel structure 107 and the second channel structure. 106 for gate control.

Figure 12d shows a schematic diagram of step S204 of preparing the CMOS inverter shown in Figure 7.

Step S204: Referring to Figure 12d, deposit an inner gate dielectric layer 105b on the laminated film structure through ALD or other techniques. The inner gate dielectric layer 105b covers the surface of the inner gate 101b. If part of the conductive film on the upper surface of the laminated film structure is etched away, then the corresponding part of the inner gate dielectric layer 105b directly covers the upper surface of the stacked film structure.

Figure 12e shows a schematic diagram of step S205 of preparing the CMOS inverter shown in Figure 7.

Step S205: Referring to FIG. 12e, use a mask protection method to deposit a second protective layer 109 on the second groove T2 and the second trench U2 therein. The second protective layer 109 may cover part of the upper surface of the laminated film structure located on both sides of the second groove T2.

Figure 12f shows a schematic diagram of step S206 of preparing the CMOS inverter shown in Figure 7.

Step S206: Referring to Figure 12f, deposit n-type active material through ALD and other technologies, and use dry etching to remove the n-type active material on the upper surface of the stacked film structure, leaving the two first grooves T1 The vertical sidewall P1 and the film-like n-type active layer on the inner wall of the first trench U1 form the first channel structure 107 respectively.

Figure 12g shows a schematic diagram of step S207 of preparing the CMOS inverter shown in Figure 7.

Step S207: Referring to FIG. 12g, remove the second groove T2 and the second trench U2 therein and deposit the second protective layer 109, and deposit the first protection layer 109 on the first groove T1 and the first trench U1 therein. Layer 110.

Figure 12h shows a schematic diagram of step S208 of preparing the CMOS inverter shown in Figure 7.

Step S208: Referring to Figure 12h, p-type nanowires (nanowires 106a and nanowires 106b) are self-assembled and grown in the second trench U2, and the nanowires 106a and 106b grow along the inner wall of the corresponding second trench U2. For the specific preparation process of nanowires, please refer to the previous step S107.

Figure 12i shows a schematic diagram of step S209 of preparing the CMOS inverter shown in Figure 7.

Step S209: Referring to Figure 12i, remove the first protective layer 110 to expose the first channel structure 107, and deposit metal material (or other conductive material) to form the first source electrode 103 extending along the surface of the first channel structure 107 in the first groove T1, and to form a p-type nanowire (nanowire 106a) in the second groove T2. The second source electrode 104 is connected to the nanowire 106b). For the remaining description about the first source electrode 103 and the second source electrode 104, please refer to the previous step S108.

It should be noted that the above process does not describe how to prepare the common drain 102, the outer gate dielectric layer 105a and the outer gate 101a. Before step S209, the outer gate dielectric layer 105a and the outer gate 101a can be sequentially deposited on the support part 20, and then the common drain 102 and the first source are simultaneously prepared on both sides of the outer gate 101a in step S209. 103 and the second source 104.

Hereinafter, the preparation method of the CMOS inverter in the embodiment corresponding to FIG. 9 will be described. The difference between this preparation method and the preparation method of the CMOS inverter in the embodiment corresponding to Figure 7 is:

In step S206, FIG. 13a shows a schematic diagram of step S206 of preparing the CMOS inverter shown in FIG. 9. Referring to FIG. 13a, before depositing the n-type active layer, the second protective layer 109 is not exposed in the inward gate dielectric layer 105b. The covered area is ion implanted to convert into the first portion 105b'.

In step S207, Figure 13b shows a schematic diagram of step S207 of preparing the CMOS inverter shown in Figure 9. Referring to Figure 13b, when the first protective layer 110 is formed, the first protective layer 110 covers the first portion 105b'.

In step S208, FIG. 13c shows a schematic diagram of step S208 of preparing the CMOS inverter shown in FIG. 9. Referring to FIG. 13c, ion implantation is performed into the area of the inner gate dielectric layer 105b that is not covered by the first protective layer 110 to convert into Part II 105b".

Figure 13d shows a schematic diagram of step S209 of preparing the CMOS inverter shown in Figure 9. The structure finally formed in step 209 can be referred to Figure 13d.

Hereinafter, the preparation method of the CMOS inverter in the embodiment corresponding to FIG. 10 will be described.

Figure 14a shows a schematic diagram of step S301 of preparing the CMOS inverter shown in Figure 10.

Step S301: Referring to FIG. 14a, deposit a conductive material layer M (which can be a metal material or other conductive material) on the substrate 10.

Figure 14b shows a schematic diagram of step S302 of preparing the CMOS inverter shown in Figure 10.

Step S302: Referring to FIG. 14b, etch a plurality of first grooves T1 arranged at intervals and penetrating to the substrate 10. The two opposite sidewalls of the first groove T1 are used as the first grooves of adjacent CMOS inverters. Vertical side wall P1.

Figure 14c shows a schematic diagram of step S303 of preparing the CMOS inverter shown in Figure 10.

Step S303: Referring to Figure 14c, use ALD or other methods to deposit a first gate oxide dielectric layer 105s on the surface of the conductive material layer M. The first gate oxide dielectric layer 105s covers the upper surface of the conductive material layer M and the first groove T1. The first vertical side wall P1.

Figure 14d shows a schematic diagram of step S304 of preparing the CMOS inverter shown in Figure 10.

Step S304: Referring to Figure 14d, deposit an n-type active layer on the surface of the gate oxide dielectric layer 105s, and use dry etching to etch away the n-type active layer corresponding to the upper surface of the conductive material layer M, only A portion of the n-type active layer corresponding to the first vertical sidewall P1 is retained to form the first channel structure 107 .

Figure 14e shows a schematic diagram of step S305 of preparing the CMOS inverter shown in Figure 10.

Step S305: Referring to FIG. 14e, deposit the first protective layer 110 into the first groove T1. The first protective layer 110 can cover the portion of the gate oxide dielectric layer 105s located on the upper surface of the conductive material layer M. Using dry etching, a second groove T2 is etched between every two first grooves T1. The two opposite sidewalls of the second groove T2 are used as the third groove of the adjacent CMOS inverter. The two vertical sidewalls P2 and the portion between each adjacent first groove T1 and the second groove T2 in the conductive material layer M form the support portion 20 of the CMOS inverter (also the inner gate 101b).

Figure 14f shows a schematic diagram of step S306 of preparing the CMOS inverter shown in Figure 10.

Step S306: Referring to FIG. 14f, sequentially deposit and etch a gate oxide dielectric layer 105t and a thin-film p-type active layer on the inner wall of the second groove T2. The p-type active layer can also cover the first protective layer 110. the upper surface. The gate oxide dielectric layer 105t and the gate oxide dielectric layer 105s corresponding to each support part 20 form an inner gate dielectric layer 105b.

Figure 14g shows a schematic diagram of step S307 of preparing the CMOS inverter shown in Figure 10.

Step S307: Referring to FIG. 14g, dry etching is used to etch away the p-type active layer, the gate oxide dielectric layer 105t and the first protective layer 110 on the upper surface of the conductive material layer M.

Figure 14h shows a schematic diagram of step S308 of preparing the CMOS inverter shown in Figure 10.

Step S308: Referring to FIG. 14h, deposit a metal material (or other conductive material) to form a first source electrode 103 extending along the surface of the first channel structure 107 in the first groove T1, and in the second groove T2 A second source electrode 104 extending along the surface of the second channel structure 106 is formed. And at the same time, a common drain 102 is formed. The common drain 102 extends along the first channel structure 107 on the first vertical sidewall P1 and the second channel structure 106 on the second vertical sidewall P2 respectively, and the middle part is supported The surface of the inner gate dielectric layer 105b on the upper side of the portion 20.

The components in the drawings of the embodiments of this application are only for showing the working principle of the CMOS inverter, and do not truly reflect the actual size relationship of the components.

Based on the same inventive concept, embodiments of the present application provide a memory chip, which can be used in memories, such as dynamic random access memories. The memory chip includes: upstream devices, downstream devices, and the CMOS inverter provided in the above embodiments. Inverter, the CMOS inverter can be specifically located in the peripheral circuit, and the upstream device is electrically connected to the common gate 101 of the CMOS inverter. The upstream device can be a DRAM unit, a voltage regulator or other transistor structures, as long as the common gate can be 101 input voltage is enough, and the downstream device is electrically connected to the common drain 102, which can be a transistor structure. CMOS inverters can be specifically used in the back-end process of peripheral circuits of memories. Compared with using metal interconnections of planar structure transistors prepared in the front-end process to form CMOS inverters, it can produce greater cost advantages and increase space. utilization, which helps improve performance. For other beneficial effects, please refer to the previous CMOS inverter.

Based on the same inventive concept, the embodiment of the present application provides a memory. Figure 15 shows a schematic diagram of a memory provided by the embodiment of the present application. Referring to Figure 15, the memory 200 includes a circuit board 201 and the memory chip 202 provided in the above embodiment. The memory chip is disposed on the circuit board and is electrically connected to the circuit board 201. The circuit board 201 can be electrically connected to other modules through interfaces such as the gold finger 203. By utilizing the above memory chip, higher storage performance can be achieved, and for beneficial effects, reference can be made to the memory chip of the above embodiment.

Based on the same inventive concept, embodiments of the present application provide an electronic device. The electronic device can be a terminal device such as a mobile phone or a computer, or an intermediate-level electronic module such as a display panel and a motherboard. The electronic device includes: upstream devices and downstream devices. As well as the CMOS inverter provided in the above embodiment, the CMOS inverter can be specifically located in the peripheral circuit, and the upstream device is electrically connected to the common gate 101 of the CMOS inverter. The upstream device can be a DRAM unit, a voltage regulator or other The transistor structure is as long as the voltage can be input to the common gate 101. The downstream device is electrically connected to the common drain 102, and the downstream device can be other transistors. For its beneficial effects, please refer to the memory chip or CMOS inverter mentioned above.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present application, and all of them should be covered. within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

A CMOS inverter, characterized by comprising: a substrate, a support part, a first channel structure, a second channel structure, a first source, a second source, a common gate, a gate dielectric layer and a common a drain; wherein the first channel structure and the second channel structure have opposing carrier types;

The support portion is disposed on the substrate and has first vertical sidewalls and second vertical sidewalls that are oppositely arranged. The first channel structure is in the shape of a film and extends along the first vertical sidewall. , the second channel structure is disposed on the second vertical sidewall;

The common drain is electrically connected to the first channel structure and the second channel structure respectively, and the first source is electrically connected to the first channel structure and is spaced apart from the common drain. It is arranged that the second source electrode is electrically connected to the second channel structure and is spaced apart from the common drain electrode;

The common gate is spaced apart from the first channel structure and the second channel structure respectively through the gate dielectric layer for controlling the first channel structure and the second channel structure. On and off.
The CMOS inverter according to claim 1, wherein the surface of the first vertical side wall is a plane.
The CMOS inverter according to claim 1, wherein the first vertical sidewall has a plurality of first trenches spaced apart along the vertical direction;

The portion of the first channel structure corresponding to each first trench extends along the inner wall of the first trench.
The CMOS inverter according to claim 2 or 3, characterized in that the surface of the second vertical side wall is a plane, the second channel structure is in a film shape, and is formed along the second vertical side wall. surface extension.
The CMOS inverter according to claim 2 or 3, wherein the second vertical sidewall has a plurality of second trenches spaced apart along the vertical direction, and at least part of the second channel structure is distributed in each of the second trenches.
The CMOS inverter according to claim 5, wherein the second channel structure includes a plurality of nanowires, and the plurality of nanowires are at least partially disposed in the plurality of second trenches on a one-to-one basis. inside the tank.
The CMOS inverter according to claim 6, wherein the first channel structure is made of n-type semiconductor channel material, and each nanowire in the second channel structure is p-type. Nanowires.
The CMOS inverter according to claim 5, wherein the second channel is in the shape of a film and extends along the second vertical sidewall, and a portion corresponding to each second trench Extend along the inner wall of the second groove.
The CMOS inverter according to claim 5, wherein when the second vertical sidewall has a plurality of first trenches spaced apart along the vertical direction, the plurality of first trenches and the The plurality of second grooves are one-to-one;

The support part includes a plurality of first insulating dielectric layers and a plurality of second insulating dielectric layers alternately stacked on the substrate along a vertical direction, and the second insulating dielectric layer and the first insulating dielectric layer are made of different materials. material made of;

The two vertical sides of each second insulating dielectric layer and the first insulating dielectric layers on both sides in the vertical direction respectively form the first trench and the second trench.
The CMOS inverter according to claim 5, wherein when the surface of the first vertical sidewall is planar, the support portion includes a plurality of layers of first layers alternately stacked on the substrate along a vertical direction. An insulating dielectric layer and a plurality of second insulating dielectric layers, the second insulating dielectric layer and the first insulating dielectric layer being made of different materials;

A vertical side of each second insulating dielectric layer and the first insulating dielectric layers on both sides in the vertical direction form a first trench.
The CMOS inverter according to any one of claims 1 to 10, wherein the common gate includes an inner gate, the gate dielectric layer includes an inner gate dielectric layer, and the inner gate is located on the first between the channel structure and the second channel structure, and spaced apart from the first channel structure and the second channel structure respectively by the inner gate dielectric layer; and/or,

The common gate includes an outer gate, the gate dielectric layer includes an outer gate dielectric layer, the outer gate is located on a side of the first channel structure away from the second channel structure, and the second A side of the channel structure is away from the first channel structure and is spaced apart from the first channel structure and the second channel structure respectively through the outer gate dielectric layer.
The CMOS inverter according to claim 11, wherein when the common gate includes both the inner gate and the outer gate, the inner gate is electrically connected to the outer gate.
The CMOS inverter according to claim 11, wherein when the surface of the first vertical sidewall and the surface of the second vertical sidewall are both planar, the inner gate is disposed on the liner. on the bottom to form the support part.
The CMOS inverter according to claim 11, wherein the inner gate is in the shape of a film and is located between the first channel structure and the support portion; and/or,

The outer gate is in the shape of a film and is located on a side of the first channel structure away from the support portion.
The CMOS inverter according to claim 14, wherein the inner gate dielectric layer includes a first part and a second part, the first part corresponds to the first channel structure, and the second part corresponds to The second channel structure corresponds, and the first part and the second part are made of different materials.
The CMOS inverter of claim 15, wherein the inner gate is electrically isolated from corresponding parts of the first part and the second part respectively.
A memory chip, characterized in that it includes: an upstream device, a downstream device and the CMOS inverter according to any one of claims 1 to 16, the upstream device is electrically connected to the common gate, and the downstream device electrically connected to the common drain.
A memory, characterized by comprising: a circuit board and the memory chip of claim 17, the memory chip being disposed on the circuit board and electrically connected to the circuit board.
An electronic device, characterized in that it includes: an upstream device, a downstream device and the CMOS inverter according to any one of claims 1 to 16, the upstream device is electrically connected to the common gate, and the downstream device electrically connected to the common drain.