CN117835693A

CN117835693A - Storage array, storage and electronic equipment

Info

Publication number: CN117835693A
Application number: CN202211182921.5A
Authority: CN
Inventors: 孙莹; 黄凯亮; 景蔚亮; 王正波; 廖恒
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-09-27
Filing date: 2022-09-27
Publication date: 2024-04-05
Also published as: WO2024066560A1

Abstract

The embodiment of the application provides a memory array, a memory and electronic equipment, relates to the technical field of memories, and can reduce the complexity and cost of a process for preparing the memory. The memory array includes a plurality of memory layers formed on a substrate, the plurality of memory layers being stacked in a direction perpendicular to the substrate; each storage layer comprises at least one storage unit, each storage unit comprises a first transistor and a second transistor which are of annular structures, the first transistor and the second transistor are arranged along the direction perpendicular to the substrate, wherein the first pole and the second pole of each transistor are distributed along the direction perpendicular to the substrate, and the channel layers of the first transistor and the second transistor are of annular structures and perpendicular to the substrate.

Description

Storage array, storage and electronic equipment

Technical Field

The present disclosure relates to the field of memory technologies, and in particular, to a memory array, a memory including the memory array, a method for forming the memory array, and an electronic device including the memory.

Background

The memory cell of the conventional dynamic random access memory (dynamic random access memory, DRAM) includes a transistor and a capacitor, which is called a single-tube single-capacitor (1transistor 1capacitor,1T1C) structure, and as the integrated circuit is continuously developed, the transistor is continuously miniaturized, which brings about unavoidable short channel effects such as an increase in leakage current, a decrease in mobility, and the like. Therefore, researchers propose a memory with a double-tube single-capacitor (2transistor 1capacitor,2T1C) structure, which can improve the problems caused by the segment channel effect and can realize the nanosecond read-write speed and the millisecond storage time.

The 2T0C structure memory based on the planar device needs to be subjected to multi-layer wiring, the preparation process is complex, the area utilization rate is low, and the memory array with high integration density is difficult to realize. Although the storage density can be increased by continuously vertically stacking, the number of required photomasks, the preparation cost and the period can be doubled every time one layer of devices is added, and the requirement on the alignment precision of photoetching is also increased along with the increase of the stacking layer number.

Disclosure of Invention

The embodiment of the application provides a memory array, a memory comprising the memory array, a forming method of the memory array and electronic equipment comprising the memory, so that the process difficulty and cost of a memory preparation process are reduced.

In order to achieve the above purpose, the embodiments of the present application adopt the following technical solutions:

in a first aspect, embodiments of the present application provide a memory array that may be used in a dynamic random access memory (dynamic random access memory, DRAM). The memory array includes a substrate and a plurality of memory layers formed on the substrate, the plurality of memory layers being stacked in a direction perpendicular to the substrate to increase a memory density; each memory layer includes at least one memory cell including a first transistor and a second transistor disposed in a direction perpendicular to the substrate, each of the first transistor and the second transistor including a gate electrode, a first pole, a second pole, and a channel layer, each of the gate electrode, the first pole, the second pole, and the channel layer of the first transistor and the second transistor being ring-shaped and perpendicular to the substrate.

The first pole and the second pole of the first transistor are distributed along the direction vertical to the substrate, the channel layer of the first transistor surrounds the grid electrode of the first transistor, and the first pole and the second pole of the first transistor distributed along the direction vertical to the substrate are connected; the channel layer of the second transistor surrounds the gate of the second transistor and connects the first and second poles of the second transistor distributed along the direction perpendicular to the substrate; the surface of the gate of the second transistor remote from the substrate is in contact with the second pole of the first transistor and can serve as a storage node for storing data and information.

In addition, the shape of the channel layer and the grid electrode of each transistor is annular, the channel layer and the grid electrode are arranged around the grid electrode, the channel layer and the grid electrode are sequentially formed in a mode of growing or depositing on the inner wall of an opening, and the size of the area of each pole, the channel layer and the like of each transistor can be adjusted by adjusting the size of the opening.

In one possible implementation, the gate of the first transistor is located on a side of the second pole remote from the substrate; the first pole of the first transistor is disposed around the gate. The first pole and the second pole distributed along the direction vertical to the substrate are of annular structures, so that the annular first pole and the annular second pole can be formed by etching holes after stacking materials of the first pole and the second pole in the direction vertical to the substrate, extra photomasks are not needed to be used for preparation, the number of photomasks needed to be used is reduced, and the preparation difficulty and cost are reduced.

In one possible implementation, the channel layer of the first transistor is in ohmic contact with the first and second poles of the first transistor; the channel layer of the first transistor comprises a first part, a second part and a third part; the first portion is located between the first pole of the first transistor and the gate of the first transistor; the third part is positioned between the second pole of the first transistor and the grid electrode of the first transistor; the second portion connects the first portion and the third portion.

In one possible implementation, the gate of the first transistor includes a first gate portion and a second gate portion connected, the first gate portion extending in parallel with the substrate, the second gate portion extending in perpendicular to the substrate; the first electrode of the first transistor is located at one side of the first gate part far away from the substrate, the gate of the first transistor comprises the first gate part with the extending direction parallel to the substrate, and the channel layer is arranged around the gate, so that the channel layer can form a concave structure around the outer side of the gate, the longer the first gate part of the gate extends, the deeper the depth of the concave structure formed by the channel layer is, and the larger the effective width of the channel layer is, so that the on-current of the first transistor is larger, and the read-write speed of the memory can be improved.

In one possible implementation manner, the first transistor includes a gate oxide dielectric layer, the gate oxide dielectric layer is located between a channel layer of the first transistor and a gate of the first transistor, the gate oxide dielectric layer of the first transistor separates the channel layer of the first transistor from the gate of the first transistor, the gate and the channel layer are both annular in shape, so that the gate oxide dielectric layer between the gate and the channel layer is also annular in structure, and a surrounding axis is perpendicular to the substrate, and therefore, the gate oxide dielectric layer can be formed by growing, depositing and the like on a side wall of the opening, the number of photomasks required to be used is reduced, and the preparation difficulty and cost are reduced.

In one possible implementation, the first transistor includes a conductive film layer disposed between the channel layer and the first pole of the first transistor and the second pole of the first transistor, so as to improve ohmic contact between the channel layer and the first pole and the second pole, and improve on-current of the transistor.

In one possible implementation, the gate, the first pole, and the second pole of the second transistor are ring-shaped, and the axis around is perpendicular to the substrate; the first pole and the second pole of the second transistor encircle the grid electrode of the second transistor, wherein the first pole of the second transistor is positioned at one side far away from the substrate, the second pole of the second transistor is positioned at one side close to the substrate, the second transistor is similar to the first transistor in structure, and is also a transistor with a vertical channel structure, wherein the first pole and the second pole are distributed along the direction vertical to the substrate, the first pole and the second pole encircle the grid electrode, the number of light covers required in the preparation process of the multilayer annular structure along the direction vertical to the substrate is less, the cost is lower, in addition, the structure of the first transistor of the second transistor is similar, the whole is of the annular multilayer structure, the first transistor and the second transistor can be prepared simultaneously in the preparation process without preparing one of the first transistor and the second transistor, and the complexity of the preparation process can be reduced.

In one possible implementation, the gate, the first pole, and the second pole of the second transistor are ring-shaped, and the axis around is perpendicular to the substrate; the grid electrode of the second transistor is positioned at one side of the second pole of the second transistor far away from the substrate; the first pole of the second transistor is disposed around the gate of the second transistor. The second transistor and the first transistor have the same structure, and the first transistor and the second transistor can be prepared simultaneously in the preparation process, so that the complexity of the preparation process can be reduced.

In one possible implementation, the channel layer of the second transistor includes a fourth portion, a fifth portion, and a sixth portion connected in sequence; the fourth part of the channel layer of the second transistor is positioned between the first electrode of the second transistor and the grid electrode of the second transistor, and the channel layer is arranged around the grid electrode, so that structures such as the channel layer, the grid electrode and the like can be formed by growing, depositing and the like on the inner wall of the opening in sequence.

In one possible implementation, the gate of the second transistor includes a third gate portion and a fourth gate portion connected; the extending direction of the third grid part is parallel to the substrate, and the extending direction of the fourth grid part is perpendicular to the substrate; the first electrode of the second transistor is positioned at one side of the third grid part far away from the substrate; the second pole of the second transistor is located at one side of the third gate part facing the substrate, so that the third gate part of the gate separates the first pole from the second pole of the second transistor in the direction perpendicular to the substrate, the channel layer of the second transistor is arranged around the gate, so that the channel layer can form a concave structure around the third gate part, the longer the third gate part extends, the deeper the depth of the concave structure, the larger the effective width of the channel layer, and therefore the on-current of the second transistor is larger, and the read-write speed of the memory can be improved.

In one possible implementation, the second transistor includes a gate oxide dielectric layer, and the channel layer of the second transistor, the gate oxide dielectric layer of the second transistor, and the gate of the second transistor are disposed along a direction parallel to the substrate; the gate oxide dielectric layer of the second transistor separates the channel layer of the second transistor from the gate of the second transistor.

In one possible implementation, the second transistor includes a conductive film layer disposed between the channel layer of the second transistor and the first pole of the second transistor, the second pole of the second transistor, to thereby improve ohmic contact.

In one possible implementation, each memory layer further includes a write word line, a write bit line, a read word line, and a read bit line; the gate of the first transistor is connected with the write word line, the first pole of the first transistor is connected with the write bit line, the second pole of the first transistor is connected with the gate of the second transistor, the first pole of the second transistor is connected with the read word line, and the second pole of the second transistor is connected with the read bit line.

In one possible implementation, the write word line is located on a side of the first transistor away from the substrate, and a surface of the gate of the first transistor away from the substrate is in contact with the write word line; the position of the film layer of the write bit line in the direction perpendicular to the substrate is positioned on the same layer as the first pole of the first transistor; the film layer position of the read word line in the direction perpendicular to the substrate is positioned on the same layer as the first electrode of the second transistor; the read bit line is located in the same layer as the second pole of the second transistor in a direction perpendicular to the substrate.

In one possible implementation, the storage layer includes a plurality of storage units; the write word line and the read word line extend along a first direction parallel to the substrate; the writing bit line and the reading bit line extend along a second direction parallel to the substrate; the writing wire is electrically connected with the grid electrodes of the first transistors of the memory cells positioned in the first direction; the write bit line is electrically connected with first poles of first transistors of a plurality of memory cells positioned in a second direction; the read word line is electrically connected with first poles of second transistors of a plurality of memory cells positioned in a first direction; the read bit line is electrically connected to a second pole of a second transistor of the plurality of memory cells located in a second direction.

In one possible implementation, the write bit line is integral with the first pole of the first transistor; the read word line is integrally arranged with the first pole of the second transistor; the read bit line is integral with the second pole of the second transistor.

In a second aspect, the present application further provides a memory, where the memory includes a controller and a memory array in any of the foregoing implementations, the controller is electrically connected to the memory array, and the controller is configured to control reading and writing of the memory array. In the memory provided by the application, the memory array in the implementation manner is included, and in the memory array, the first transistor and the second transistor are arranged along the direction vertical to the substrate, so that the memory cells with the structure can be stacked along the direction vertical to the substrate to increase the memory density, improve the memory capacity, and the number of required photomasks can be reduced by the memory cells with the vertical structure, and the preparation cost is reduced.

In a third aspect, an embodiment of the present application further provides a method for manufacturing a memory, where the method includes: forming a second electrode of the second transistor, a first electrode of the second transistor, a second electrode of the first transistor and a first electrode of the first transistor in a direction perpendicular to the substrate, wherein the second electrode of the second transistor, the first electrode of the second transistor, the second electrode of the first transistor and the first electrode of the first transistor are annular and are perpendicular to the substrate; forming a channel layer of the second transistor and a channel layer of the first transistor, wherein the channel layer of the first transistor and the channel layer of the second transistor are annular and are perpendicular to the substrate, and the channel layer of the first transistor is connected with a first pole and a second pole of the first transistor; the channel layer of the second transistor is connected with the first pole and the second pole of the second transistor; forming a gate of the second transistor and a gate of the first transistor, a channel layer of the first transistor surrounding the gate of the first transistor; the channel layer of the second transistor surrounds the gate of the second transistor, and the surface of the gate of the second transistor away from the substrate is in contact with the second electrode of the first transistor.

In one possible implementation, forming the channel layer of the first transistor includes: forming a first portion, a second portion, and a third portion of a channel layer of the first transistor, the first portion being in contact with a first pole of the first transistor; the third portion is in contact with the second pole of the first transistor; the third portion connects the first portion and the third portion.

In one possible implementation, forming the gate of the first transistor includes: forming a first gate portion of the gate, an extending direction of the first gate portion being parallel to the substrate; a second gate portion connected to the first gate portion is formed, and an extending direction of the second gate portion is perpendicular to the substrate.

In one possible implementation, forming the channel layer of the second transistor includes: forming a fourth portion, a fifth portion, and a sixth portion of a channel layer of the second transistor, the fourth portion being in contact with a first electrode of the second transistor; the sixth portion is in contact with the second pole of the first transistor; the fifth portion connects the fourth portion with the sixth portion.

In one possible implementation, forming the gate of the second transistor includes: forming a third gate portion of the gate, an extension direction of the third gate portion being parallel to the substrate; a fourth gate portion connected to the third gate portion is formed, and an extending direction of the fourth gate portion is perpendicular to the substrate.

In one possible implementation, the method further includes: forming a writing line, a writing bit line, a reading word line and a reading bit line; the gate of the first transistor is connected with the write word line, the first pole of the first transistor is connected with the write bit line, the second pole of the first transistor is connected with the gate of the second transistor, the first pole of the second transistor is connected with the read word line, and the second pole of the second transistor is connected with the read bit line.

In one possible implementation, forming the write word line, the write bit line, the read word line, and the read bit line includes: forming a write word line on one side of the first transistor away from the substrate, wherein the surface of the gate of the first transistor away from the substrate is contacted with the write word line; forming a write bit line in the same layer as the first electrode of the first transistor in a film layer in a direction perpendicular to the substrate; forming a read word line in the same layer as the first electrode of the second transistor in a film layer in a direction perpendicular to the substrate; the read bit line is formed in the same layer as the second pole of the second transistor in the film layer in the direction perpendicular to the substrate.

In one possible implementation, forming the write word line, the write bit line, the read word line, and the read bit line further includes: the write bit line is integrally arranged with the first pole of the first transistor; the read word line is integrally arranged with the first pole of the second transistor; the read bit line is integral with the second pole of the second transistor.

In a fourth aspect, embodiments of the present application further provide an electronic device, including: a processor and a memory as provided in the foregoing second aspect, wherein the processor and the memory are electrically connected.

Drawings

Fig. 1 is a schematic diagram of an electronic device according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a memory according to an embodiment of the present disclosure;

FIG. 3 is a schematic three-dimensional structure of a memory according to an embodiment of the present disclosure;

FIG. 4 is a simplified circuit diagram of a memory according to an embodiment of the present application;

FIG. 5 is a circuit diagram of a memory cell in a memory according to an embodiment of the present application;

FIG. 6 is a circuit diagram of a memory cell in a memory according to an embodiment of the present application;

FIG. 7 is a circuit diagram of a memory array formed by a plurality of memory cells in a memory according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a process structure of a multi-layer memory cell in a memory according to an embodiment of the present disclosure;

fig. 9 is a diagram of a positional relationship between a memory cell and a substrate in a memory according to an embodiment of the present application;

FIG. 10 is a cross-sectional view of a process structure of a memory cell in a memory according to an embodiment of the present disclosure;

FIG. 11 is a cross-sectional view of a process structure of another memory cell in a memory according to an embodiment of the present disclosure;

FIG. 12a is a cross-sectional view of a process structure of another memory cell in a memory according to an embodiment of the present disclosure;

FIG. 12b is a cross-sectional view of a process structure of another memory cell in a memory according to an embodiment of the present disclosure;

FIG. 13 is a cross-sectional view of a process structure of another memory cell in a memory according to an embodiment of the present disclosure;

FIG. 14 is a cross-sectional view of a process structure for two memory cell stacks provided in an embodiment of the present application;

FIG. 15 is a schematic structural diagram of a memory array including a memory layer according to an embodiment of the present disclosure;

FIG. 16 is a block flow diagram of a method for fabricating a memory according to an embodiment of the present disclosure;

fig. 17a to 17r are cross-sectional views of corresponding process structures after each step in a memory manufacturing method according to an embodiment of the present application is completed.

Detailed Description

The embodiment of the application provides electronic equipment. Fig. 1 is a block circuit diagram of an electronic device 200 according to an embodiment of the present application, where the electronic device 200 may be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, a personal computer (personal computer, PC), a server, a workstation, or the like.

As shown in fig. 1, an electronic device 200 may include a bus 205, and a System On Chip (SOC) 210 coupled to the bus 205. The SOC 210 may be used to process data, such as data of processing applications, process image data, and buffer temporary data. In one embodiment, the SOC 210 may include an application processor (application processor, AP) 211 for processing applications, an image processing unit (graphics processing unit, GPU) 212 for processing image data, and a first random access memory (random access memory, RAM) 213 for caching high-speed data. The first RAM213 may be a static random access memory (static random access memory, SRAM), an embedded flash (eflash), or the like. The AP 211, the GPU 212, and the first RAM213 may be integrated into one die (die), or may be respectively disposed in a plurality of die.

As further shown in fig. 1, the electronic device 200 may further include a second RAM220 connected to the SOC210 via the bus 205. The second RAM220 may be a dynamic random access memory (dynamic random access memory, DRAM). The second RAM220 may be used to hold volatile data, such as temporary data generated by the SOC 210. The second RAM220 typically has a larger storage capacity than the first RAM 213, but typically has a slower read speed than the first RAM 213.

In addition, the electronic device 200 may further include a communication chip 230 and a power management chip 240 connected to the SOC210 through the bus 205. The communication chip 230 may be used for processing the protocol stack, amplifying, filtering, etc. the analog radio frequency signal, or simultaneously implementing the above functions. The power management chip 240 may be used to power other chips. In one embodiment, the SOC210 and the second RAM220 may be packaged in a single package structure, such as with 2.5D (dimension) or 3D packaging, etc., to achieve faster inter-chip data transfer rates.

Fig. 2 is a circuit block diagram of a memory 300 that may be used in an electronic device according to an embodiment of the present application. In one embodiment, the memory 300 may be the first RAM 213 as shown in fig. 1 or the second RAM220. The application scenario of the memory 300 is not limited. In one possible implementation, memory 300 may also be RAM disposed external to SOC 210. The position of the memory 300 in the electronic device and the positional relationship with the SOC210 are not limited in the present application.

As shown in fig. 2, the memory 300 includes a memory array 31 and a controller 32 for accessing the memory array 31, wherein the controller 32 is for controlling read and write operations of the memory array 31. The memory array 31 may be a single-layer memory array, or may include a first-layer memory array and a second-layer memory array stacked in a Z-direction perpendicular to the substrate as shown in fig. 3, or may include more layers of memory arrays in alternative embodiments. Where two or more layers of memory arrays are involved, such memories may be referred to as three-dimensional integrated memory structures to increase storage capacity.

In the memory structure shown in fig. 3, the control circuit is integrated on the substrate by a front end of line (FEOL) process, and the interconnect and the memory are integrated on the control circuit by a back end of line (BEOL) process. The control circuit may generate control signals, which may be read-write control signals, for controlling read-write operations of data in the memory.

In one embodiment, the memory array 31 in the memory may include a plurality of memory cells 400 arranged in an array as shown in FIG. 4, wherein each memory cell 400 may be used to store 1 bit (bit) or multiple bits of data. The memory array 31 may further include signal lines such as Word Lines (WL) and Bit Lines (BL). Each memory cell 400 is electrically connected to a corresponding word line WL and bit line BL. The different memory cells 400 may be electrically connected by WL and BL. One or more WL and BL are used to select the memory cell 400 to be read and written in the memory array by receiving the control level output by the control circuit, so as to implement the read and write operation of data.

The controller 32 in memory may include one or more of the circuit structures shown in fig. 4 as decoder 320, driver 330, timing controller 340, buffer 350, or input-output driver 360.

In the memory 300 structure shown in fig. 4, the decoder 320 is configured to decode according to the received address to determine the memory cell 400 that needs to be accessed. The driver 330 is used to control the level of the signal line according to the decoding result generated by the decoder 320, thereby realizing access to the designated memory cell 400. The buffer 350 is used for buffering the read data, and may be, for example, a first-in first-out (FIFO) buffer. The timing controller 340 is used for controlling the timing of the buffer 350 and controlling the driver 330 to drive the signal lines in the memory array 310. The input-output driver 360 is used to drive transmission signals, such as to drive received data signals and to drive data signals to be transmitted, so that the data signals can be transmitted over a long distance.

The memory array 310, the decoder 320, the driver 330, the timing controller 340, the buffer 350, and the input/output driver 360 may be integrated into one chip or may be integrated into a plurality of chips.

The memory 300 to which embodiments of the present application relate may be a dynamic random access memory (dynamic random access memory, DRAM). A conventional DRAM memory cell is composed of a transistor (transistor) and a capacitor (capacitor), as shown in fig. 5, fig. 5 shows a circuit diagram of a memory cell in a memory provided in an embodiment of the present application, a first terminal of the transistor T of the memory cell is connected to a Bit Line (BL), and a second terminal thereof is connected to a first terminal of the capacitor C. The gate of the transistor T is connected to a Word Line (WL), the second end of the capacitor C may be connected to a voltage terminal, and the voltage terminal may be connected to a voltage (e.g., a ground voltage or a half power supply voltage) of a certain level (e.g., a desired voltage level) through a Source Line (SL).

The memory cell of the 1T1C structure stores "1" or 0 "by using the amount of the charge stored by the capacitor, but with the continuous development of the integrated circuit, the transistor is continuously miniaturized, which also brings unavoidable short channel effects, such as increased leakage current of the transistor, reduced mobility, and the like, when the transistor is in an off state, a certain leakage current exists between the source and the drain, the higher the technology node, such as 10nm, 7nm, 5nm, and higher technology node, the smaller the size of the transistor, the more obvious the short channel effect, and in addition, the projected area of the capacitor is also reduced along with the miniaturization of the transistor, so that in order to ensure the stable operation of the 1T1C memory, the capacitor needs to be made higher, and the continuous expansion of the height of the capacitor and the continuous miniaturization of the projected area also bring great challenges to the etching process.

In order to improve the stability of the DRAM, the embodiment of the present application proposes a 2T0C structure memory, as shown in fig. 6, fig. 6 shows a circuit diagram of one memory cell 400 in the memory 300 provided in the embodiment of the present application, where the memory cell 400 belongs to a memory cell structure of a gain-cell of 2T0C, that is, two transistors, for example, a first transistor T1 and a second transistor T2 are included in one memory cell 400.

In addition, the memory 300 includes four control lines, namely a Write Word Line (WWL), a Write Bit Line (WBL), a Read Word Line (RWL), and a Read Bit Line (RBL), respectively.

The gate of the first transistor T1 is connected to WWL, the first pole of the first transistor T1 is connected to WBL, the second pole of the first transistor T1 is connected to the gate of the second transistor T2, the connection point between the second pole of the first transistor T1 and the gate of the second transistor T2 is used as a Storage Node (SN), the first pole of the second transistor T2 is connected to RBL, and the second pole of the second transistor T2 is connected to RWL.

In the memory cell shown in fig. 6, the write bit line WBL may also be referred to as a first control line for loading a signal to the first pole of the first transistor T1, the read bit line RBL may also be referred to as a second control line for loading a signal to the first pole of the second transistor T2, the write word line WWL may also be referred to as a third control line for loading a signal to the gate of the first transistor T1, and the read word line RWL may also be referred to as a fourth control line for loading a signal to the second pole of the second transistor T2.

In the embodiment of the present application, the transistor, for example, the first transistor T1 or the second transistor T2 described above may be selected from an NMOS (N-channel metal oxide semiconductor ) transistor, or may be selected from a PMOS (P-channel metal oxide semiconductor ) transistor. One of the drain (drain) or source (source) of the transistor is referred to as a first pole, the other pole is referred to as a second pole, and the control terminal of the transistor is a gate. The drain and source of the transistor may be determined according to the flow direction of the current, for example, taking the first transistor T1 shown in fig. 6 as an example, when the current flows from left to right, the first pole at the left end is the drain, and the second pole at the right end is the source; conversely, when the current flows from right to left, the second pole at the right end is the drain and the first pole at the left end is the source.

The memory array 31 can be obtained by arranging the memory cells 400 shown in fig. 6 in an array, wherein the circuit structure of each memory cell 400 is the same. For example, in the memory array 31 shown in fig. 7, a memory array which is 4×4 and is arranged in the X direction and the Y direction perpendicular to each other is exemplarily shown. In some alternative embodiments, when the storage arrays shown in fig. 7 are stacked along the Z direction shown in fig. 3, three-dimensional stacking can be implemented, so as to further improve the storage capacity, so as to adapt to the processor with high operation efficiency.

The writing operation and the reading operation of the 2T0C memory cell 400 shown in fig. 6 are described below.

The write operation process: in the writing operation, the voltage of the read bit line RBL is 0, and the second transistor T2 does not operate; the write word line WWL is supplied with a first write word line control signal which controls the first transistor T1 to be turned on. When first logic information, for example, "0", is written, a first write bit line control signal is supplied to the write bit line WBL (or the read word line RWL), and the first write bit line control signal is written into SN through the first transistor T1. The first transistor T1 is therefore also called a Write Transistor (WTR) and the second transistor T2 is also called a Read Transistor (RTR). When the second logic information, for example, "1", is written, the write bit line WBL (or the read word line RWL) is supplied with the second write bit line control signal, which is written through the first transistor T1.

It should be appreciated that after the write operation is completed, the second transistor T2 does not operate; the write word line WWL is supplied with a second write word line control signal which controls the first transistor T1 to be turned off, and at this time, the potential stored in the node is not affected by the outside.

The read operation process comprises the following steps: providing a second write word line control signal to the write word line WWL, the second write word line control signal controlling the first transistor T1 to be turned off; the read word line RWL (or the write bit line WBL) is supplied with a read word line control signal, and the logic information stored in the memory cell is determined according to the level of the current on the read bit line RBL. When the node stores the first write bit line control signal, since the first write bit line control signal can control the second transistor T2 to be turned on, when the read word line RWL (or the write bit line WBL) provides the read word line control signal, the read word line RWL (or the write bit line WBL) charges the read bit line RBL through the second transistor T2, and the voltage on the read bit line RBL increases, so that when the current on the read bit line RBL is detected to be large, the logic information "0" stored in the memory cell can be read. When the node stores the second write bit line control signal, since the second write bit line control signal can control the second transistor T2 to be turned off, when the read word line RWL (or the write bit line WBL) provides the read word line control signal, the read word line RWL (or the write bit line WBL) does not charge the read bit line RBL through the second transistor T2, and the read bit line RBL maintains the voltage of 0V, so that when the current on the read bit line RBL is detected to be smaller, the logic information "1" stored in the memory cell can be read.

In order to increase the retention time of the 2T0C structure memory, the first transistor T1 and the second transistor T2 may be thin film transistors (Thin film transistor, TFT), where the TFT is a transistor formed by depositing or growing a plurality of film structures, and the conductive channel is an amorphous metal oxide with very low leakage or other wide bandgap materials. Because the leakage of the TFT is much lower than that of a silicon transistor, the leakage of current on the RTR gate through the WTR is greatly reduced, and the storage duration of the memory is greatly prolonged. In the read operation, only the current of the RTR needs to be read, and then the storage state is judged to be "1" or "0" according to the level of the current.

The 2T0C structure memory based on the planar device can increase the memory density by stacking a plurality of memory cell layers in a direction perpendicular to the substrate, for example, a in fig. 8 illustrates a schematic view of a 3-layer memory cell (or memory array) stack, and b in fig. 8 illustrates a schematic cross-sectional view along A-A' direction in a diagram of fig. 8. The transistors T1 and T2 of each memory cell are disposed in the XY plane, the first pole and the second pole of the first transistor T1 are disposed in the XY plane, and the first pole and the second pole of the second transistor T2 are disposed in the XY plane, and because the positions of the first pole and the second pole of the first transistor T1 and the second pole of the second transistor T2 are different, one photomask is required to be used when the first pole and the second pole of the first transistor T1 are formed, one photomask is required to be used when the first pole and the second pole of the second transistor T2 are formed, and 4 photomasks are required to be used when the first pole and the second pole of the second transistor T2 are formed.

In addition, although the storage density can be increased by continuously stacking in the direction perpendicular to the XY plane (i.e., in the Z direction) as shown in fig. 8 b, since the two transistors of each memory cell are all in the XY plane and the first pole and the second pole of each transistor are all distributed in the XY plane, a large number of photomasks are required for preparing each layer of memory array, and the number of photomasks required and the preparation cost are doubled for each layer of stacked memory array, the preparation period is doubled, and furthermore, as the number of stacked layers is increased, the requirement on the alignment accuracy of photolithography is also increased, and there are problems such as complicated preparation process and high risk.

The 2T0C structure memory based on the planar device needs to be subjected to multi-layer wiring, the preparation process is complex, the area utilization rate is low, and therefore, the memory array with high integration density is difficult to realize.

In a memory cell 400 such as that shown in fig. 6 and 7 described above, embodiments of the present application provide some memory cell process structures that may improve the storage density, as described in detail below.

Fig. 9 simply illustrates a layout manner of the first transistor T1 and the second transistor T2 in the memory cell 400, and in fig. 9, the first transistor T1 and the second transistor T2 in any memory cell 400 provided in the embodiment of the present application are stacked in a direction perpendicular to the substrate 100, instead of being laid in a parallel direction perpendicular to the substrate 100.

In addition, the first transistor T1 and the second transistor T2 of the memory cell 400 of the present application each belong to a thin film transistor (Thin film transistor, TFT) structure. In combination with the layout shown in fig. 9, the first transistor T1 and the second transistor T2 may form a three-dimensional integration on the substrate 100.

Referring to fig. 10, fig. 10 is a cross-sectional view of a process structure of one possible implementation of a memory cell 400 provided in an embodiment of the present application, where a first transistor T1 and a second transistor T2 are disposed along a direction perpendicular to a substrate 100, the first transistor T1 includes a gate 411, a first pole 412, a second pole 413, a channel layer 414, and a gate oxide dielectric layer 415, and the second transistor T2 includes the gate 421, the first pole 422, the second pole 423, the channel layer 424, and the gate oxide dielectric layer 425. The grid electrode, the first pole, the second pole, the channel layer and the gate oxide dielectric layer of the first transistor T1 and the second transistor T2 are all annular structures.

The first and second poles 412 and 413 of the first transistor T1 and the first and second poles 422 and 423 of the second transistor T2 are sequentially disposed in a direction perpendicular to the substrate 100. In the embodiment of the present application, a pole of the first transistor T1 or the second transistor T2 close to the substrate is referred to as a second pole of the transistor, and a pole far from the substrate is referred to as a first pole of the transistor.

The gate 411, the gate oxide dielectric layer 415, the channel layer 414, and the like of the first transistor T1 are sequentially stacked in a direction parallel to the substrate, wherein the gate oxide dielectric layer 415 surrounds the gate 411, the channel layer 414 surrounds the gate oxide dielectric layer 415, and the gate oxide dielectric layer 415 is formed of an insulating material, so that the channel layer 414 can be separated from the gate 411. The gate electrode 421, the gate oxide dielectric layer 425, the channel layer 424, and the like of the second transistor T2 are sequentially stacked in a direction parallel to the substrate, wherein the gate oxide dielectric layer 425 surrounds the gate electrode 421, the channel layer 424 surrounds the gate oxide dielectric layer 425, and the gate oxide dielectric layer 425 is formed of an insulating material, so that the channel layer 424 can be separated from the gate electrode 421.

The first transistor T1 and the second transistor T2 are sequentially arranged along the direction perpendicular to the substrate 100, the first pole and the second pole of each transistor T1 and the second transistor T2 are annular, and are arranged along the direction perpendicular to the substrate 100, so that the two electrodes can be formed by stacking the materials of the first pole and the second pole and then forming holes, a photomask is not required to be used for preparing the first pole 412 and the second pole 413 of the first transistor T1 and the first pole 422 and the second pole 423 of the second transistor T2 respectively, the number of photomasks required for preparing each transistor can be reduced, in addition, the shape of a channel layer and a grid electrode of each transistor is annular and is perpendicular to the substrate, the channel layer surrounds the grid electrode, the first pole and the second pole distributed along the direction perpendicular to the substrate are connected, the channel layer and the grid electrode can be sequentially formed in a growing or depositing mode on the inner wall of the holes, etching of the photomask is not required, the area of each pole, the channel layer and the like of each transistor can be greatly reduced by adjusting the photomask, the horizontal structure is also required for preparing the multiple layers, the number of the photomask is also required to be reduced, the number of the memory cells can be prepared in parallel to the manufacturing the multiple layers, the memory array can be further reduced, the manufacturing cost of the memory array can be increased, and the memory array can be further reduced.

With continued reference to fig. 10, the gate 411, the first pole 412, the second pole 413, the channel layer 414 and the gate oxide layer 415 of the first transistor T1 are all ring structures, the axes surrounded by the ring structures are perpendicular to the substrate 100, wherein the first pole 412 and the second pole 413 are disposed along the direction perpendicular to the substrate 100, the gate 411 of the first transistor T1 is located at the side of the second pole 413 away from the substrate, the first pole 412 surrounds the gate 411, the first pole 412 and the second pole 413 are not contacted with each other, the first pole 412 and the second pole 413 are connected through the channel layer 414 surrounding the gate 411, and the channel layer 414 is in ohmic contact with both the first pole 412 and the second pole 413.

Illustratively, the annular first pole 412 includes a first side M1 parallel to the substrate 100 and a second side M2 perpendicular to the substrate 100; the first side M1 faces the substrate 100 (or the second transistor T2), and the second side M2 faces the gate 411. The annular second pole 413 includes a third side M3 parallel to the substrate, the third side M3 being a side surface of the second pole 413 remote from the substrate, the third side M3 facing the gate 411 and the first pole 412.

The channel layer 414 is a channel of carriers in the transistor, also referred to as a semiconductor layer or a conductive channel layer, and the channel layer 414 of the first transistor T1 is in ohmic contact with both the first pole 412 and the second pole 413 of the first transistor T1. In the embodiment of the present application, the channel layer 414 includes a first portion P1, a second portion P2, and a third portion P3; the first portion P1 is located between the first pole 412 of the first transistor T1 and the gate 411 of the first transistor T1; the third portion P3 is located between the second pole 413 of the first transistor T1 and the gate 411 of the first transistor T1; the second portion P2 connects the first portion P1 and the third portion P3.

Referring to fig. 10, a first portion P1 is located between the second side M2 of the first pole 412 of the first transistor T1 and the gate 411, and a third portion P3 is located between the third side M3 of the second pole 413 of the first transistor T1 and the gate 411.

When the gate 411 is powered on, a gate oxide dielectric layer 415 is present between the gate 411 and the channel layer 414, an electric field generated by the gate 411 acts on the channel layer 414 to form a conductive channel in the channel layer, a current may flow from the first pole 412 to the second pole 413 through the channel layer 414, or a current may flow from the second pole 413 to the first pole 412 through the channel layer 414, a pole from which a current flows is called a source (source), and a pole from which a current flows is called a drain (drain).

The second transistor T2 includes a gate 421, a first electrode 422, a second electrode 423, a channel layer 424 and a gate oxide dielectric layer 425, where the gate 421, the first electrode 422, the second electrode 423, the channel layer 424 and the gate oxide dielectric layer 425 are also ring structures, and an axis surrounded by each ring structure is perpendicular to the substrate 100.

The gate 421 of the second transistor T2 is far from the substrate 100, and contacts the second pole 413 of the first transistor T1, the first pole 422 and the second pole 423 are distributed around the gate 411, and the first pole 422 and the second pole 423 are distributed along a direction perpendicular to the substrate, the first pole 422 is located at a side far from the substrate 100, the second pole 423 is located at a side near the substrate 100, and the first pole 422 and the second pole 423 are not contacted with each other and are connected through a channel layer 424 disposed around the gate 421. The channel layer 424 is in ohmic contact with both the first pole 422 and the second pole 423.

The channel layer 424 is a channel of carriers in the transistor, also referred to as a semiconductor layer or a conductive channel layer, and the channel layer 424 of the second transistor T2 is in ohmic contact with both the first pole 422 and the second pole 423 of the second transistor T2. In the embodiment of the present application, the channel layer 424 of the second transistor T2 includes a fourth portion P4, a fifth portion P5, and a sixth portion P6; the fourth portion P4 is located between the first electrode 422 of the second transistor T2 and the gate 421 of the second transistor T2; the sixth portion P6 is located between the second pole 423 of the second transistor T2 and the gate 421 of the second transistor T2; the fifth part P5 connects the fourth part P4 and the sixth part P6.

A gate oxide dielectric layer 425 is disposed between the channel layer 424 and the gate 421. It is also contemplated that the gate oxide dielectric layer 425 is disposed around the gate 421, the channel layer 424 is disposed around the gate oxide dielectric layer 425, and the first and second poles 422 and 423 are disposed around the channel layer 424. This allows the second transistor T2 to form a multi-layered ring structure.

As can be seen, the memory cell 400 provided in the embodiment of the present application includes the first transistor T1 and the second transistor T2, where the first transistor T1 and the second transistor T2 are distributed along the vertical direction of the substrate, and the first pole and the second pole of the first transistor T1 or the second transistor T2 are distributed along the vertical direction of the substrate 100, so that multiple etching of a photomask is not required to form the first pole and the second pole, and only the materials of the first pole and the second pole need to be stacked along the vertical direction of the substrate 100; the first pole and the second pole are distributed in the direction vertical to the substrate, so that the channel layer connecting the first pole and the second pole can encircle a vertical channel with the axis vertical to the substrate, the channel layer, the gate oxide dielectric layer and the grid electrode are sequentially stacked, more photomasks are needed for preparing the structure of arranging the first pole, the second pole, the channel layer and the like in the direction parallel to the substrate, the first pole and the second pole can be formed in a mode of stacking electrode materials and then opening holes, the channel layer, the gate oxide dielectric layer and the grid electrode are formed through the processes of opening holes, growing, depositing and the like, and the first pole and the second pole do not need to be prepared by utilizing photomasks respectively, so that the number of photomasks needed can be reduced, the alignment difficulty in the preparation process is reduced, and the cost is reduced.

In the above example, the structure of the second transistor T2 is different from that of the first transistor T1, and the main difference is that the second poles of the two transistors are different, the second pole 413 of the first transistor T1 is located at a side of the gate 411 near the substrate 100, and the second pole 423 of the second transistor T2 is disposed around the gate 421. In another embodiment of the present application, the structure of the second transistor T2 may be the same as that of the first transistor T1.

See, for example, fig. 11. The second pole 423 of the second transistor T2 is located at a side of the gate 421 near the substrate 100, and the first pole 422 is disposed around the gate 421. The first pole 422 and the second pole 423 are connected by a channel layer 424 surrounding the gate 421, the channel layer 424 is in ohmic contact with both the side of the first pole 422 facing the gate 421 and the side of the second pole 423 facing away from the substrate 100, and a gate oxide dielectric layer 425 is located between the gate 421 and the channel layer 424 to separate the gate 421 from the channel layer 424.

In the foregoing examples, it is mentioned that a short channel effect may be caused in the case where the channel width of the transistor is small, but such a problem may be well overcome for the memory cell 400 provided in the embodiment of the present application. In the memory cell provided by the embodiment of the application, the first transistor T1 and the second transistor T2 are of vertical channel structures, the first pole and the second pole are distributed along the direction perpendicular to the substrate, the channel layer is connected with the first pole and the second pole, and the larger the interval between the first pole and the second pole is, the larger the width of the channel layer is, so that the short channel effect can be avoided.

However, in some cases, under the situation that the distance between the first pole and the second pole cannot be made larger due to the limitation of the sizes of the first transistor T1 and the second transistor T2, the embodiment of the application provides another implementation manner, which can increase the effective channel width, increase the on current of the transistor, and avoid the occurrence of short channel effect.

Referring to fig. 12a, referring to the memory cell shown in fig. 10, the gate 411 of the first transistor T1 includes a first gate portion G1 and a second gate portion G2 in contact, wherein the first gate portion G1 extends in parallel with the substrate 100, the second gate portion G2 extends in perpendicular to the substrate 100, and one end of the first gate portion G1 is connected to one end of the second gate portion G2 near the substrate 100, such that the cross-section of the gate 411 of the first transistor T1 is L-shaped.

The first pole 412 of the first transistor T1 is located at a side of the first gate portion G1 remote from the substrate 100, and the second pole 413 of the first transistor T1 is located at a side of the first gate portion G1 close to the substrate 100. This can be considered as follows: the first gate portion G1 of the gate 411 of the first transistor T1 separates the first pole 412 from the second pole 413 of the first transistor T1 in a direction perpendicular to the substrate 100.

It can be seen that, since the size of the first transistor T1 cannot be too large, the length of the gate 411 in the direction perpendicular to the substrate 100 cannot be too long, and in the memory cell 400 provided in this embodiment of the present application, the first gate portion G1 of the gate 411 of the first transistor T1 may also extend in the direction parallel to the substrate 100, and since the channel layer 414 is disposed around the gate 411, the channel layer 414 may form a concave structure parallel to the substrate 100. The greater the length of extension of the first gate portion G1 of the gate 411, the deeper the recess of the concave structure, and accordingly, the greater the channel width of the channel layer 414 of the first transistor T1, the greater the on-current of the first transistor T1. Conversely, if the extension length of the first gate portion G1 is shorter, the depth of the concave structure formed by the channel layer 414 is shallower, and the channel width of the channel layer 414 is smaller, the on current of the first transistor T1 is smaller, so that the effective channel width of the channel layer 414 can be adjusted by adjusting the extension length of the first gate portion G1, thereby improving the read-write performance of the memory.

The gate oxide dielectric layer 415 of the first transistor T1 also forms a matching concave structure based on the channel layer 414 of the first transistor T1 to achieve electrical isolation of the channel layer 414 of the first transistor T1 from the gate 411 of the first transistor T1.

Similarly, the gate 421 of the second transistor T2 also includes a portion perpendicular to the substrate 100 and a portion parallel to the substrate 100, wherein the extending direction is parallel to the substrate 100 and is the third gate portion G3, and the extending direction is perpendicular to the substrate 100 and is the fourth gate portion G4. One end of the third gate portion G3 is connected to the fourth gate portion G4. The first electrode 422 of the second transistor T2 is located at an end of the third gate portion G3 remote from the substrate, the second electrode 423 of the second transistor T2 is located at an end of the third gate portion G3 close to the substrate, and the third gate portion G3 of the second transistor T2 separates the first electrode 422 from the second electrode 423 of the second transistor T2 in a direction perpendicular to the substrate 100.

The channel layer 424 of the second transistor T2 surrounds the gate electrode 421, and thus, the channel layer 424 of the second transistor T2 forms a concave structure at a portion where the third gate portion G3 of the gate electrode 421 of the second transistor T2 extends.

The longer the third gate portion G3 extends, the greater the depth of the concave structure formed by the channel layer 424, so that the greater the width of the channel layer 424, the greater the on-current of the second transistor T2; conversely, if the extension length of the third gate portion G3 is shorter, the depth of the concave structure formed by the channel layer 424 is smaller, so that the width of the channel layer 424 is smaller, the on-current of the second transistor T2 is smaller, and thus the width of the channel layer 424 can be adjusted by adjusting the extension length of the third gate portion G3 of the gate 421 of the second transistor T2.

Illustratively, the first electrode 422 of the second transistor T2 includes a fourth side M4 perpendicular to the substrate 100 and a fifth side M5 parallel to the substrate 100, wherein the fourth side M4 faces the gate 421 and the fifth side M5 faces the substrate 100. The second pole 423 of the second transistor includes a sixth side M6 parallel to the substrate 100 and a seventh side M7 perpendicular to the substrate 100. Wherein the sixth side M6 is remote from the substrate 100 and the seventh side M7 is directed towards the gate 421 of the second transistor T2.

The channel layer 424 of the second transistor T2 includes a fourth portion P4, a fifth portion P5 and a sixth portion P6, the fourth portion P4 being located between the first electrode 422 and the gate 421 of the second transistor T2, and the fourth portion P4 being in contact with both the fourth side M4 and the fifth side M5 of the first electrode 422 in conjunction with fig. 12 a; the sixth portion P6 is in contact with both the sixth side M6 and the seventh side M7 of the second pole, and the longer the third gate portion G3 of the gate 421 extends, the deeper the depth of the concave structure formed by the channel layer 424, i.e., the greater the width of the channel layer 424. Conversely, if the extension length of the third gate portion G3 of the gate 421 of the second transistor T2 is shorter, the depth of the concave structure formed by the channel layer 424 is shallower, and the channel width of the channel layer 424 is smaller, the on-current of the second transistor T2 is smaller, so that the effective channel width of the channel layer 424 can be adjusted by adjusting the extension length of the first gate portion G1 of the gate 421 of the second transistor T2, thereby improving the read-write performance of the memory.

The gate oxide dielectric layer 425 of the second transistor T2 also forms a matching recess structure based on the recess structure formed by the channel layer 424 of the second transistor T2 to electrically isolate the channel layer 424 of the first transistor T1 from the gate 421 of the first transistor T1.

Of course, referring to fig. 12b, based on the structure of the memory cell shown in fig. 11, the channel widths of the first transistor T1 and the second transistor T2 can be increased by forming a concave channel layer structure, so as to avoid the short channel effect.

Since the operation principle of the memory cell structures provided in fig. 10 and 11 is the same and the structures are similar, the memory cell shown in fig. 10 is taken as an example in the following description of the present application, and the present application can be applied to the memory cell provided in fig. 11.

Based on the memory cell structure provided in fig. 10, fig. 13 is a cross-sectional view of a process structure of another memory cell provided in the embodiment of the present application, in the first transistor T1 and the second transistor T2, a conductive film layer is further provided, and in the first transistor T1, the conductive film layer 416 is used to connect the first pole 412 and the second pole 413 of the first transistor T1, so as to improve ohmic contact and increase the on current of the first transistor T1. In the second transistor T2, the conductive film 426 is used to connect the first electrode 422 and the second electrode 423 of the second transistor T2, so as to improve ohmic contact and increase the on-current of the second transistor T2.

Referring to fig. 14, fig. 14 shows a schematic diagram of a memory cell stack, where the memory array provided in the embodiment of the present application may be stacked in a direction perpendicular to the substrate 100 to increase the memory density, and different memory layers in the Z direction are separated by an insulating medium, so that any memory cell of the memory array in any layer can be accessed in a read/write process, and data read/write of the memory array in other layers is not affected. Wherein the insulating medium may be aluminum oxide (AlOx).

Fig. 15 is a simplified schematic diagram of a three-dimensional structure of a memory 300 according to the present application, and in fig. 15, the memory 300 is exemplarily shown to include one layer of a memory array, and of course, in an alternative embodiment, more layers of memory arrays may be stacked in a direction perpendicular to the substrate.

As shown in fig. 15, in any one layer of the memory array, a plurality of memory cells arranged in a first direction are included, and in order to distinguish the memory cells, the memory cells are respectively identified as memory cells MC1 to MC4, for example, memory cell MC1 and memory cell MC2 shown in fig. 15 are arranged in the first direction, and memory cell MC3 and memory cell MC4 are arranged in the first direction; the memory array of any one layer further includes a plurality of memory cells arranged in a second direction, for example, as shown in fig. 15, in which the memory cells MC1 and MC3 are arranged in the second direction, and the memory cells MC2 and MC4 are arranged in the second direction, wherein the first direction and the second direction are perpendicular to each other, and herein, the first direction may refer to an X direction shown in the drawing, and the second direction may be a Y direction shown in the drawing.

The memory array further includes a plurality of write word lines, write bit lines, read word lines, and read bit lines, wherein the write word lines, read word lines extend along a first direction, for example WWL1 extends along the first direction and WWL2 extends along the first direction as shown in fig. 15; RWL1 extends in a first direction and RWL2 extends in a first direction; the write bit lines and the read bit lines extend in a second direction, for example, WBL1 extends in the second direction and WBL2 extends in the second direction as shown in fig. 15; RBL1 extends in a first direction and RBL2 extends in a second direction.

The write word line is electrically connected to the gates of the first transistors T1 of the plurality of memory cells located in the first direction, for example, as shown in fig. 15, WWL1 is connected to the gates of the first transistors T1 of the MC1, MC 2; the write bit line is electrically connected to the first poles of the first transistors T1 of the plurality of memory cells located in the second direction, e.g., WBL1 is connected to the first poles of the first transistors T1 of MC1, MC 3; the read word line is electrically connected to the first poles of the second transistors T2 of the plurality of memory cells located in the first direction, e.g., RWL2 is connected to the first poles of the second transistors T2 of MC1, MC 2; the read bit line is electrically connected to the second poles of the second transistors T2 of the plurality of memory cells located in the second direction, e.g., RBL2 is connected to the second poles of the second transistors T2 of the MC2, MC 4.

In other words, the gate of the first transistor T1 is connected to the write word line, the first pole of the first transistor T1 is connected to the write bit line, the first pole of the second transistor T2 is connected to the read word line, and the second pole of the second transistor T2 is connected to the read bit line, however, in each memory cell, the second pole of the first transistor T1 of the memory cell is connected to the gate of the second transistor T2.

The write word line is located on a side of the first transistor T1 remote from the substrate 100, and the gate 411 of the first transistor T1 is in contact with the write word line away from the surface of the substrate 100, for example, WWL2 is in contact with the gate 411 of the first transistor T1 as shown in fig. 15. The write bit line is located in the same layer as the first electrode 412 of the first transistor T1 in a direction perpendicular to the substrate 100, e.g., WBL2 is located in the same layer as the first electrode 412 of the first transistor T1 as shown in fig. 15. The read word line is located at the same layer as the first electrode 422 of the second transistor T2 in the direction perpendicular to the substrate 100; for example, as shown in FIG. 15, RWL2 is on the same layer as the first electrode 422 of the second transistor T2; the read bit line is located at the same layer as the second pole 423 of the second transistor T2 in the direction perpendicular to the substrate 100, for example, as shown in fig. 15, the RBL2 is located at the same layer as the second pole 423 of the second transistor T2.

In some possible implementations, the write bit line is formed of the same material as the first pole of the first transistor T1, and is integrally provided with the first pole 412 of the first transistor T1, or the write bit line may be used as the first pole of the first transistor T1; the read word line and the first electrode of the second transistor T2 are formed of the same material, and the read word line and the first electrode 422 of the second transistor T2 are integrally arranged, or the read word line may be used as the first electrode of the second transistor T2; the read bit line and the second diode 423 of the second transistor T2 are formed of the same material, and the read bit line is integrally provided with the second diode 423 of the second transistor T2, or may be the read bit line or may be the second diode of the second transistor T2.

The materials that the first transistor T1, the second transistor T2, the write word line, the write bit line, the read word line, and the read bit line may be selected are described below.

Wherein, the materials of the writing bit line, the reading bit line and the reading word line are the same; the material of the write word line is different from the material of the write bit line, or the material of the first pole 412 of the first transistor T1, the material of the first pole 422 of the second transistor T2, and the material of the second pole 423 are the same, and the material of the write word line is different from the material of the write bit line, and the write word line and the write bit line are two materials with a higher selective etching ratio, because the write word line is connected with the gate of the first transistor T1, and the gate of the first transistor T1 is located at a side far away from the substrate, that is, the first transistor T1 and the second transistor T2 are located in the space between the write word line and the substrate, in order to avoid affecting the write word line when preparing the first transistor T1, the second transistor T2, and other control lines, the write word line and the read bit line are different, for example, the write word line and the read bit line are two materials with a higher selective etching ratio, so that they do not affect each other when etching.

The second pole 413 of the first transistor T1 is in contact with the gate 421 of the second transistor T2, the second pole 413 of the first transistor T1 may be used as SN of the memory cell, and the second pole 413 of the first transistor T1 is made of the same material as the write word line.

The gate 411 of the first transistor T1 and the gate 421 of the second transistor T2 are in a ring structure, and the axes around which they surround are perpendicular to the substrate 100, and the materials of the gate 411 of the first transistor T1 and the gate 421 of the second transistor T2 may be the same as the material of the write word line or the material of the read bit line, and of course, the materials of the gate 411 of the first transistor T1 and the gate 421 of the second transistor T2 may be different from the material of the write word line or the material of the read bit line.

Illustratively, the write word line, the second pole 423 of the first transistor T1, the gate 411 of the first transistor T1, the gate 421 of the second transistor T2 are metal materials or other conductive materials, and may be, for example, titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (Wu), molybdenum (Mo), indium TiN Oxide (ITO), indium Zinc Oxide (IZO), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), or the like, or any combination thereof.

The write bit line, the read word line, the read bit line may be a metal material or other conductive material, for example, titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (Wu), molybdenum (Mo), indium TiN Oxide (ITO), indium Zinc Oxide (IZO), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), or any combination thereof, but the material of the write bit line, the read word line, the read bit line is different from the material of the write word line.

The gate oxide dielectric layer is made of insulating material such as silicon dioxide (SiO ₂ ) Aluminum oxide (Al) ₂ O ₃ ) Hafnium oxide (HfO) ₂ ) Zirconium dioxide (ZrO) ₂ ) Titanium dioxide (TiO) ₂ ) Yttria (Y) ₂ O ₃ ) Silicon nitride (Si) ₃ N ₄ ) Iso-insulating material or aluminum (Al) -doped hafnium oxide (HfO) ₂ ) Silicon (Si) -doped hafnium oxide (HfO) ₂ ) Zirconium (Zr) doped hafnium oxide (HfO) ₂ ) Lanthanum doped hafnium oxide (HfO) ₂ ) Yttrium (Y) -doped hafnium oxide (HfO) ₂ ) Etc. ferroelectric materials or any combination thereof, laminated structures of combination materials, etc.

The material of the channel layer may be silicon-based semiconductor material such as silicon (Si), polysilicon (poly-Si), amorphous silicon (amorphorus-Si), or indium trioxide (In) ₂ O ₃ ) Zinc oxide (ZnO), gallium oxide (Ga) ₂ O ₃ ) Indium Tin Oxide (ITO), titanium dioxide (TiO) ₂ ) Such as metal oxide, indium gallium zinc oxide (In-Ga-Zn-O), indium tin zinc oxide (In-Sn-Zn-O), and the likeThing, graphene, molybdenum disulfide (MoS ₂ ) A two-dimensional semiconductor material such as black phosphorus, or any combination thereof.

The conductive film layers 416 and 426 may be heavily doped conductive materials, such as Indium Gallium Zinc Oxide (IGZO) with a high indium (In) content, indium oxide (InOx), zinc oxide (ZnO), C-axis aligned crystalline indium gallium zinc oxide (CAAC IGZO), indium Tin Oxide (ITO), and the like.

In addition, referring to fig. 3 and 14, the memory cell provided in the embodiments of the present application may further increase the storage density by stacking the layers in a direction perpendicular to the substrate (e.g., the Z direction in the drawing), where different memory layers are isolated by dielectric layers, and the dielectric layers are made of insulating materials, such as silicon dioxide (SiO ₂ ) Aluminum oxide (Al) ₂ O ₃ ) Hafnium oxide (HfO) ₂ ) Zirconium dioxide (ZrO) ₂ ) Titanium dioxide (TiO) ₂ ) Yttria (Y) ₂ O ₃ ) Silicon nitride (Si) ₃ N ₄ ) Such as insulating materials or any combination thereof, laminated structures, and laminated structures of the combination materials.

In addition, the embodiment of the application further provides a method for forming a memory array, and fig. 16 is a schematic flow chart for preparing the memory array provided in the embodiment of the application.

Step S1: forming a first transistor and a second transistor in a direction perpendicular to the substrate, each of the first transistor and the second transistor including a gate electrode, a first pole, a second pole, and a channel layer connecting the first pole and the second pole; the first pole and the second pole of the first transistor are arranged along the direction vertical to the substrate, the channel layer of the first transistor is annular, and the axis surrounded by the channel layer of the first transistor is vertical to the substrate; the surface of the grid electrode of the second transistor far away from the substrate is contacted with the second electrode of the first transistor; the first pole and the second pole of the second transistor are arranged along the direction vertical to the substrate, the channel layer of the second transistor is annular, and the axis surrounded by the channel layer of the second transistor is vertical to the substrate.

Step S2: the first electrode of the first transistor is electrically connected with the write bit line, the first electrode of the second transistor is electrically connected with the read word line, and the second electrode of the second transistor is electrically connected with the read bit line.

It should be noted that, the steps S1 and S2 are not limited to the process flow, and the step S1 is executed first and then the step S2 is executed. In some alternative process flows, step S1 and step S2 may be performed simultaneously; or part of the flow in the step S2 is performed simultaneously with the step S1; or the partial flow of step S1 is performed simultaneously with step S2.

Illustratively, step S1 includes:

s1a: the second pole of the first diode, the first pole of the second transistor, the second pole of the first transistor and the first pole of the first transistor are all annular in the direction perpendicular to the substrate, and are perpendicular to the substrate.

In the embodiment of the application, the first pole, the second pole and the first pole and the second pole of the first transistor are vertical to the substrate and are distributed along the direction vertical to the substrate, so that the first pole, the second pole and the first pole and the second pole of the first transistor can be formed by stacking materials of the first pole and the second pole and then forming through holes, and the first pole and the second pole of the first transistor and the first pole and the second pole of the second transistor do not need to be prepared by using photomasks respectively, so that the number of photomasks required can be reduced, and the difficulty and the cost of a preparation process are reduced.

S1b: forming a channel layer of the second transistor and a channel layer of the first transistor, wherein the channel layer of the first transistor and the channel layer of the second transistor are annular and are perpendicular to the substrate, and the channel layer of the first transistor is connected with a first pole and a second pole of the first transistor; the channel layer of the second transistor is connected with the first pole and the second pole of the second transistor.

Illustratively, forming the channel layer of the second transistor includes: forming a fourth portion, a fifth portion, and a sixth portion of a channel layer of the second transistor, the fourth portion being in contact with a first electrode of the second transistor; the sixth portion is in contact with the second pole of the first transistor; the fifth portion connects the fourth portion with the sixth portion.

Illustratively, forming the channel layer of the first transistor includes: forming a first portion, a second portion, and a third portion of a channel layer of the first transistor, the first portion being in contact with a first pole of the first transistor; the third portion is in contact with the second pole of the first transistor; the third portion connects the first portion and the third portion.

The channel layer of the first transistor and the channel layer of the second transistor may be prepared simultaneously.

S1c: and forming a gate oxide dielectric layer of the second transistor and a gate oxide dielectric layer of the first transistor.

S1d: forming a gate of the second transistor and a gate of the first transistor, a channel layer of the first transistor surrounding the gate of the first transistor; the channel layer of the second transistor surrounds the gate of the second transistor, and the surface of the gate of the second transistor away from the substrate is in contact with the second electrode of the first transistor.

Illustratively, forming the gate of the first transistor includes: forming a first gate portion of the gate, an extending direction of the first gate portion being parallel to the substrate; a second gate portion connected to the first gate portion is formed, and an extending direction of the second gate portion is perpendicular to the substrate.

Illustratively, forming the gate of the second transistor includes: forming a third gate portion of the gate, an extension direction of the third gate portion being parallel to the substrate; a fourth gate portion connected to the third gate portion is formed, and an extending direction of the fourth gate portion is perpendicular to the substrate.

Here, the extension lengths of the first gate portion of the gate of the first transistor and the third gate portion of the gate of the second transistor may be adjusted as required.

Illustratively, forming the write word line, the write bit line, the read word line, and the read bit line includes:

forming a write word line on one side of the first transistor away from the substrate, wherein the surface of the gate of the first transistor away from the substrate is contacted with the write word line; forming a write bit line in the same layer as the first electrode of the first transistor in a film layer in a direction perpendicular to the substrate; forming a read word line in the same layer as the first electrode of the second transistor in a film layer in a direction perpendicular to the substrate; the read bit line is formed in the same layer as the second pole of the second transistor in the film layer in the direction perpendicular to the substrate.

The specific process flows involved in the above steps S1 and S2 are described below with reference to the accompanying drawings.

Fig. 17a to 17m are schematic cross-sectional views of a process structure after each step in a process for manufacturing a memory array according to an embodiment of the present application.

As shown in fig. 17a, a stacked structure of a first conductive layer 002 and a first sacrificial layer 003 is sequentially formed over a substrate 100 in a direction perpendicular to the substrate 100.

The first conductive layer 002 may be a metal material such as any one of titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (Wu), molybdenum (Mo), indium TiN Oxide (ITO), indium Zinc Oxide (IZO), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), or any combination thereof.

The material of the first sacrificial layer 003 here is an oxide which may be silicon, such as SiOx.

As shown in fig. 17b, grooves 004 are formed in the stacked first conductive layer 002 and first sacrificial layer 003, and then an insulating medium 005 is filled in the grooves 004. For example, as shown in fig. 17c, the material of the insulating medium 005 may be SiNx, and the insulating medium 005 is backfilled and then planarized by a Chemical Mechanical Polishing (CMP) process.

As shown in fig. 17d, a second conductive layer 006, a first insulating dielectric layer 007, a second sacrificial layer 008, a third sacrificial layer 009, and a third conductive layer 010 are sequentially deposited on the stacked first conductive layer 002 and first sacrificial layer 003. Then, the slot 011 is etched again to the first insulating dielectric layer 007, and then referring to fig. 17e, the insulating dielectric 012 is backfilled in the slot 011, the material of the insulating dielectric 012 may be the same as that of the insulating dielectric 005, and a planarization process is performed by using a Chemical Mechanical Polishing (CMP) process after the insulating dielectric 012 is backfilled.

As shown in fig. 17f, a second insulating dielectric layer 013 and a fourth conductive layer 014 are further sequentially deposited on the third conductive layer 010, and the fourth conductive layer 014 is different from the materials of the first conductive layer 002, the second conductive layer 006 and the third conductive layer 010 described above.

As shown in fig. 17g, a through hole is opened such that the through hole penetrates through the fourth conductive layer 014, the second insulating dielectric layer 013, the third conductive layer 010, the third sacrificial layer 009, the second sacrificial layer 008 and the first insulating dielectric layer 007, the second conductive layer 006, the first sacrificial layer 003 and the first conductive layer 002 in order, as shown in fig. 17g, two holes, respectively, the hole 015 and the hole 016, are opened in the structure shown in fig. 17g, each hole corresponds to one memory cell, so that the structure shown in fig. 17g can prepare two memory cells distributed along the parallel substrate direction.

As shown in fig. 17h, the second sacrificial layer 008 is removed, and for example, the second sacrificial layer 008 may be removed from the opened holes 15, 16, or the like by a process of wet etching.

After the second sacrificial layer 008 is removed, a conductive material is grown in the cavity formed by removing the second sacrificial layer 008 to form a fifth conductive layer 017, where the fifth conductive layer 017 may be made of a metal material, and the metal material of the fifth conductive layer 017 may be the same as that of the fourth conductive layer 014.

As shown in fig. 17i, the third sacrificial layer 009 and the first sacrificial layer 003 are partially removed (or completely removed), and the first conductive layer 002, the second conductive layer 006, and the third conductive layer 010 are partially removed. Here, the third sacrificial layer 009 and the first sacrificial layer 003 may be partially removed (or completely removed) by a process such as wet etching, and the first conductive layer 002, the second conductive layer 006, and the third conductive layer 010 may be partially removed. Since the first conductive layer 002, the second conductive layer 006, and the third conductive layer 010 can be made of the same material, the first conductive layer 002, the second conductive layer 006, and the third conductive layer 010 can be partially removed by the same etchant, and the degree of etching can be adjusted by controlling the length of etching time.

After the third sacrificial layer 009 and the first sacrificial layer 003 are partially removed (or completely removed), and the first conductive layer 002, the second conductive layer 006, and the third conductive layer 010 are partially removed, the internal apertures of the original holes 015 and 016 are enlarged, and are separated into upper and lower portions by the fifth conductive layer 017 and the first insulating medium layer 007 in the direction perpendicular to the substrate. Taking hole 015 as an example, is divided into 015a and 015b, wherein the space of 015a is used to form the first transistor T1,015b and the space of 015b is used to form the second transistor T2.

Further, in this step, the longer the third sacrificial layer 009 and the first sacrificial layer 003 are etched, the more the portions of the third sacrificial layer 009 and the first sacrificial layer 003 are etched, so that the deeper the grooves formed by removing the third sacrificial layer 009 and the first sacrificial layer 003, the deeper the concave structures formed when the channel layer and the gate oxide dielectric layer are formed in the subsequent process, and the depth of the concave structures formed by the channel layer can be adjusted by controlling the length of time for etching the third sacrificial layer 009 and the first sacrificial layer 003, for example, the longer the time for etching the third sacrificial layer 009 and the first sacrificial layer 003, the deeper the depth of the concave structures formed by the channel layer, and the greater the width of the conductive channel, and the greater the on-current of the transistor.

Of course, in this step, the third sacrificial layer 009 and the first sacrificial layer 003 may not be etched, so that the gates of the first transistor T2 and the second transistor T2 may be formed to be perpendicular to the substrate 100, and the channel layer and the gate oxide dielectric layer may not be formed to be concave.

Referring to fig. 17j, a semiconductor material layer 018 and a gate oxide dielectric layer 019 are sequentially grown within a cavity (e.g., 015a shown in fig. 17 i) formed by partially removing the third sacrificial layer 009 and the third conductive layer 010. A semiconductor material layer 020 and a gate oxide dielectric layer 021 are sequentially grown in a cavity (e.g., 015b shown in fig. 17 i) formed by partially removing the first conductive layer 002, the first sacrificial layer 003, and the second conductive layer 006.

For example, semiconductor material layer 018 and gate oxide dielectric layer 019, and semiconductor material layer 020 and gate oxide dielectric layer 021 may be formed by depositing semiconductor material and gate oxide dielectric material in sequence within holes 015 and 016, respectively, using a monoatomic layer deposition (atomic layer deposition, ALD) process, as shown.

Wherein the semiconductor material layer 018 is used to form a channel layer of the first transistor T1, and the gate oxide dielectric layer 019 is used to form a gate oxide dielectric layer of the first transistor T1; the semiconductor material layer 020 is used for forming a channel layer of the second transistor T2, and the gate oxide dielectric layer 021 is used for forming a gate oxide dielectric layer of the second transistor T2.

The semiconductor material layers 018 and 020 may be silicon-based semiconductor material such as silicon (Si), polysilicon (poly-Si), amorphous silicon (amorphorus-Si), or indium trioxide (In) ₂ O ₃ ) Zinc oxide (ZnO), gallium oxide (Ga) ₂ O ₃ ) Indium Tin Oxide (ITO), titanium dioxide (TiO) ₂ ) Such as metal oxide, indium gallium zinc oxide (In-Ga-Zn-O), indium tin zinc oxide (In-Sn-Zn-O), graphene, molybdenum disulfide (MoS) ₂ ) A two-dimensional semiconductor material such as black phosphorus, or any combination thereof. The material of the gate oxide dielectric layers 019 and 021 may be an insulating material such as silicon dioxide (SiO ₂ ) Aluminum oxide (Al) ₂ O ₃ ) Hafnium oxide (HfO) ₂ ) Zirconium dioxide (ZrO) ₂ ) Titanium dioxide (TiO) ₂ ) Yttria (Y) ₂ O ₃ ) Silicon nitride (Si) ₃ N ₄ ) Iso-insulating material or aluminum (Al) -doped hafnium oxide (HfO) ₂ ) Silicon (Si) -doped hafnium oxide (HfO) ₂ ) Zirconium (Zr) doped hafnium oxide (HfO) ₂ ) Lanthanum doped hafnium oxide (HfO) ₂ ) Yttrium (Y) -doped hafnium oxide (HfO) ₂ ) Etc. ferroelectric materials or any combination thereof, laminated structures of combination materials, etc.

As shown in fig. 17k, portions of semiconductor material layer 018 are etched and then gate oxide dielectric layer 019 is again deposited. This can prevent the semiconductor material layer 018 from contacting the gate electrode when forming the gate electrode of the first transistor T1, and prevent the semiconductor layer 020 from contacting the gate electrode when forming the gate electrode of the second transistor T2.

As shown in fig. 17l, after the first insulating dielectric layer 007 and the second insulating dielectric layer 013 are partially removed, a portion 019 (such as a portion in a dashed line frame in the figure) of the gate oxide dielectric layer may be highlighted or suspended, and a portion 021 (such as a portion in a dashed line frame in the figure) of the gate oxide dielectric layer may be highlighted or suspended.

As shown in fig. 17m, 019 of the gate oxide dielectric layer and 021 of the gate oxide dielectric layer are removed to highlight or suspend the portions.

As shown in fig. 17n, the gate material is filled in the holes using an ALD process. For example, the gate material 022 and the gate material 023 may be grown through the holes 015 and 016 shown in fig. 17e, and the gate material 022 and the gate material 023 may be, for example, titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (Wu), molybdenum (Mo), indium TiN Oxide (ITO), indium Zinc Oxide (IZO), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), or the like, or any combination thereof. Wherein the gate material 022 is used to form the gate of the first transistor T1, and the gate material 023 is used to form the gate of the second transistor T2

As shown in fig. 17o, the gate material 022, the gate material 023 are filled and etched back, and then the insulating dielectric material 024 is filled in the hole, so that the first transistor T1 and the second transistor T2 distributed along the direction perpendicular to the substrate 100 are formed, and the first transistor T1 and the second transistor T2 are both in a ring-shaped structure.

As can be seen from fig. 17a to 17o, the present application is schematically presented as a process for manufacturing a memory cell, wherein the first transistor and the second transistor of any one memory cell are manufactured simultaneously, instead of manufacturing one transistor first and then manufacturing the other transistor.

In addition, the process for manufacturing the memory unit provided by the embodiment of the application can form the memory unit only by perforating the laminated structure and then etching, depositing, backfilling and other processes in the holes, so that the steps of photomask quantity, alignment and the like required for manufacturing the transistor with the horizontal structure are reduced, and the process difficulty is reduced.

From fig. 17a to 17o, it can be seen that two memory cells arranged along the X-direction are separated by insulating media 005 and 012. The gate of the first transistor T1 of the two memory cells is connected to WWL extending in the X-direction, whereas the first pole of the second transistor T2 of the two memory cells is connected to RWL extending in the X-direction.

In addition, after forming a layer of memory cells, an insulating medium may be grown on the layer of memory cells, where the insulating medium may be SiO ₂ 、Al ₂ O ₃ 、HfO ₂ 、ZrO ₂ 、TiO ₂ 、Y ₂ O ₃ 、Si ₃ N ₄ Such as insulating materials or any combination thereof, laminated structures, and laminated structures of the combination materials. And then forming another layer of memory cells in the Z direction, wherein two adjacent layers of memory cells in the Z direction can be separated by an insulating medium, so that the three-dimensional stacking of the memory array is realized.

From fig. 17a to 17o, it can be seen that the first conductive layer 002 is used to form the second pole of the second transistor T2 and the read word line, so the second pole of the second transistor T2 is located at the same layer as the read word line and may be integrally provided; the second conductive layer 006 is used to form the first pole of the second transistor T2 and the read bit line, so the first pole of the second transistor T2 and the read bit line are located in the same layer, and may be integrally disposed; the fifth conductive layer 017 is used to form the second pole of the first transistor T1, the third conductive layer 010 is used to form the first pole of the first transistor T1 and the write bit line, so that the first pole of the first transistor T1 and the write bit line are located at the same layer, and may be integrally provided, and the fourth conductive layer 014 is used to form the write word line, so that the write word line is located at a side of the first transistor T1 remote from the substrate.

The first conductive layer 002, the second conductive layer 006 and the third conductive layer 010 are made of the same conductive material, the fourth conductive layer 014 and the fifth conductive layer 017 are made of the same conductive material, and the materials of the first conductive layer 002, the second conductive layer 006 and the third conductive layer 010 are different from those of the first conductive layer 002, the second conductive layer 006 and the third conductive layer 010, so that the structure of the first transistor is slightly different from that of the second transistor.

For the first transistor T1, the second pole 413 is located on the side of the gate 411 close to the substrate, whereas for the second transistor T2, the second pole 423 is arranged around the gate 421, which is caused by the fact that the material of the second pole 413 of the first transistor T1 is different from the material of the second pole 423 of the second transistor T2, i.e. the material of the first conductive layer 002 is different from the material of the fifth conductive layer 017. However, the fifth conductive layer 017 forms a second pole of the first transistor T1, the third conductive layer 010 forms a first pole of the first transistor, and the material of the fifth conductive layer 017 is different from that of the third conductive layer 010, that is, the first pole of the first transistor T1 is different from that of the second pole, which may cause the contact resistances of the first pole and the second pole of the first transistor T1 to be different, which may affect the performance of the first transistor T1.

In addition, in one possible implementation, the material of the first conductive layer 002 may be the same as that of the fifth conductive layer 017, that is, the fifth conductive layer 017 and the first conductive layer 002 are the same, the material of the second conductive layer 006 and the third conductive layer 010 are the same, so that the structure of the second pole of the second transistor T2 is the same as that of the second pole of the first transistor T1, and finally the second transistor T2 can form a channel layer, a gate oxide dielectric layer and a gate electrode which are the same as those of the first transistor T1, referring to fig. 17p, and thus the memory cell, the first transistor T1 and the second transistor T2 have the same structure, that is, the memory cell structure provided in fig. 11 in the foregoing example. However, as such, the manufacturing process may cause the materials of the first and second poles of the first transistor T1 and the second pole of the second transistor T2 to be different, so that the performance of both the first and second transistors T1 and T2 may be affected.

In another implementation manner of the embodiment of the present application, the material of the first pole or the second pole of the transistor may be replaced on the basis of the structure prepared as shown in fig. 17n or fig. 17p, so that the material of the first pole and the material of the second pole of the transistor are the same.

For example, referring to fig. 17q, one possible implementation is to completely remove the fifth conductive layer 017 on the basis of the structure prepared in fig. 17n, fill the space formed by removing the fifth conductive layer 017 with the same conductive material as the third conductive layer 010, etch back the space, and fill the hole with the insulating dielectric material 024, thereby forming the first transistor T1 and the second transistor T2 distributed along the vertical direction of the substrate 100, and thus forming the first electrode of the first transistor T1 with the same material as the second electrode.

Alternatively, referring to fig. 17r, on the basis of the structure prepared in fig. 17p, the fifth conductive layer 017 and the first conductive layer 002 are completely removed (here, the material of the first conductive layer 002 is the same as that of the fifth conductive layer 017), then the space where the fifth conductive layer 017 and the first conductive layer 002 are removed is filled with the same conductive material as that of the third conductive layer 010, and then the hole is filled with the insulating dielectric material 024, thereby forming the first transistor T1 and the second transistor T2 distributed in the direction perpendicular to the substrate 100, and thus the first electrode of the first transistor T1 is the same as that of the second electrode, and the first electrode of the second transistor T2 is the same as that of the second electrode.

In other possible embodiments of the present application, the first pole and the second pole of the transistor may be made of the same material in other manners, which are not limited by the examples of the present application.

In the description of the embodiments of the present application, a particular feature, structure, material, or characteristic may be combined in any one or more embodiments or examples in a suitable manner.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A memory array, comprising:

a substrate;

a plurality of memory layers formed on the substrate, the plurality of memory layers being stacked in a direction perpendicular to the substrate;

each memory layer comprises at least one memory cell, and each memory cell comprises a first transistor and a second transistor, wherein the first transistor and the second transistor are arranged along the direction perpendicular to the substrate;

The first transistor and the second transistor comprise a grid electrode, a first pole, a second pole and a channel layer for connecting the first pole and the second pole, and the grid electrode, the first pole, the second pole and the channel layer are all annular and are perpendicular to the substrate;

wherein the first pole and the second pole of the first transistor are arranged along the direction vertical to the substrate, the channel layer of the first transistor is vertical to the substrate, and the channel layer of the first transistor surrounds the grid electrode of the first transistor; a surface of the gate of the second transistor remote from the substrate is in contact with the second pole of the first transistor;

the first pole and the second pole of the second transistor are arranged along the direction perpendicular to the substrate, the channel layer of the second transistor is perpendicular to the substrate, and the channel layer of the second transistor surrounds the grid electrode of the second transistor.

2. The memory array of claim 1, wherein,

the gate of the first transistor is located on a side of the second pole of the first transistor remote from the substrate;

The first pole of the first transistor is disposed around the gate.

3. The memory array of claim 1 or 2, wherein a channel layer of the first transistor is in contact with both the first pole and the second pole of the first transistor;

the channel layer of the first transistor comprises a first part, a second part and a third part;

the first portion is located between the first pole of the first transistor and the gate of the first transistor;

the third portion is located between the second pole of the first transistor and the gate of the first transistor;

the second portion connects the first portion with the third portion.

4. A memory array according to any one of claims 1 to 3, wherein the gate of the first transistor comprises a first gate portion and a second gate portion connected, the first gate portion extending in a direction parallel to the substrate, the second gate portion extending in a direction perpendicular to the substrate;

the first electrode of the first transistor is located on a side of the first gate portion remote from the substrate.

5. The memory array of any of claims 1-4, wherein the first transistor further comprises a gate oxide dielectric layer between the channel layer of the first transistor and the gate of the first transistor, the gate oxide dielectric layer of the first transistor separating the channel layer of the first transistor from the gate of the first transistor.

6. The memory array of any of claims 1-5, wherein the first transistor further comprises a conductive film layer disposed between the channel layer and the first pole of the first transistor, the second pole of the first transistor.

7. The memory array of any of claims 1-6, wherein an axis around which the gate, the first pole, and the second pole of the second transistor are wrapped is perpendicular to the substrate;

the first and second poles of the second transistor surround the gate of the second transistor, wherein the first pole of the second transistor is located on a side away from the substrate and the second pole of the second transistor is located on a side closer to the substrate.

8. The memory array of any of claims 1-6, wherein the gate, the first pole, and the second pole of the second transistor are ring-shaped and the axis around is perpendicular to the substrate;

the gate of the second transistor is located on a side of the second pole of the second transistor remote from the substrate;

the first pole of the second transistor is disposed around the gate of the second transistor.

9. The memory array of claim 7 or 8, wherein a channel layer of the second transistor is in contact with both the first and second poles of the second transistor, the channel layer of the second transistor comprising a fourth portion, a fifth portion, and a sixth portion;

wherein the fourth portion of the channel layer of the second transistor is located between the first pole of the second transistor and the gate of the second transistor;

the sixth portion of the channel layer of the second transistor is located between the second pole of the second transistor and the gate of the second transistor;

the fifth portion connects the fourth portion with the sixth portion.

10. The memory array of any of claims 7-9, wherein the gate of the second transistor comprises a third gate portion and a fourth gate portion connected;

the extending direction of the third grid part is parallel to the substrate, and the extending direction of the fourth grid part is perpendicular to the substrate;

the first pole of the second transistor is located on a side of the third gate portion remote from the substrate;

The second pole of the second transistor is located on a side of the third gate portion facing the substrate.

11. The memory array of any of claims 7-10, wherein the second transistor further comprises a gate oxide dielectric layer, the gate oxide dielectric layer of the second transistor being located between the channel layer of the second transistor and the gate of the second transistor, the gate oxide dielectric layer of the second transistor separating the channel layer of the second transistor from the gate of the second transistor.

12. The memory array of any of claims 7-11, wherein the second transistor further comprises a conductive film layer disposed between the channel layer of the second transistor and the first pole of the second transistor, the second pole of the second transistor.

13. The memory array of any of claims 1-12, wherein each of the memory layers further comprises a write word line, a write bit line, a read word line, and a read bit line;

the gate of the first transistor is connected with the write word line, the first pole of the first transistor is connected with the write bit line, the second pole of the first transistor is connected with the gate of the second transistor, the first pole of the second transistor is connected with the read word line, and the second pole of the second transistor is connected with the read bit line.

14. The memory array of claim 13, wherein the write word line is located on a side of the first transistor remote from the substrate, and the gate of the first transistor is in contact with the write word line away from a surface of the substrate;

a film layer position of the write bit line in a direction perpendicular to the substrate is located at the same layer as the first pole of the first transistor;

the film layer position of the read word line in the direction perpendicular to the substrate is positioned on the same layer as the first electrode of the second transistor;

and the read bit line is positioned on the same layer with the second pole of the second transistor in the position of the film layer in the direction perpendicular to the substrate.

15. The memory array of claim 13 or 14, wherein the memory layer comprises a plurality of memory cells;

the write word line and the read word line extend along a first direction parallel to the substrate; the write bit line and the read bit line extend along a second direction parallel to the substrate;

the write word line is electrically connected with the grid electrodes of the first transistors of the memory cells in the first direction;

the write bit line electrically connects first poles of the first transistors of the plurality of the memory cells located in the second direction;

The read word line is electrically connected to first poles of second transistors of a plurality of memory cells located in the first direction;

the read bit line is electrically connected to a second pole of a second transistor of the plurality of memory cells located in the second direction.

16. The memory array of any of claims 13-15, wherein the write bit line is integral with the first pole of the first transistor;

the read word line is integrally arranged with the first pole of the second transistor;

the read bit line is integral with the second pole of the second transistor.

17. A memory, comprising:

the memory array of any one of claims 1-16;

and the controller is electrically connected with the storage array and is used for controlling the reading and writing of the storage array.

18. A method for manufacturing a memory, the method comprising:

forming a second pole of a second transistor, a first pole of a second transistor, a second pole of a first transistor and a first pole of a first transistor in a direction perpendicular to a substrate, wherein the second pole of the second transistor, the first pole of the second transistor, the second pole of the first transistor and the first pole of the first transistor are all annular and perpendicular to the substrate;

Forming a channel layer of the second transistor and a channel layer of the first transistor, wherein the channel layer of the first transistor and the channel layer of the second transistor are annular and are perpendicular to the substrate, and the channel layer of the first transistor is connected with a first pole and a second pole of the first transistor; the channel layer of the second transistor is connected with the first pole and the second pole of the second transistor;

forming a gate of the second transistor and a gate of the first transistor, the channel layer of the first transistor surrounding the gate of the first transistor; the channel layer of the second transistor surrounds the gate of the second transistor, the gate of the second transistor being in contact with the second pole of the first transistor away from the surface of the substrate.

19. The method of claim 18, wherein forming the channel layer of the first transistor comprises: forming a first portion, a second portion, and a third portion of the channel layer of the first transistor, the first portion being in contact with the first pole of the first transistor; the third portion is in contact with the second pole of the first transistor; the third portion connects the first portion and the third portion.

20. The method of claim 18 or 19, wherein forming the gate of the first transistor comprises:

forming a first gate portion of the gate, an extension direction of the first gate portion being parallel to the substrate;

and forming a second gate part connected with the first gate part, wherein the extending direction of the second gate part is perpendicular to the substrate.

21. The method of any of claims 18-20, wherein forming the channel layer of the second transistor comprises:

forming a fourth portion, a fifth portion, and a sixth portion of the channel layer of the second transistor, the fourth portion being in contact with the first pole of the second transistor; the sixth portion is in contact with the second pole of the first transistor; the fifth portion connects the fourth portion with the sixth portion.

22. The method of any of claims 18-21, wherein forming the gate of the second transistor comprises:

forming a third gate portion of the gate, an extension direction of the third gate portion being parallel to the substrate;

and forming a fourth gate portion connected with the third gate portion, wherein the extending direction of the fourth gate portion is perpendicular to the substrate.

23. The method according to any one of claims 18 to 22, further comprising:

forming a writing line, a writing bit line, a reading word line and a reading bit line;

24. The method of claim 23, wherein forming a write word line, a write bit line, a read word line, and a read bit line comprises:

forming the writing line on one side of the first transistor away from the substrate, wherein the surface of the gate of the first transistor away from the substrate is contacted with the writing line;

forming the write bit line in a film layer in a direction perpendicular to the substrate, the same layer as the first pole of the first transistor;

forming the read word line in the same layer as the first electrode of the second transistor in a film layer in a direction perpendicular to the substrate;

the read bit line is formed in the same layer as the second pole of the second transistor in a film layer in a direction perpendicular to the substrate.

25. The method of claim 23 or 24, wherein forming the write word line, the write bit line, the read word line, and the read bit line further comprises:

the write bit line is integrally disposed with the first pole of the first transistor;

the read bit line is integral with the second pole of the second transistor.

26. An electronic device, comprising: a processor and memory as in claim 17, wherein the processor and the memory are electrically connected.