CN117858497A

CN117858497A - Memory, manufacturing method thereof and memory system

Info

Publication number: CN117858497A
Application number: CN202211184253.XA
Authority: CN
Inventors: 邵光速
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-09-27
Filing date: 2022-09-27
Publication date: 2024-04-09

Abstract

The embodiment of the disclosure provides a memory, a manufacturing method thereof and a memory system, wherein the memory comprises: a first substrate having a first side and a second side disposed opposite in a first direction; the first direction is the thickness direction of the first substrate; a first peripheral circuit disposed on the first side; a second peripheral circuit disposed on the second side; the first memory cell array is arranged on one side of the first peripheral circuit, which is far away from the second peripheral circuit, and is electrically connected with the first peripheral circuit; the second memory cell array is arranged on one side, far away from the first peripheral circuit, of the second peripheral circuit and is electrically connected with the second peripheral circuit.

Description

Memory, manufacturing method thereof and memory system

Technical Field

The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a memory, a method of manufacturing the same, and a memory system.

Background

With the rapid increase of popularity of electronic devices and the vigorous development of the electronic device market, electronic products are increasingly required to be miniaturized and thinned while having high performance, multiple functions, high reliability and convenience. Such demands place higher demands on the integration level and reliability of the memory.

Disclosure of Invention

Based on this, in order to solve one or more of the related technical problems, embodiments of the present disclosure provide a memory, a manufacturing method thereof, and a memory system.

According to an embodiment of the present disclosure, there is provided a memory including:

a first substrate having a first side and a second side disposed opposite in a first direction; the first direction is the thickness direction of the first substrate;

a first peripheral circuit disposed on the first side;

a second peripheral circuit disposed on the second side;

the first memory cell array is arranged on one side of the first peripheral circuit, which is far away from the second peripheral circuit, and is electrically connected with the first peripheral circuit;

the second memory cell array is arranged on one side, far away from the first peripheral circuit, of the second peripheral circuit and is electrically connected with the second peripheral circuit.

In the above aspect, the first memory cell array and/or the second memory cell array includes: a plurality of first-type memory cells arranged in an array along a second direction and a third direction; each first type of storage unit comprises: control transistor and capacitance; wherein the amount of charge stored in the capacitance is changed by the control transistor; the second direction and the third direction intersect and are both perpendicular to the first direction.

In the above scheme, the first memory cell array and/or the second memory cell array includes: a memory cell structure, the memory cell structure comprising: a first bit line, a first control transistor, a capacitor, a second control transistor, a second bit line, and a first word line and a second word line stacked in the first direction; wherein the first bit line and the second bit line extend along the second direction, and the first word line and the second word line extend along the third direction;

one of a source electrode or a drain electrode of the first control transistor is connected with the first bit line, the other of the source electrode or the drain electrode is connected with one electrode of the capacitor, and a grid electrode is connected with the first word line;

one of a source electrode or a drain electrode of the second control transistor is connected with the second bit line, the other of the source electrode or the drain electrode is connected with the other electrode of the capacitor, and a gate electrode is connected with the second word line.

In the above scheme, the first memory cell array and/or the second memory cell array includes: a memory cell structure, the memory cell structure comprising: a first bit line, a first control transistor, a first capacitor, a second control transistor, a second bit line, a first word line, a second word line, and a second bit line stacked in the first direction; wherein the first bit line and the second bit line extend along the second direction, and the first word line and the second word line extend along the third direction;

One of a source electrode or a drain electrode of the first control transistor is connected with the first bit line, the rest of the source electrode or the drain electrode is connected with one electrode of the first capacitor, and a grid electrode is connected with the first word line;

one of a source electrode or a drain electrode of the second control transistor is connected with the second bit line, the other of the source electrode or the drain electrode is connected with one electrode of the second capacitor, and a gate electrode is connected with the second word line.

In the above scheme, the first memory cell array and/or the second memory cell array includes: and a plurality of memory cell structures stacked along the first direction, wherein the bit line is shared between two adjacent memory cell structures.

In the above scheme, the first memory cell array and/or the second memory cell array includes: a first capacitor, a first control transistor, a bit line, a second control transistor, a second capacitor, and a first word line and a second word line stacked in the first direction; wherein the bit line extends along the second direction, and the first word line and the second word line extend along the third direction;

One of a source or a drain of the second control transistor is connected to the bit line, the remaining one of the source or the drain is connected to one electrode of the second capacitor, and a gate is connected to the second word line.

In the above aspect, the first memory cell array and/or the second memory cell array includes: a plurality of second-class memory cells arranged in an array along a second direction and a third direction; each of the second type of storage units comprises: a read transistor and a write transistor; wherein a resistance state between a source and a drain of the read transistor is changed by the write transistor; the second direction and the third direction intersect and are both perpendicular to the first direction.

In the above aspect, the first memory cell array and/or the second memory cell array includes: a read word line, a read transistor, a write word line, a read bit line, and a write bit line stacked along the first direction; wherein the read word line and the write bit line extend along the second direction, and the write word line and the read bit line extend along the third direction;

one of a source or a drain of the read transistor is connected to the read word line, and the remaining one of the source or the drain is connected to the read bit line;

One of a source or a drain of the write transistor is connected to a gate of the read transistor, the remaining one of the source or the drain is connected to the write bit line, and the gate is connected to the write gate.

In the above solution, the memory further includes:

one or more first interconnect layers between the first peripheral circuitry and the first array of memory cells; the first peripheral circuit is electrically connected with the first memory cell array through the one or more first interconnection layers;

one or more second interconnect layers between the second peripheral circuitry and the second array of memory cells; the second peripheral circuitry is electrically connected to the second array of memory cells through the one or more second interconnect layers.

In the above solution, the memory further includes:

a plurality of first conductive pillars; the first memory cell array and the first peripheral circuit are electrically connected with the one or more first interconnection layers through the plurality of first conductive pillars;

a plurality of second conductive pillars; the second memory cell array and the second peripheral circuit are electrically connected to the one or more second interconnect layers through the plurality of second conductive pillars.

In the above aspect, the first peripheral circuit and/or the second peripheral circuit includes:

a ridge structure located on the first side and/or the second side surface of the first substrate, wherein an isolation structure is arranged between the ridge structures; and

and the source and drain ends of the transistor are connected with the memory cell arrays on the corresponding sides.

In the above solution, the memory further includes:

a second substrate disposed on a side of the first memory cell array away from the first peripheral circuit;

and a third substrate disposed on a side of the second memory cell array remote from the second peripheral circuit.

According to an embodiment of the present disclosure, there is provided a memory system including: a memory as described in the above embodiments of the present disclosure; and

and the memory controller is connected with the memory and is used for controlling the memory.

According to an embodiment of the present disclosure, there is provided a method for manufacturing a memory, including:

forming a first peripheral circuit on a first side of a first substrate;

forming a first memory cell array connected to the first peripheral circuit on the first peripheral circuit;

forming a second peripheral circuit on a second side of the first substrate; the first side and the second side are oppositely arranged along the thickness direction of the first substrate;

And forming a second memory cell array connected with the second peripheral circuit on one side of the second peripheral circuit away from the first peripheral circuit.

forming a first peripheral circuit on a first side of a first substrate;

forming a first memory cell array on a second substrate;

forming a second memory cell array on a third substrate;

bonding the first substrate to the second substrate such that a first array of memory cells is located on a side of the first peripheral circuitry remote from the second peripheral circuitry; the first memory cell array is electrically connected with the first peripheral circuit;

bonding the first substrate to the third substrate such that a second array of memory cells has the second peripheral circuitry away from a side of the first peripheral circuitry; the second memory cell array is electrically connected to the second peripheral circuit.

In the above aspect, the method of forming the first peripheral circuit/the second peripheral circuit includes:

Forming a ridge structure on a first side/second side surface of the first substrate, wherein an isolation structure is formed between the ridge structures;

and forming a transistor on the ridge structure, wherein both ends of a source and a drain of the transistor are connected with the memory cell arrays on the corresponding sides.

In the above scheme, the method further comprises:

forming one or more first interconnect layers between the first peripheral circuit and the first memory cell array; the first peripheral circuit is electrically connected with the first memory cell array through the one or more first interconnection layers;

forming one or more second interconnect layers between the second peripheral circuit and the second memory cell array; the second peripheral circuitry is electrically connected to the second array of memory cells through the one or more second interconnect layers.

In the above scheme, the method further comprises:

etching the semiconductor layer where the first memory cell array is located and the dielectric layer around the first peripheral circuit, and filling conductive materials to form a plurality of first conductive columns, wherein the first memory cell array and the first peripheral circuit are electrically connected with the one or more first interconnection layers through the plurality of first conductive columns;

Etching the semiconductor layer where the second memory cell array is located and the dielectric layer around the second peripheral circuit, and filling conductive materials to form a plurality of second conductive columns, wherein the second memory cell array and the second peripheral circuit are electrically connected with the one or more second interconnection layers through the second conductive columns.

In various embodiments of the present disclosure, a first peripheral circuit and a first memory cell array connected to the first peripheral circuit are disposed on a first side of a first substrate, and a second peripheral circuit and a second memory cell array connected to the second peripheral circuit are disposed on a second side of the first substrate. Thus, the memory portion and the corresponding peripheral portion can be formed on both sides of the first substrate, and the integration level of the memory can be improved.

Drawings

FIG. 1a is a schematic diagram of a first type of memory cell according to an embodiment of the disclosure;

FIG. 1b is an enlarged schematic diagram of the first type memory cell in FIG. 1 a;

FIG. 2a is a schematic diagram of a memory cell array according to an embodiment of the disclosure;

FIG. 2b is an enlarged schematic diagram of the memory cell of FIG. 2 a;

FIG. 3a is a schematic diagram illustrating another memory cell array according to an embodiment of the disclosure;

FIG. 3b is an enlarged schematic diagram of the memory cell of FIG. 3 a;

FIG. 4a is a schematic diagram illustrating a structure of another memory cell array according to an embodiment of the disclosure;

FIG. 4b is an enlarged schematic view of a portion of the memory cell array of FIG. 4 a;

FIG. 5a is a schematic diagram of a memory structure with a 2T0C memory cell according to an embodiment of the disclosure;

FIG. 5b is an enlarged schematic diagram of the second type memory cell of FIG. 5 a;

FIG. 5c is a schematic circuit diagram of the memory cell array corresponding to FIG. 5 b;

FIG. 6 is a flow chart of a method for fabricating a memory according to an embodiment of the disclosure;

FIGS. 7 a-7 d are schematic cross-sectional views illustrating a process for fabricating a memory device according to embodiments of the present disclosure;

FIG. 8 is a flow chart of another method for fabricating a memory according to an embodiment of the disclosure;

fig. 9 a-9 f are schematic cross-sectional views illustrating a fabrication process of another memory device according to an embodiment of the present disclosure.

In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components.

The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.

Detailed Description

In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The present disclosure is described more specifically in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the disclosure.

It will be understood that the meanings of "on … …", "over … …" and "over … …" in this disclosure should be interpreted in the broadest manner so that "on … …" means not only that it is "on" something with no intervening features or layers therebetween (i.e., directly on something), but also that it is "on" something with intervening features or layers therebetween.

Further, spatially relative terms such as "on … …," "above … …," "above … …," "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated for ease of description. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In the presently disclosed embodiments, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entirety of the underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal facing at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along an inclined surface. The layer may comprise a plurality of sub-layers. For example, the interconnect layer may include one or more conductors and contact sublayers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sublayers.

In the presently disclosed embodiments, the terms "first," "second," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. The technical solutions described in the embodiments of the present disclosure may be arbitrarily combined without any conflict.

In the following embodiments, the first direction is a direction of the thickness of the first substrate, the second direction and the third direction intersect and are perpendicular to the first direction, that is, an included angle between the second direction and the third direction is any angle between 0-90 degrees. For ease of understanding, the second direction is described as being perpendicular to the third direction. Illustratively, the first direction is the Z-axis direction shown in the drawings; the second direction is the X-axis direction shown in the drawing; the third direction is the Y-axis direction shown in the drawings. It should be noted, however, that the description of the directions in the following examples is only for illustrating the present disclosure and is not intended to limit the scope of the present disclosure.

In addition, various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details have been exaggerated for the sake of clarity of presentation and certain details may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.

Memory referred to in embodiments of the present disclosure includes, but is not limited to, dynamic random access memory (DRAM, dynamic Random Access Memory). It should be noted, however, that the description of the embodiments below with respect to the dynamic random access memory is only for illustrating the present disclosure, and is not intended to limit the scope of the present disclosure.

The dynamic random access memory may include peripheral circuitry and an array of memory cells; wherein the peripheral circuitry may comprise any suitable digital, analog, and/or mixed signal circuitry configured to facilitate various operations of a memory implementation read operations, write operations, erase operations, and the like. For example, the peripheral circuits may include control logic (e.g., control circuits or controllers), data buffers, decoders (decoders may also be referred to as decoders), drivers and read and write circuits and so forth. When the control logic receives the read-write operation command and the address data, under the action of the control logic, the decoder can apply corresponding voltages obtained from the driver to corresponding bit lines and word lines based on the decoded address so as to realize the read-write of the data and perform data interaction with the outside through the data buffer.

The memory cell array may include a plurality of memory cells; each memory cell may include a Transistor and a Capacitor, that is, the dynamic random access memory is a 1 Transistor (T) and 1 Capacitor (C, capacitor) (1T 1C) architecture; two Transistor structures may also be included, i.e., a dynamic random access memory is a 2 Transistor (T) and 0 Capacitor (C) (2T 0C) architecture. It should be understood that whether the dynamic random access memory is a 1T1C architecture or a 2T0C architecture, the main working principle is to use the capacitance or the amount of charge stored in a Storage Node (SN) between two transistors to represent whether a binary bit is l or 0.

However, in forming a memory, a peripheral circuit is generally disposed in parallel with a memory cell array on the same side of a substrate, so that an area for forming the memory cell array in the substrate is reduced and a memory capacity is reduced. Further, with the miniaturization development of the memory, it is difficult to form a memory cell array in a multi-layered stacked arrangement, and further, even if a memory cell array in a multi-layered stacked arrangement is formed, corresponding problems may occur due to the multi-layered stacking, such as difficulty in wiring of the multi-layered memory cell array, an increase in resistance due to an excessively long lead length, or a problem that the requirement of the multi-layered memory cell array cannot be satisfied due to a small control range of the peripheral circuit.

Based on this, in order to solve one or more of the above problems, embodiments of the present disclosure provide a memory capable of reducing process difficulty while improving integration density; wherein the memory comprises:

a first peripheral circuit disposed on the first side;

a second peripheral circuit disposed on the second side;

Here, the first substrate may be any base material known to those skilled in the art for carrying semiconductor integrated circuit constituent elements, and illustratively, the constituent materials of the first substrate may include silicon (Si), germanium (Ge), silicon germanium (SiGe), and may further include silicon-on-insulator (Silicon on Insulator, SOI) or germanium-on-insulator (Germanium on Insulator, GOI), and the like. In some embodiments, the first substrate may be doped to form a P-well (for an N-type MOSFET) or an N-well (for a P-type MOSFET) depending on the type of memory device.

Here, referring to fig. 1a, the first substrate 10 has a first side 101 and a second side 102 disposed opposite in a Z-axis direction, which is a thickness direction of the first substrate. The first peripheral circuit 103 is arranged on a first side 101 of the first substrate and the second peripheral circuit 104 is arranged on a second side 102 of the first substrate. The first memory cell array 105 is disposed on the first side 101 of the first substrate and is connected to the first peripheral circuit 103. A second array of memory cells 106 is disposed on the second side 102 of the first substrate and is connected to the second peripheral circuit 104. Therefore, the peripheral circuits and the corresponding memory cell arrays are arranged on the two sides of the first substrate, and the storage density of the memory is further improved.

In some embodiments, the first peripheral circuit 103 may be coupled to the first memory cell array 105 by corresponding bit lines, word lines, source lines, lower select gate lines at the source terminal, and upper select gate lines at the drain terminal; likewise, the second peripheral circuit 104 may also be coupled to the second memory cell array 106 by corresponding bit lines, word lines, source lines, lower select gate lines at the source terminal, and upper select gate lines at the drain terminal.

Here, the first and second peripheral circuits 103 and 104 may each include any suitable digital, analog, and/or mixed signal circuits that facilitate various operations of a memory implementation read operation, write operation, erase operation, etc., such that voltage signals and/or current signals may be applied to the corresponding first and second memory cell arrays 105 and 106 through the corresponding bit lines, word lines, source lines, lower selection gate lines, and upper selection gate lines, and voltage signals and/or current signals may be sensed from each of the corresponding first and second memory cell arrays 105 and 106 to facilitate the corresponding first and second memory cell arrays 105 and 106 to perform operations.

In some embodiments, the first peripheral circuit 103 and the second peripheral circuit 104 may each include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology, such as page buffers/sense amplifiers, column decoders/bit line drivers, row decoders/word line drivers, voltage generators, control logic, registers, interfaces, and data buses. It should be appreciated that in some examples, additional peripheral circuitry not shown herein may also be included.

The page buffer/sense amplifier may be configured to read data from and program (write) data to a corresponding memory cell array according to a control signal from the control logic. In one example, the page buffer/sense amplifier may store a page of program data (write data) to be programmed into one page of the corresponding memory cell array. In another example, the page buffer/sense amplifier may perform a program verify operation to ensure that data has been properly programmed to the array of memory cells coupled to the selected word line. In yet another example, the page buffer/sense amplifier may also sense a low power signal from a bit line representing a data bit stored in a corresponding memory cell array and amplify a small voltage swing to an identifiable logic level in a read operation. The column decoder/bit line driver may be configured to be controlled by the control logic and select one or more memory cells in the memory cell array by applying the bit line voltage generated from the voltage generator. The registers may be coupled to the control logic and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit.

In some embodiments, the methods of forming the first peripheral circuit 103, the second peripheral circuit 104, the first memory cell array 105, the second memory cell array 106 include, but are not limited to, physical vapor deposition (Physical Vapor Deposition, PVD) processes, chemical vapor deposition (Chemical Vapor Deposition, CVD) processes, atomic layer deposition (Atomic Layer Deposition, ALD) processes, doping processes, and the like.

In order to more clearly understand the structural layout of the present solution, the following describes the structural layout of the first memory cell array and/or the second memory cell array as a first type architecture (1T 1C architecture) and a second type architecture (2T 0C architecture) in detail with reference to the accompanying drawings.

The following are embodiments in which the first memory cell array and/or the second memory cell array are of a first type of architecture:

in some embodiments, the first memory cell array and/or the second memory cell array comprises: a plurality of first-type memory cells arranged in an array along a second direction and a third direction; each first type of storage unit comprises: control transistor and capacitance; wherein the amount of charge stored in the capacitance is changed by the control transistor; the second direction and the third direction intersect and are both perpendicular to the first direction.

Here, referring to fig. 1a, the first memory cell array 105 and/or the second memory cell array 106 includes a plurality of first-type memory cells 107, the plurality of first-type memory cells 107 being arranged in an array in an X-axis direction and a Y-axis direction, each first-type memory cell 107 including a control transistor 1071 and a capacitor 1072; the control transistor 1071 is used for controlling the turn-off and turn-off of the capacitor to change the charge amount stored in the capacitor, thereby realizing the storage of data.

In some embodiments, referring to fig. 1b, the control transistor 1071 may include a Source (S), a Drain (D, drain), and a Gate (G, gate); the region between the drain and the source is the Channel region (C). The gate may be located at one side of the channel region; or may be located on opposite sides of the channel region; but may also be located around the channel region. The specific position can be set according to the actual requirement of the transistor; here and hereinafter, the gate electrode is illustrated as being located at opposite sides of the channel region.

It should be noted that referring to fig. 1b, the control transistor 1071 may further include a Gate Oxide (Gate Oxide, also called Gate dielectric layer) between the Gate and the channel region, wherein the Gate Oxide is made of a material with a wide band gap and a high dielectric constant, or a material suitable for manufacturing a device with a very small size, such as HfO ₂ 。

In some embodiments, referring to fig. 1b, the capacitor 1072 may include a first electrode layer L1, a dielectric layer L2 covering the first electrode layer, and a second electrode layer L3 covering the dielectric layer. The first electrode layer L1 is used as one electrode of the capacitor 1072, and the second electrode layer L3 is used as the other electrode of the capacitor 1072. Namely, one end of the first-type memory cell is a first electrode layer of a capacitor; the other end of the storage unit is a second electrode layer of the capacitor. Here, the first electrode layer of the capacitor is connected to the source or the drain in the control transistor 1071; the second electrode layer of the capacitor is connected to a connection structure in the memory, such as an interconnect layer.

Here, the materials of the first electrode layer and the second electrode layer each include, but are not limited to, titanium nitride (TiN), and the material of the dielectric layer includes a High dielectric constant (High-K) material, wherein the High dielectric constant material generally refers to a material having a dielectric constant higher than 3.9, and is generally significantly higher than this value. In some specific examples, the material of the dielectric layer may include, but is not limited to, hafnium oxide (HfO ₂ ) The method comprises the steps of carrying out a first treatment on the surface of the Methods of forming the first electrode layer, the dielectric layer, the second electrode layer include, but are not limited to, PVD, CVD, ALD and the like.

It should be noted that fig. 1a is a schematic structural diagram of a first type of memory cell according to an embodiment of the disclosure; fig. 1b is an enlarged schematic diagram of the first type memory cell 107 in fig. 1 a.

In some embodiments, the first memory cell array and/or the second memory cell array comprises: a memory cell structure, the memory cell structure comprising: a first bit line, a first control transistor, a capacitor, a second control transistor, a second bit line, and a first word line and a second word line stacked in the first direction; wherein the first bit line and the second bit line extend along the second direction, and the first word line and the second word line extend along the third direction;

Referring to fig. 2a, 2b, the first memory cell array 105 and/or the second memory cell array 106 includes a plurality of memory cell structures 108, and each memory cell structure 108 may include a first bit line 1081, a first control transistor 1082, a capacitor 1083, a second control transistor 1084, and a second bit line 1085 arranged along the Z-axis direction, and each memory cell structure 108 further includes a first word line 1086 and a second word line 1087 extending along the Y-axis direction. Wherein, the first control transistor 1082 and the second control transistor 1084 each include a source S, a drain D, and a gate G; the capacitor 1083 includes a first electrode layer L1, a dielectric layer L2, and a second electrode layer L3.

Illustratively, referring to FIG. 2b, the first bit line 1081 is coupled to the source of the first control transistor 1082, the drain of the first control transistor 1082 is coupled to the first electrode layer of the capacitor 1083, the second electrode of the capacitor 1083 is coupled to the drain of the second control transistor 1084, and the source of the second control transistor 1084 is coupled to the second bit line 1085; the gate of the first control transistor 1082 is connected to the first word line 1086, and the gate of the second control transistor 1084 is connected to the second word line 1087; it should be noted that, in other embodiments, the gate of the first control transistor 1082 is the first word line 1086; the gate of the second control transistor 1084 is the second word line 1087.

Here, the voltage control transistors (first control transistor 1082, second control transistor 1084) are turned on or off by the word lines (first word line 1086, second word line 1087), and the bit lines (first bit line 1081, second bit line 1085) are used to perform a read or write operation on the transistors (first control transistor 1082, second control transistor 1084) when the transistors are turned on.

Methods of forming the first bit line 1081, the first control transistor 1082, the capacitor 1083, the second control transistor 1084, the second bit line 1085, the first word line 1086, and the second word line 1087 include, but are not limited to, PVD, CVD, ALD, and the like.

It should be noted that fig. 2a is a schematic structural diagram of a memory cell array according to an embodiment of the disclosure; fig. 2b is an enlarged schematic diagram of the memory cell structure 108 of fig. 2 a.

It should be noted that, in this embodiment, the first control transistor and the second control transistor share a capacitor, so that the process steps can be reduced and the manufacturing efficiency can be improved.

In some embodiments, the first memory cell array and/or the second memory cell array comprises: a memory cell structure, the memory cell structure comprising: a first bit line, a first control transistor, a first capacitor, a second control transistor, a second bit line, a first word line, a second word line, and a second bit line stacked in the first direction; wherein the first bit line and the second bit line extend along the second direction, and the first word line and the second word line extend along the third direction;

Referring to fig. 3a, the first memory cell array 105 and/or the second memory cell array 106 includes a plurality of memory cell structures 109, and each memory cell structure 109 may include a first bit line 1091, a first control transistor 1092, a first capacitor 1093, a second capacitor 1094, a second control transistor 1095, and a second bit line 1096 stacked in the Z-axis direction, and each memory cell structure 109 further includes a first word line 1097 and a second word line 1098 extending in the Y-axis direction. Wherein, the first control transistor 1092 and the second control transistor 1095 each include a source S, a drain D, and a gate G; the first capacitor 1093 and the second capacitor 1094 each include a first electrode layer L1, a dielectric layer L2, and a second electrode layer L3.

For example, referring to fig. 3b, the source of the first control transistor 1092 is connected to the first bit line 1091, the drain of the first control transistor 1092 is connected to the first electrode layer of the first capacitor 1093, the gate of the first control transistor 1092 is connected to the first word line 1097, and in other embodiments, the gate of the first control transistor 1092 is the first word line 1097. The source of the second control transistor 1095 is connected to the second bit line 1096, the drain of the second control transistor 1095 is connected to the first electrode layer of the second capacitor 1094, the gate of the second control transistor 1095 is connected to the second word line 1098, and in other embodiments, the gate of the second control transistor 1095 is the second word line 1098.

It should be noted that fig. 3a is a schematic structural diagram of another memory cell array according to an embodiment of the disclosure; fig. 3b is an enlarged schematic diagram of the memory cell structure 109 in fig. 3 a.

It should be noted that, in this embodiment, the first control transistor and the second control transistor correspond to the first capacitor and the second capacitor respectively, so that flexibility of read-write operation can be improved, and meanwhile, storage density is improved.

In some embodiments, the first memory cell array and/or the second memory cell array comprises: and a plurality of memory cell structures stacked along the first direction, wherein the bit line is shared between two adjacent memory cell structures.

For example, referring to fig. 2a, when the first memory cell array 105 and/or the second memory cell array 106 includes a plurality of memory cell structures 108 stacked in the Z-axis direction, two memory cell structures 108 adjacent in the Z-axis direction share one bit line 1085.

For example, referring to fig. 3a, when the first memory cell array 105 and/or the second memory cell array 106 include a plurality of memory cell structures 109 stacked in the Z-axis direction, two memory cell structures 109 adjacent in the Z-axis direction share one bit line 1091.

In some embodiments, the first memory cell array and/or the second memory cell array comprises: a first capacitor, a first control transistor, a bit line, a second control transistor, a second capacitor, and a first word line and a second word line stacked in the first direction; wherein the bit line extends along the second direction, and the first word line and the second word line extend along the third direction;

Referring to fig. 4a, 4b, in the first memory cell array 105 and/or the second memory cell array 106, the first capacitor 1101 and the second capacitor 1105 each include a first electrode layer L1, a dielectric layer L2 and a second electrode layer L3, and the first control transistor 1102 and the second control transistor 1104 each include a source S, a drain D and a gate G. The source of the first control transistor 1102 is connected to the bit line 1103, the drain of the first control transistor 1102 is connected to the first electrode layer of the first capacitor 1101, and the gate of the first control transistor 1102 is connected to the first word line 1106, and in other embodiments, the gate of the first control transistor 1102 is the first word line 1106. The source of the second control transistor 1104 is connected to the bit line 1103, the drain of the second control transistor 1104 is connected to the first electrode layer of the second capacitor 1105, and the gate of the second control transistor 1104 is connected to the second word line 1107, and in other embodiments, the gate of the second control transistor 1104 is the second word line 1107.

It should be noted that fig. 4a is a schematic structural diagram of another memory cell array according to an embodiment of the disclosure; FIG. 4b is an enlarged schematic diagram of a partial structure of the memory cell array of FIG. 4 a.

It should be noted that, in this embodiment, the first control transistor and the second control transistor share one bit line, so that the process steps for forming the bit line can be reduced, the difficulty of wiring the bit line can be reduced, and the process window can be improved.

The following are embodiments in which the first memory cell array and/or the second memory cell array are of a second type of structure:

in some embodiments, the first memory cell array and/or the second memory cell array comprises: a plurality of second-class memory cells arranged in an array along a second direction and a third direction; each of the second type of storage units comprises: a read transistor and a write transistor; wherein a resistance state between a source and a drain of the read transistor is changed by the write transistor; the second direction and the third direction intersect and are both perpendicular to the first direction.

Referring to fig. 5a, the first memory cell array 105 and/or the second memory cell array 106 includes a plurality of second type memory cells 201, and the plurality of second type memory cells 201 are arranged in an array along an X-axis direction and a Y-axis direction. Referring to fig. 5b and 5c, each of the second type memory cells 201 may include two transistors, a read transistor 202 and a write transistor 203, wherein a storage node SN is formed between the read transistor 202 and the write transistor 203; here, both the read transistor and the write transistor may be used to change a resistance state between the source and the drain of the read transistor to achieve reading and writing of data.

In some embodiments, the first memory cell array and/or the second memory cell array comprises: a Read Word Line (RWL), a Read transistor, a Write Word Line (WWL, write Word Line), a Read Bit Line (RBL, read Bit Line), a Write Bit Line (WBL, write Bit Line) stacked in the first direction; wherein the read word line and the write bit line extend along the second direction, and the write word line and the read bit line extend along the third direction;

Referring to fig. 5b and 5c, the read word line 204 and the write bit line 207 are parallel to each other and each extend in the X-axis direction, and the write word line 205 and the read bit line 206 are parallel to each other and each extend in the Y-axis direction. Wherein the source of the read transistor 202 is connected to the read word line 204, and the drain of the read transistor 202 is connected to the read bit line 206; the gate of the read transistor 202 is connected to the source of the write transistor 203, the drain of the write transistor 203 is connected to the write bit line 207, and the gate of the write transistor 203 is connected to the write word line 205.

It should be noted that, fig. 5a is a memory with a 2T0C memory cell architecture, fig. 5b is an enlarged schematic diagram of the second type memory cell 201 in fig. 5a, and fig. 5C is a schematic diagram of a circuit structure corresponding to fig. 5 b.

It should be noted that, in the embodiment, the first control transistor and the second control transistor are configured as a 2T0C architecture, wherein the charge retention time of the 2T0C architecture is longer than that of the capacitor in the conventional 1T1C architecture, the refresh frequency is lower, and the memory power consumption is lower.

In some embodiments, the memory further comprises:

Referring to fig. 2a and 5a, one or more first interconnection layers 301 are further disposed between the first peripheral circuit 103 and the first memory cell array 105 for making electrical connection between the first peripheral circuit 103 and the first memory cell array 105; and one or more second interconnection layers 302 are also disposed between the second peripheral circuit 104 and the second memory cell array 106, for implementing electrical connection between the second peripheral circuit and the second memory cell array, where the first interconnection layer 301 and the second interconnection layer 302 may each include a sub-interconnection layer, and the plurality of sub-interconnection layers are connected by one or more metal electrodes (or referred to as electrodes in layers) 303, where the first interconnection layer 301 includes three metal electrodes 303, and the second interconnection layer 302 includes two metal electrodes 303. Here, the constituent materials of the first interconnect layer 301 and the second interconnect layer 302 may be, but not limited to, metals such as copper or tungsten, and the like, and the method of forming the first interconnect layer 301 and the second interconnect layer includes, but is not limited to, PVD, CVD, ALD and the like.

In some embodiments, the memory further comprises: a plurality of first conductive pillars; the first memory cell array and the first peripheral circuit are electrically connected with the one or more first interconnection layers through the plurality of first conductive pillars;

For example, referring to fig. 5a, the first conductive pillar 401 and the second conductive pillar 402 may be used to connect the peripheral circuit and the memory cell array on the same side, so that on one hand, the connection reliability between the memory cell and the peripheral circuit on the same side may be improved, and on the other hand, the difficulty in processing the leads of the memory cells in the plurality of memory cell arrays stacked may be reduced. The materials of the first conductive pillar 401 and the second conductive pillar 402 include, but are not limited to, metals, such as copper or tungsten. Methods of forming the first conductive pillars 401 and the second conductive pillars 402 include, but are not limited to, PVD, CVD, ALD, etc.

The first memory cell array and the second memory cell array are formed in the semiconductor layer, and the first peripheral circuit and the second peripheral circuit are formed in the dielectric layer, where the semiconductor layer and the dielectric layer may be the same as or different from the first substrate, and the constituent materials of the semiconductor layer and the dielectric layer include, but are not limited to, silicon.

In some embodiments, referring to fig. 5a, the first peripheral circuit and/or the second peripheral circuit comprises:

a ridge structure 501 on the first side and/or the second side surface of the first substrate, wherein an isolation structure 601 is provided between the ridge structures; and

and a transistor 701 on the ridge structure 501, wherein both ends of the source and the drain of the transistor are connected with the memory cell array on the corresponding side.

Furthermore, the surface of the ridge structure 501 is provided with positioning means (not shown) by means of which an electrical connection of the ridge structure 501 to external structures, such as the first interconnect layer 301 and the second interconnect layer 302, is achieved.

Illustratively, referring to FIG. 5a, the source or drain of the transistor 701 on a first side of the first substrate is connected to the first memory cell array 105 and the source or drain of the transistor 701 on a second side of the first substrate is connected to the second memory cell array 106. Here, the isolation structure 601 is an insulating material, and performs an insulating function to reduce signal interference. The transistor 701 is the same as the control transistor in the previous embodiment, and is not described here again.

In some embodiments, the memory further comprises:

Here, the second substrate and the third substrate are the same as the first substrate, and the descriptions thereof are omitted. In some embodiments, a first peripheral circuit may be formed on a first side of a first substrate, a second peripheral circuit may be formed on a second side of the first substrate, a first memory cell array may be formed on a second substrate, a second memory cell array may be formed on a third substrate, then the first side of the first substrate may be bonded to the second substrate such that the first peripheral circuit is connected to the first memory cell array, and the second side of the first substrate may be bonded to the third substrate such that the second peripheral circuit is connected to the second memory cell array. Thus, peripheral circuits and memory cell arrays can be formed on a plurality of substrates respectively, so that mutual interference among process procedures is reduced, and the success rate of double-sided integration is improved.

In the embodiment of the disclosure, a first peripheral circuit and a first memory cell array connected with the first peripheral circuit are arranged on a first side of a first substrate, and a second peripheral circuit and a second memory cell array connected with the second peripheral circuit are arranged on a second side of the first substrate. Thus, the memory portion and the corresponding peripheral portion can be formed on both sides of the first substrate, and the integration level of the memory can be improved.

Based on the memory in the foregoing embodiments, the present disclosure further provides a method for manufacturing a memory, and fig. 6 is a schematic flow chart of the method for manufacturing a memory according to the embodiment of the present disclosure. As shown in fig. 6, a method for manufacturing a memory according to an embodiment of the present disclosure includes the steps of:

step S601: forming a first peripheral circuit on a first side of a first substrate;

step S602: forming a first memory cell array connected to the first peripheral circuit on the first peripheral circuit;

step S603: forming a second peripheral circuit on a second side of the first substrate; the first side and the second side are oppositely arranged along the thickness direction of the first substrate;

step S604: and forming a second memory cell array connected with the second peripheral circuit on one side of the second peripheral circuit away from the first peripheral circuit.

It should be understood that the steps shown in fig. 6 are not exclusive and that other steps may be performed before, after, or between any of the steps in the illustrated operations. The steps shown in fig. 6 can be sequentially adjusted according to actual needs. Fig. 7a to 7d are schematic cross-sectional views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the disclosure. The following describes in detail the method for manufacturing the memory provided in the embodiment of the present disclosure with reference to fig. 6, 7a to 7 d.

It should be noted that in the following steps, only one of various architectures of the memory is exemplarily described, but it should be understood that the description of the following embodiments with respect to the memory architecture is only used to illustrate the present disclosure, and is not used to limit the scope of the present disclosure.

Step S601 is performed, referring to fig. 7a, providing a first substrate 10. The first substrate 10 has a first side 101 and a second side 102. The first side 101 and the second side 102 are opposite sides of the first substrate 10 in the Z-axis direction. Wherein the first side 101 is located above the second side 102, and a first peripheral circuit 103 is formed on the first side 101 of the first substrate 10.

Step S602 is performed, referring to fig. 7b, forming a first memory cell array 105 on a side of the first peripheral circuit 103 remote from the first substrate 10, the first peripheral circuit 103 being connected to the first memory cell array 105.

Step S603 is performed, referring to fig. 7c, the first substrate 10 is flipped such that the second side 102 of the first substrate 10 is located above the first side 101, and then the second peripheral circuit 104 is formed on the surface of the second side 102 of the first substrate.

Referring to fig. 7d, a second memory cell array 106 is formed on a side of the second peripheral circuit 104 away from the first substrate 10, and the second memory cell array 106 is connected to the second peripheral circuit 104.

In this embodiment, the first peripheral circuit and the first memory cell array connected to the first peripheral circuit are disposed on the first side of the first substrate, and the second peripheral circuit and the second memory cell array connected to the second peripheral circuit are disposed on the second side of the first substrate. Thus, the memory portion and the corresponding peripheral portion can be formed on both sides of the first substrate, and the integration level of the memory can be improved.

According to another aspect of the disclosure, the disclosure further provides a method for manufacturing a memory, and fig. 8 is a schematic flow chart of another method for manufacturing a memory provided in an embodiment of the disclosure. As shown in fig. 8, another method for manufacturing a memory according to an embodiment of the present disclosure includes the following steps:

step S801: forming a first peripheral circuit on a first side of a first substrate;

step S802: forming a second peripheral circuit on a second side of the first substrate; the first side and the second side are oppositely arranged along the thickness direction of the first substrate;

step S803: forming a first memory cell array on a second substrate;

step S804: forming a second memory cell array on a third substrate;

step S805: bonding the first substrate to the second substrate such that a first array of memory cells is located on a side of the first peripheral circuitry remote from the second peripheral circuitry; the first memory cell array is electrically connected with the first peripheral circuit;

Step S806: bonding the first substrate to the third substrate such that a second array of memory cells is located on a side of the second peripheral circuitry remote from the first peripheral circuitry; the second memory cell array is electrically connected to the second peripheral circuit.

It should be understood that the steps shown in fig. 8 are not exclusive and that other steps may be performed before, after, or between any of the steps in the illustrated operations. The steps shown in fig. 8 can be sequentially adjusted according to actual needs. Fig. 9a to 9f are schematic cross-sectional views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the disclosure. The following describes in detail the method for manufacturing the memory provided in the embodiment of the present disclosure with reference to fig. 8, 9a to 9 f.

Step S801 is performed, referring to fig. 9a, providing a first substrate 10. The first substrate 10 has a first side 101 and a second side 102. Here, the first side 101 is located above the second side 102, and the first peripheral circuit 103 is formed on the first side 101 of the first substrate 10.

Step S802 is performed, referring to fig. 9b, forming a second peripheral circuit 104 on the second side 102 of the first substrate.

Step S803 is performed, referring to fig. 9c, providing a second substrate 20, forming a first memory cell array 105 on either one of two opposite sides of the second substrate 20 in the thickness direction.

Step S804 is performed, referring to fig. 9d, providing a third substrate 30, forming a second memory cell array 106 on either one of two opposite sides of the third substrate 30 in the thickness direction.

Step S805 is performed, referring to fig. 9e, bonding the first side 101 of the first substrate 10 with the second substrate 20 so that the first memory cell array 105 is connected with the first peripheral circuit 103.

Step S806 is performed, referring to fig. 9f, bonding the second side 102 of the first substrate 10 with the third substrate 30 such that the second memory cell array 106 is connected with the second peripheral circuit 104.

In the process of forming the memory of this embodiment, different device structures, such as a peripheral circuit and a memory cell array, may be formed on a plurality of substrates, and then the stacked memory may be formed by bonding, so that the peripheral circuit and the memory cell array may be formed on different substrates, and mutual interference in the process of forming the peripheral circuit and the memory cell array may be reduced, thereby reducing adverse effects of a process on a structural device, improving a process window, thereby improving a yield of the device, and reducing manufacturing costs.

In some embodiments, a method of forming the first peripheral circuit/second peripheral circuit includes:

Methods of forming the ridge structure include, but are not limited to, etching processes, deposition processes, and the like.

In some embodiments, referring to fig. 7d and 9f, the method further comprises:

forming one or more first interconnect layers 301 between the first peripheral circuitry 103 and the first memory cell array 105; the first peripheral circuit is electrically connected with the first memory cell array through the one or more first interconnection layers;

forming one or more second interconnect layers 302 between the second peripheral circuitry 104 and the second array of memory cells 106; the second peripheral circuitry is electrically connected to the second array of memory cells through the one or more second interconnect layers.

The materials of the first interconnect layer and the second interconnect layer and the method for forming the same are described above, and are not described here again.

In some embodiments, the method further comprises:

The materials of the first conductive pillar and the second conductive pillar and the forming method thereof are described before, and are not described herein again.

Based on the memory in the above embodiments, the present disclosure further provides a memory system, including: a memory as described in the above embodiments of the present disclosure; and

In some embodiments, the memory system includes, but is not limited to, an internal memory.

The above-described unit structure may employ any material capable of realizing its basic function in terms of material selection, but each layer has its preferred material in order to further improve the electrical properties and use effects of the memory.

In several embodiments provided by the present disclosure, it should be understood that the disclosed apparatus and methods may be implemented in a non-targeted manner. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the components shown or discussed are coupled to each other or directly.

The units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A memory, comprising:

A first peripheral circuit disposed on the first side;

a second peripheral circuit disposed on the second side;

2. The memory according to claim 1, wherein the first memory cell array and/or the second memory cell array comprises: a plurality of first-type memory cells arranged in an array along a second direction and a third direction; each first type of storage unit comprises: control transistor and capacitance; wherein the amount of charge stored in the capacitance is changed by the control transistor; the second direction and the third direction intersect and are both perpendicular to the first direction.

3. The memory according to claim 2, wherein the first memory cell array and/or the second memory cell array comprises: a memory cell structure, the memory cell structure comprising: a first bit line, a first control transistor, a capacitor, a second control transistor, a second bit line, and a first word line and a second word line stacked in the first direction; wherein the first bit line and the second bit line extend along the second direction, and the first word line and the second word line extend along the third direction;

4. The memory according to claim 2, wherein the first memory cell array and/or the second memory cell array comprises: a memory cell structure, the memory cell structure comprising: a first bit line, a first control transistor, a first capacitor, a second control transistor, a second bit line, a first word line, a second word line, and a second bit line stacked in the first direction; wherein the first bit line and the second bit line extend along the second direction, and the first word line and the second word line extend along the third direction;

5. The memory according to claim 3 or 4, wherein the first memory cell array and/or the second memory cell array comprises: and a plurality of memory cell structures stacked along the first direction, wherein the bit line is shared between two adjacent memory cell structures.

6. The memory of claim 3, wherein the first array of memory cells and/or the second array of memory cells comprises: a first capacitor, a first control transistor, a bit line, a second control transistor, a second capacitor, and a first word line and a second word line stacked in the first direction; wherein the bit line extends along the second direction, and the first word line and the second word line extend along the third direction;

7. The memory according to claim 1, wherein the first memory cell array and/or the second memory cell array comprises: a plurality of second-class memory cells arranged in an array along a second direction and a third direction; each of the second type of storage units comprises: a read transistor and a write transistor; wherein a resistance state between a source and a drain of the read transistor is changed by the write transistor; the second direction and the third direction intersect and are both perpendicular to the first direction.

8. The memory according to claim 7, wherein the first memory cell array and/or the second memory cell array comprises: a read word line, a read transistor, a write word line, a read bit line, and a write bit line stacked along the first direction; wherein the read word line and the write bit line extend along the second direction, and the write word line and the read bit line extend along the third direction;

9. The memory of claim 1, wherein the memory further comprises:

10. The memory of claim 9, wherein the memory further comprises: a plurality of first conductive pillars; the first memory cell array and the first peripheral circuit are electrically connected with the one or more first interconnection layers through the plurality of first conductive pillars;

11. The memory of claim 1, wherein ridge structures are located on the first side and/or the second side surface of the first substrate, wherein the ridge structures have isolation structures therebetween; and

and the source and drain ends of the transistor are connected with the memory cell array.

12. The memory of claim 1, wherein the memory further comprises:

13. A memory system, comprising: the memory of claims 1-12; and

14. A method of fabricating a memory, the method comprising:

forming a first peripheral circuit on a first side of a first substrate;

15. A method of fabricating a memory, the method comprising:

forming a first peripheral circuit on a first side of a first substrate;

forming a first memory cell array on a second substrate;

forming a second memory cell array on a third substrate;

16. The method of manufacturing a memory according to claim 14 or 15, wherein the method of forming the first peripheral circuit/the second peripheral circuit comprises:

17. The method according to claim 14 or 15, characterized in that the method further comprises:

18. The method of manufacturing a memory of claim 17, further comprising: