CN117497596A - Structure for improving reliability of vertical power device and manufacturing method thereof - Google Patents

Structure for improving reliability of vertical power device and manufacturing method thereof Download PDF

Info

Publication number
CN117497596A
CN117497596A CN202311625400.7A CN202311625400A CN117497596A CN 117497596 A CN117497596 A CN 117497596A CN 202311625400 A CN202311625400 A CN 202311625400A CN 117497596 A CN117497596 A CN 117497596A
Authority
CN
China
Prior art keywords
region
layer
trench
gate
oxide layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311625400.7A
Other languages
Chinese (zh)
Inventor
曾大杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Shangyangtong Technology Co ltd
Original Assignee
Shenzhen Shangyangtong Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Shangyangtong Technology Co ltd filed Critical Shenzhen Shangyangtong Technology Co ltd
Priority to CN202311625400.7A priority Critical patent/CN117497596A/en
Publication of CN117497596A publication Critical patent/CN117497596A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention discloses a structure for improving the reliability of a vertical power device, a trench gate penetrating through a channel region and a source region formed on the surface of the channel region are arranged in a device unit region, a second trench structure penetrating through the channel region is arranged in a terminal region, a first thermal oxide layer covers all regions of the terminal region and the device unit region, the first thermal oxide layer directly carries out thermal oxidation on materials of a first epitaxial layer and materials of a second conductive material layer in the terminal region, the first thermal oxide layer directly carries out thermal oxidation on materials of the first epitaxial layer and materials of a grid conductive material layer in the device unit region, and the reliability of the vertical power device is improved by utilizing the interface characteristic between the first thermal oxide layer and the materials of the first epitaxial layer and a comprehensive etching-free continuous extending structure of the first thermal oxide layer. The invention also discloses a manufacturing method of the structure for improving the reliability of the vertical power device. The invention can improve the reliability and reduce the process cost at the same time.

Description

Structure for improving reliability of vertical power device and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a structure for improving the reliability of a vertical power device. The invention also relates to a manufacturing method of the structure for improving the reliability of the vertical power device.
Background
In order to reduce the specific on-resistance or increase the power density of the power device, a vertical structure is generally adopted. Compared with a transverse device, the vertical structure can bear breakdown voltage by utilizing the longitudinal drift region, the dimension of the primary cell of the vertical structure is not in direct proportion to the breakdown voltage, the on-resistance can be reduced better, and the current density is improved.
However, for vertical devices, the termination structure remains a lateral device and the termination structure needs to withstand sufficient withstand voltage. In order to secure withstand voltage of the terminal, various terminal structures such as field limiting rings, field plates, etc. have been proposed.
The maximum value of the termination field strength is typically at the interface of Silicon (Silicon) and an insulating layer (typically Silicon dioxide) over the Silicon. In order to ensure the reliability of the device, it is necessary to reduce the defect density of the interface. For silicon power devices, the most common method of reducing interface defect density of the terminal includes:
As shown in fig. 1A to 1B, the schematic device structure of the conventional first power device in each step of the method for manufacturing field oxide required for the termination region is shown; the method comprises the following steps:
as shown in fig. 1A, a semiconductor substrate 101 is provided, and the semiconductor substrate 101 includes a silicon substrate. An oxide layer 102 is formed on the semiconductor substrate 101 by a thermal oxidation process. The temperature of the thermal oxidation process is typically 900-1200 ℃, and the thickness of the oxide layer is typically betweenBetween them.
Thereafter, as shown in fig. 1B, a termination region and a device cell region are defined by using a Mask (Mask) and performing a photolithography process, and in fig. 1B, the termination region is located at the left side of the line AA and the device cell region is located at the right side of the line AA. Typically, there is also a transition region between the termination region and the device cell region, which is also part of the termination region. The device cell region is also commonly referred to as an active region or a cell region, and a device cell, i.e., a cell, may be formed in the device cell region.
Thereafter, etching is performed according to a photolithography process to remove the oxide layer 102 in the device cell region, and the oxide layer 102 in the termination region remains.
After the oxide layer 102 in the device cell region is removed, the top surface of the semiconductor substrate 101 is exposed, so that the structure of the device cell, if a gate structure, a channel region, a source region, etc., can be formed in the device cell region.
The oxide layer 102 included in the termination region forms a good interface with the semiconductor substrate 101, thereby reducing the interface defect density of the termination.
As shown in fig. 2, a schematic device structure in a step of defining a field oxide formation region in a method for manufacturing field oxide required for a termination region in a conventional first power device; the method comprises the following steps:
first, a hard mask layer (HM) is deposited on a semiconductor substrate 201, and in fig. 2, the HM is formed by stacking an Oxide layer 202 (Oxide), a Nitride layer 203 (Nitride), and an Oxide layer 204.
Defining a terminal area and a device unit area by using a Mask and performing a photolithography process, wherein in fig. 1B, the terminal area is positioned at the left side of a line AA, and the device unit area is positioned at the right side of the line AA; thereafter, the HM is etched to remove the HM in the termination region, and the HM of the active region is exposed.
Then, an oxide layer is formed by using thermal oxygen. The oxide layer produced by using the characteristic that Oxygen (Oxygen) can not diffuse in Nitride any more is only in the termination region. The second prior art method provides a smoother Profile of the oxide layer in the termination region and less stress than the first prior art method described above.
However, both methods have a disadvantage in that an additional photomask is required to form the oxide layer, which increases the cost of the process.
Disclosure of Invention
The invention aims to solve the technical problem of providing a structure for improving the reliability of a vertical power device, which can reduce the defect density between the epitaxial layer material of a terminal structure and a top oxide layer and simultaneously prevent the oxide layer on the top of the epitaxial layer material of the terminal structure from being graphically etched, thereby optimizing the reliability of the device and reducing the process cost. Therefore, the invention also provides a manufacturing method of the structure for improving the reliability of the vertical power device.
In order to solve the technical problems, in the structure for improving the reliability of the vertical power device provided by the invention, the vertical power device comprises a device unit area and a terminal area, wherein the terminal area surrounds the peripheral side of the device unit area.
A second conductivity type doped channel region is formed in a surface region of the first conductivity type doped first epitaxial layer.
The first epitaxial layer at the bottom of the channel region serves as a drift region.
A back electrode region is formed at the bottom of the drift region, and a back electrode formed by a back metal layer is formed on the back of the back electrode region.
A plurality of parallel device units are formed in the device unit area; each of the device cells includes a trench gate.
The trench gate comprises a gate trench, a gate dielectric layer formed on the inner side surface of the gate trench and a gate conductive material layer filled in the gate trench; the gate trench passes through the channel region, and a surface of the channel region laterally covered by the gate conductive material layer is used to form a conductive channel.
Each of the device cells further includes a heavily doped source region of the first conductivity type formed on a surface of the channel region and self-aligned to a corresponding side of the trench gate.
A plurality of second groove structures are included in the terminal region, the second groove structures comprise second grooves, second dielectric layers formed on inner side surfaces of the second grooves and second conductive material layers filled in the second grooves; the second trench passes through the channel region.
Each of the gate trenches and each of the second trenches are arranged in parallel.
A first thermal oxide layer covers all regions of the termination region in which the first thermal oxide layer is formed directly thermally oxidizing a material of the first epitaxial layer and a material of a second conductive material layer in a surface region of the channel region and the device cell region in which the first thermal oxide layer is formed directly thermally oxidizing a material of the first epitaxial layer in a surface region of the source region, a material of the first epitaxial layer in a surface region of the channel region outside the source region, and a material of a gate conductive material layer.
The composition structure of the transverse withstand voltage terminal structure comprises a plurality of second groove structures, channel regions, drift regions and first thermal oxide layers which are transversely arranged, and the reliability of the vertical power device is improved by utilizing the interface characteristics between materials of the first thermal oxide layers and the first epitaxial layers and the continuous extending structure of the first thermal oxide layers in the terminal regions and the device unit regions without etching.
A further improvement is that the impurities of the channel region and the source region are driven by a thermal process of thermal oxidation of the first thermal oxide layer.
A further improvement is that the thickness of the first thermal oxide layer meets the thickness requirement of an interlayer film, which is composed of the first thermal oxide layer.
Alternatively, the first thermal oxide layer is used as a bottom part of an interlayer film, a deposition oxide layer is further formed on the surface of the first thermal oxide layer, and the interlayer film is formed by laminating the first thermal oxide layer and the deposition oxide layer.
A further improvement is that the gate conductive material layer is connected to the gate electrode composed of the front metal layer through a top corresponding via hole penetrating the interlayer film.
The source region is connected to a source electrode composed of the front metal layer through the through hole corresponding to the top.
The second conductive material layer is a floating structure or is connected to the back electrode.
In a further improvement, the vertical power device is a vertical superjunction power device, and a superjunction structure is formed in the drift region, wherein the superjunction structure is formed by alternately arranging second conductive type columns formed in a selected region of the drift region and first conductive type columns formed in the drift region between the second conductive type columns.
A further improvement is that the second conductivity type pillar extends downward from a top surface of the first epitaxial layer where the trench gate, the second trench structure, the channel region and the source region are formed, the second conductivity type pillar comprising a stacked structure of second conductivity type ion implantation regions or comprising a second conductivity type epitaxial layer filled in a superjunction trench.
A further improvement is that the vertical power device comprises a MOSFET or an IGBT, the MOSFET comprising a trench gate MOSFET or an SGT MOSFET.
A further improvement is that the gate trench and the second trench have a process structure formed simultaneously using the same process.
And the gate dielectric layer and the second dielectric layer are made of the same material and are formed simultaneously.
The gate conductive material layer and the second conductive material layer are formed of the same material and simultaneously.
In a further improvement, the gate conductive material layer is made of polysilicon.
In order to solve the technical problems, the manufacturing method of the structure for improving the reliability of the vertical power device provided by the invention comprises the following steps:
a semiconductor substrate is provided, and a first epitaxial layer doped with a first conductivity type is formed on the front surface of the semiconductor substrate.
Simultaneously forming a plurality of trench gates in a device cell region and a plurality of second trench structures in a termination region, the termination region surrounding a periphery of the device cell region; the trench gate comprises a gate trench, a gate dielectric layer formed on the inner side surface of the gate trench and a gate conductive material layer filled in the gate trench; the second groove structure comprises a second groove, a second dielectric layer formed on the inner side surface of the second groove and a second conductive material layer filled in the second groove; each of the gate trenches and each of the second trenches are arranged in parallel.
Performing ion implantation of a second conductivity type to form a channel region in a surface region of the first epitaxial layer of the device cell region and the termination region; the gate trench penetrates through the channel region, and the surface of the channel region laterally covered by the gate conductive material layer is used for forming a conductive channel; the second trench passes through the channel region.
Ion implantation of a first conductivity type heavily doping is performed in a surface region of the channel region in a selected region of the device cell region to form a source region of each device cell, the source region and the corresponding side of the trench gate being self-aligned.
Performing thermal oxidation to form a first thermal oxide layer, wherein the first thermal oxide layer covers all areas of the terminal area and the device unit area, and in the terminal area, the first thermal oxide layer directly performs thermal oxidation to the material of the first epitaxial layer and the material of the second conductive material layer in the surface area of the channel area; in the device unit region, the first thermal oxidation layer directly performs the thermal oxidation formation on the material of the first epitaxial layer in the surface region of the source region, the material of the first epitaxial layer in the surface region of the channel region outside the source region, and the material of the gate conductive material layer; the composition structure of the transverse withstand voltage terminal structure comprises a plurality of second groove structures, channel regions, drift regions and first thermal oxide layers which are transversely arranged, and the reliability of the vertical power device is improved by utilizing the interface characteristics between materials of the first thermal oxide layers and the first epitaxial layers and the continuous extending structure of the first thermal oxide layers in the terminal regions and the device unit regions without etching.
A further improvement is that the impurities of the channel region and the source region are driven by a thermal process of the thermal oxidation of the first thermal oxide layer.
A further improvement is that the ion implantation of the channel region is performed by blanket implantation or by selective ion implantation defined by a photolithography mask.
The ion implantation of the source region adopts selective ion implantation defined by a photoetching plate.
A further improvement is that the thickness of the first thermal oxide layer meets the thickness requirement of an interlayer film, and the interlayer film consists of the first thermal oxide layer;
alternatively, the method further comprises:
and forming a deposition oxide layer on the surface of the first thermal oxide layer by adopting a CVD deposition process, and forming the interlayer film by laminating the first thermal oxide layer and the deposition oxide layer.
Further improvement is that the method further comprises:
a via hole is formed through the interlayer film.
And forming a front metal layer, and patterning the front metal layer to form a source electrode and a grid electrode.
The gate conductive material layer is connected to the gate through the top corresponding via.
The source region is connected to the source electrode through the via hole corresponding to the top.
The second conductive material layer is a floating structure or is connected to the back electrode.
In a further improvement, the vertical power device is a vertical superjunction power device, and the method further comprises the steps of, after the source region is formed and before the first thermal oxide layer is formed:
a superjunction structure is formed in the drift region, the superjunction structure being formed by alternating columns of the second conductivity type formed in selected regions of the drift region and columns of the first conductivity type formed in the drift region between the columns of the second conductivity type.
A further improvement is that the second conductivity type pillars are formed by a plurality of second conductivity type ion implantations.
Alternatively, the forming of the second conductivity type pillar includes:
forming a superjunction groove;
and filling a second conductive type epitaxial layer in the super junction groove to form the second conductive type column.
A further improvement is that the vertical power device comprises a MOSFET or an IGBT, the MOSFET comprising a trench gate MOSFET or an SGT MOSFET.
In a further improvement, the gate conductive material layer is made of polysilicon.
The oxide layer at the top of the epitaxial layer in the terminal structure adopts the first thermal oxide layer which covers the terminal region and the device unit region in a whole, and the thermal oxidation process can minimize the interface defect between the materials of the first thermal oxide layer and the first epitaxial layer at the bottom; meanwhile, the first thermal oxide layer is not more than a patterning process, so that the first thermal oxide layer has no interface in the transverse extending direction, for example, an interface formed by etching is not formed between the terminal area and the device unit area, the quality of the first thermal oxide layer can be ensured, the quality of the first thermal oxide layer can reach the optimal quality, the reliability of the device can be improved simultaneously by reducing interface defects and improving the quality of the first thermal oxide layer, and the reliability of the device can reach the optimal state.
In addition, the first thermal oxide layer does not need to adopt a patterning process, and one-time photoetching process can be saved, so that the process cost can be reduced at the same time.
In addition, the first thermal oxide layer of the present invention can be directly used as a constituent of the interlayer film, so that deposition of the interlayer film of a partial thickness is not required or only performed, which can further reduce the process cost.
In addition, the thermal oxidation process of the first thermal oxidation layer can oxidize the top area of the gate conductive material layer of the trench gate, so that the morphology of the gate conductive material layer can be repaired and the gate leakage can be optimized.
In addition, the thermal process of the thermal oxidation process of the first thermal oxide layer can be directly used as the advancing thermal process of ion implantation impurities of the channel region and the source region, so that the sharing of the thermal process can be realized, and the process cost can be further reduced.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIGS. 1A-1B are schematic views of a device structure at various steps in a method for fabricating field oxide required for a termination region in a conventional first power device;
fig. 2 is a schematic view showing a device structure in a step of defining a field oxide formation region in a method for manufacturing field oxide required for a termination region in a conventional second power device;
Fig. 3A is a schematic structural diagram of a first thermal oxide layer before forming in a structure for improving reliability of a vertical power device according to a first embodiment of the present invention;
fig. 3B is a schematic structural diagram of a first thermal oxide layer formed in a structure for improving reliability of a vertical power device according to a first embodiment of the present invention;
fig. 4 is a schematic structural diagram of a structure for improving reliability of a vertical power device according to a second embodiment of the present invention before forming a first thermal oxide layer.
Detailed Description
As shown in fig. 3A, a schematic structural diagram of the first thermal oxide layer 17 before formation in the structure for improving the reliability of the vertical power device according to the first embodiment of the present invention is shown; as shown in fig. 3B, in the structure for improving the reliability of the vertical power device according to the first embodiment of the present invention, the structure of the first thermal oxide layer 17 is omitted after the formation of the first thermal oxide layer 17; in the structure for improving the reliability of the vertical power device, the vertical power device comprises a device unit area and a terminal area, wherein the terminal area surrounds the periphery of the device unit area. In fig. 3A, the termination region is located on the left side of line AA and the device cell region is located on the right side of line AA.
A channel region 15 doped with the second conductivity type is formed in a surface region of the first epitaxial layer 12a doped with the first conductivity type.
The first epitaxial layer 12a at the bottom of the channel region 15 serves as the drift region 12.
A rear electrode region 11 is formed at the bottom of the drift region 12, and a rear electrode formed of a rear metal layer is formed on the rear surface of the rear electrode region 11. In the first embodiment of the present invention, the vertical power device is a MOSFET, the back electrode region 11 is a heavily doped drain region of the first conductivity type, and the back electrode is a drain. In other embodiments can also be: the vertical power device is an IGBT, the back electrode region 11 is a collector region heavily doped with the second conductivity type, and the back electrode is a collector.
Further, in some embodiments, taking an N-type MOSFET as an example, the semiconductor substrate is a heavily doped N-type substrate; it is desirable that the doping concentration of the semiconductor substrate be as high as possible, the resistivity be as low as possible, and the thickness of the semiconductor substrate be as thin as possible, so that not only the substrate resistance but also the thermal resistance of the chip can be reduced. Currently, for phosphorus (phosphorus) doped semiconductor substrates, the resistivity of the substrate can reach 0.7mΩ×cm, while for Arsenic (arsenical) doped semiconductor substrates, the resistivity of the substrate can reach 1.1mΩ×cm. For the thickness of semiconductor substrates, the thinnest possible is currently up to 30 μm.
The first epitaxial layer 12a is set according to the requirement of the drift region 12, and the doping concentration and thickness of the drift region 12 determine the breakdown voltage of the device; the higher the breakdown voltage required by the device, the thicker the thickness of the drift region 12, and the higher the resistivity of the drift region 12; for a 600V device, the resistivity of the drift region 12 is typically around 13 Ω cm and the thickness of the drift region 12 is typically around 50 μm.
In the first embodiment of the present invention, the first epitaxial layer 12a is formed on the surface of the semiconductor substrate. The back electrode region 11 is a heavily doped region of the first conductivity type formed on the back surface of the drift region 2 after the back surface of the semiconductor substrate is thinned. In some embodiments, the semiconductor substrate adopts a heavily doped structure of the first conductivity type, so that the back electrode region 11, i.e., the drain region, is directly composed of the thinned back side semiconductor substrate. In some embodiments, it can also be: the doping concentration of the semiconductor substrate does not meet the requirement of the first conductivity type heavy doping of the back electrode region 11, and the back electrode region 11 is composed of a back ion implantation region of the first conductivity type heavy doping performed after the back surface of the semiconductor substrate is thinned.
A plurality of parallel device units are formed in the device unit area; each device cell includes a trench gate. The step of the device cell is the sum of the width of the trench gates and the spacing between the trench gates.
The trench gate comprises a gate trench, a gate dielectric layer 13 formed on the inner side surface of the gate trench and a gate conductive material layer 14 filled in the gate trench; the gate trench passes through the channel region 15 and the surface of the channel region 15 that is laterally covered by the layer of gate conductive material 14 is used to form a conductive channel. In a first embodiment of the present invention, the MOSFET is a trench gate MOSFET. The trench gate is formed by superimposing only the gate dielectric layer 13 and the gate conductive material layer 14 formed in the gate trench. Other embodiments can also be: the MOSFET is a Shielded Gate Trench (SGT) MOSFET in which a shield electrode conductive material layer is also formed, a shield dielectric layer is isolated between the shield electrode conductive material layer and the gate trench, and an inter-gate dielectric layer is isolated between the shield electrode conductive material layer and the gate conductive material layer 14. The gate structure of the SGT MOSFET may be a side-to-side structure or an up-down structure. Reference is made specifically to the structure of an existing SGT MOSFET, and the gate structure of the SGT MOSFET will not be described in detail in this application.
Each device cell further includes a heavily doped source region 16 of the first conductivity type, the source region 16 being formed at a surface of the channel region 15 and self-aligned to a side of the corresponding trench gate. In some embodiments, a heavily doped cut-off region 16a of the first conductivity type is formed at the outermost side of the termination region, and the cut-off region 16a is typically formed at the same time as the source region 16, where the two doping process conditions are the same. In some embodiments can also be: the cut-off region 16a is independent of the process of forming the source region 16 and the doping process conditions are independent of each other.
In the termination region, a plurality of second trench structures including a second trench, a second dielectric layer 13a formed on an inner side surface of the second trench, and a second conductive material layer 14a filled in the second trench; the second trench passes through the channel region 15.
The gate trenches and the second trenches are arranged in parallel.
In the first embodiment of the present invention, the gate trench and the second trench have a process structure formed simultaneously by the same process. In some embodiments, the width of the second trenches is the same as the width of the gate trenches, and the pitch of the second trenches is the same as the pitch of the gate trenches. In some embodiments can also be: the width of the second trench and the width of the gate trench are independent of each other, and the pitch of the second trench and the pitch of the gate trench are independent of each other.
In the first embodiment of the present invention, the gate dielectric layer 13 and the second dielectric layer 13a are formed of the same material and at the same time. In some embodiments, the gate dielectric layer 13 is an oxide layer.
The gate conductive material layer 14 and the second conductive material layer 14a are formed of the same material and at the same time. In some embodiments, the material of the gate conductive material layer 14 is polysilicon that is heavily doped with the first conductivity type.
In some embodiments, the width of the trench, i.e., the gate trench or the second trench, is typically 0.3 μm, the width between the trench and the trench is 0.7 μm, the corresponding step (Pitch) is 1.0 μm, and the depth of the trench is also typically 1.0 μm.
After the trench etching is completed, an Oxide layer (Oxide) is grown as the gate dielectric layer 13 and the second dielectric layer 13a, the Oxide layer is usually grown by thermal oxygen, and the thickness is usually equal toBetween them.
In fig. 3A, a top surface of the first epitaxial layer 12a is denoted by reference numeral 301, and a first thermal oxide layer 17 is formed on the top surface of the first epitaxial layer 12a as denoted by reference numeral 301. As shown in fig. 3B, the first thermal oxide layer 17 covers the entire area of the termination area in which the first thermal oxide layer 17 is formed by directly thermally oxidizing the material of the first epitaxial layer 12a and the material of the second conductive material layer 14a in the surface area of the channel region 15 and the device cell area in which the first thermal oxide layer 17 is formed by directly thermally oxidizing the material of the first epitaxial layer 12a in the surface area of the source region 16, the material of the first epitaxial layer 12a in the surface area of the channel region 15 outside the source region 16, and the material of the gate conductive material layer 14. As shown in fig. 3B, the thermal oxidation may have a certain loss to the thickness of the first epitaxial layer 12a, and after the first thermal oxide layer 17 is formed, the top surface of the first epitaxial layer 12a may be lowered from the position indicated by the reference numeral 301 to the position indicated by the reference numeral 302. The first thermal oxide layer 17 formed by this thermal oxidation has an optimal interface structure with minimal defects.
The composition structure of the lateral withstand voltage terminal structure includes a plurality of second trench structures, a channel region 15, a drift region 12 and a first thermal oxide layer 17 which are arranged laterally, and the reliability of the vertical power device is improved by utilizing the interface characteristics between the materials of the first thermal oxide layer 17 and the first epitaxial layer 12a and the continuous extension structure of the first thermal oxide layer 17 without etching in the terminal region and the device unit region.
In some embodiments, taking silicon as an example of the material of the first epitaxial layer 12a, the first thermal oxide layer 17 consumes the trenches, i.e., the Mesa region (Mesa) between the gate trench or the second trench, in a proportion of about per productionIs to consume->Silicon (Silicon). Meanwhile, a certain amount of polysilicon is consumed; this need is a design consideration.
Some typical conditions for the thermal oxidation of the first thermal oxide layer 17 may be:
a.980 ℃ temperature, the growth thickness is
At a temperature of 1050 ℃ and a growth thickness of
A temperature of C.980 ℃ and a growth thickness of
In the first embodiment of the present invention, the impurities of the channel region 15 and the source region 16 are driven by a thermal process of thermal oxidation of the first thermal oxide layer 17.
In some embodiments, the thickness of the first thermal oxide layer 17 meets the thickness requirement of an interlayer film composed of the first thermal oxide layer 17; for example: if it is Thickness is greater thanThe first thermal oxide layer 17 may directly serve as an interlayer film. In some embodiments can also be: the first thermal oxide layer 17 is formed as a bottom portion of the interlayer film, a deposition oxide layer is further formed on the surface of the first thermal oxide layer 17, and the interlayer film is formed by laminating the first thermal oxide layer 17 and the deposition oxide layer. The deposited oxide layer of the ILD typically consists of psg+bpsg. In the prior art, ILD is directly formed on the surface of the first epitaxial layer 12 through a deposited Oxide layer, but the number of defects of the Silicon and Oxide Interface in the termination region is greater, and the long-term reliability of the product is poor. The first thermal oxide layer 17 of the first embodiment of the present invention can eliminate the problem of more interface defects caused by contact between the deposited oxide layers of the ILD and the first epitaxial layer 12.
The gate conductive material layer 14 is connected to the gate electrode composed of the front side metal layer through a top corresponding via hole penetrating the interlayer film.
The source region 16 is connected to a source composed of a front side metal layer through a top corresponding via.
The second conductive material layer 14a is a floating structure or the second conductive material layer 14a is connected to the back electrode.
In the first embodiment of the present invention, the vertical power device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments can also be: the vertical power device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
The oxide layer at the top of the epitaxial layer in the terminal structure of the first embodiment of the present invention adopts the first thermal oxide layer 17 which covers the terminal region and the device unit region entirely, and the thermal oxidation process can minimize the interface defect between the materials of the first thermal oxide layer 17 and the first epitaxial layer 12a at the bottom; meanwhile, the first thermal oxide layer 17 is not compared with a patterning process, so that the first thermal oxide layer 17 has no interface in the transverse extending direction, for example, an interface formed by etching is not formed between a terminal area and a device unit area, so that the quality of the first thermal oxide layer 17 can be ensured, the quality of the first thermal oxide layer 17 can reach the optimal quality, the reliability of a device can be improved simultaneously by reducing interface defects and improving the quality of the first thermal oxide layer 17, and the reliability of the device can reach the optimal state.
In addition, the first thermal oxide layer 17 of the first embodiment of the present invention does not need to use a patterning process, and can save a photolithography process, which can also reduce the process cost.
In addition, the first thermal oxide layer 17 of the first embodiment of the present invention can be directly used as a constituent of the interlayer film, so that deposition of the interlayer film of a partial thickness is not required or is only performed, which can further reduce the process cost.
In addition, the thermal oxidation process of the first thermal oxide layer 17 according to the first embodiment of the present invention can oxidize the top region of the gate conductive material layer 14 of the trench gate, which can repair the morphology of the gate conductive material layer 14 and thus can optimize the gate leakage.
In addition, the thermal process of the thermal oxidation process of the first thermal oxide layer 17 of the first embodiment of the present invention can be directly used as the advanced thermal process of ion implantation impurities into the channel region 15 and the source region 16, so that the sharing of the thermal process can be realized, and the process cost can be further reduced.
Fig. 4 is a schematic structural diagram of a structure for improving reliability of a vertical power device according to a second embodiment of the present invention before forming a first thermal oxide layer; the difference from the structure for improving the reliability of the vertical power device according to the first embodiment of the present invention is that:
in the structure for improving the reliability of the vertical power device according to the second embodiment of the present invention, the vertical power device is a vertical superjunction power device, and a superjunction structure is formed in the drift region 12, and the superjunction structure is formed by alternately arranging the second conductivity type pillars 18 formed in the selected region of the drift region 12 and the first conductivity type pillars formed in the drift region 12 between the second conductivity type pillars 18.
The second conductive-type pillars 18 extend downward from the top surface of the first epitaxial layer 12a, i.e., the surface corresponding to the mark 301, where the trench gate, the second trench structure, the channel region 15, and the source region 16 are formed.
In some embodiments, the second conductivity type pillars 18 comprise a stacked structure of second conductivity type ion implanted regions. For example: taking a typical 80V N-type Super Junction (SJ) MOSFET as an example, the P column, i.e. the second conductivity type column 18, is formed by 5-10 ion implants, the single ion implant dose is 3e 12-1 e13cm 2 The energy of implantation is between 100 and 3500keV, and the implanted impurity is Boron. In the process implementation, the P-pillar is placed after the ion implantation of the NP, i.e., source region 16, to minimize thermal processes and reduce lateral diffusion of the P-pillar, thereby increasing the conductivity channel of the N-type drift region.
In some embodiments can also be: the second conductivity type pillar 18 includes a second conductivity type epitaxial layer filled in the superjunction trench. The super junction structure formed by filling the super junction groove can be applied to higher super junction devices, such as SJ MOSFETs of 600V.
The vertical power device that can be formed by the method for manufacturing a structure for improving the reliability of a vertical power device according to the first embodiment of the present invention includes a MOSFET or an IGBT, and the method for manufacturing a structure for improving the reliability of a vertical power device according to the embodiment of the present invention includes the following steps:
As shown in fig. 3A, a semiconductor substrate is provided, and a first epitaxial layer 12a doped with a first conductivity type is formed on the front surface of the semiconductor substrate. In some embodiments, the semiconductor substrate adopts a heavily doped structure of the first conductivity type, so that the back electrode region 11 is directly formed after the back surface of the semiconductor substrate is thinned.
Simultaneously forming a plurality of trench gates in the device unit region and a plurality of second trench structures in a terminal region, wherein the terminal region surrounds the periphery of the device unit region; the trench gate comprises a gate trench, a gate dielectric layer 13 formed on the inner side surface of the gate trench and a gate conductive material layer 14 filled in the gate trench; the second trench structure includes a second trench, a second dielectric layer 13a formed on an inner side surface of the second trench, and a second conductive material layer 14a filled in the second trench; the gate trenches and the second trenches are arranged in parallel. In some embodiment methods, the process of forming the trench gate and the second trench structure includes the substeps of:
and forming a gate trench and a second trench by trench etching. Typically, a hard mask layer is formed before the trench etching, then a photolithography is performed to define a formation region of the gate trench and the second trench, and then the hard mask layer and the first epitaxial layer 12a are sequentially etched to form the gate trench and the second trench.
Thereafter, a gate dielectric layer 13 is formed on the inner side surface of the gate trench and a second dielectric layer 13a is formed on the inner side surface of the second trench. Preferably, the gate dielectric layer 13 and the second dielectric layer 13a are oxide layers formed by thermal oxygen growth.
And then filling and back etching the polysilicon to form polysilicon only in the gate trench and the second trench, and removing the polysilicon on the surface of the platform region between the trenches. The gate conductive material layer 14 is composed of polysilicon formed in the gate trench, and the second conductive material layer 14a is composed of polysilicon formed in the second trench.
Performing ion implantation of the second conductivity type to form a channel region 15 in the surface region of the first epitaxial layer 12a of the device cell region and the termination region; the gate trench passes through the channel region 15, and the surface of the channel region 15 laterally covered by the gate conductive material layer 14 is used to form a conductive channel; the second trench passes through the channel region 15. In the method of the first embodiment of the present invention, the ion implantation of the channel region 15 is performed by full-scale implantation. Other embodiments of the method can also be: selective ion implantation using a reticle definition.
Ion implantation of a heavily doped first conductivity type forms source regions 16 of each device cell in the surface regions of channel regions 15 in selected regions of the device cell regions, the source regions 16 being self-aligned with the sides of the corresponding trench gates. The ion implantation of the source region 16 employs a selective ion implantation defined by a lithography. In some embodiment methods, ion implantation of source region 16 also simultaneously forms a termination region 16a at the outermost periphery of the termination region.
As shown in fig. 3B, thermal oxidation is performed to form a first thermal oxide layer 17, the first thermal oxide layer 17 covering all regions of the termination region and the device cell region, in which the first thermal oxide layer 17 is formed by directly thermally oxidizing the material of the first epitaxial layer 12a and the material of the second conductive material layer 14a in the surface region of the channel region 15; in the device cell region, the first thermal oxide layer 17 is formed by directly thermally oxidizing the material of the first epitaxial layer 12a in the surface region of the source region 16, the material of the first epitaxial layer 12a in the surface region of the channel region 15 outside the source region 16, and the material of the gate conductive material layer 14; the composition structure of the lateral withstand voltage terminal structure includes a plurality of second trench structures, a channel region 15, a drift region 12 and a first thermal oxide layer 17 which are arranged laterally, and the reliability of the vertical power device is improved by utilizing the interface characteristics between the materials of the first thermal oxide layer 17 and the first epitaxial layer 12a and the continuous extension structure of the first thermal oxide layer 17 without etching in the terminal region and the device unit region.
In the method of the first embodiment of the present invention, the impurities of the channel region 15 and the source region 16 are driven by a thermal process of thermal oxidation of the first thermal oxide layer 17. In this way, not only one annealing process can be saved, but also excessive diffusion of impurities of the channel region 15 and the source region 16 can be prevented.
In the method of the first embodiment of the present invention, the thermal oxidation may cause a loss in the thickness of the first epitaxial layer 12a, for example, the top surface of the first epitaxial layer 12a may be lowered from the position indicated by the mark 301 to the position indicated by the mark 302. At the same time, thermal oxidation also causes a loss of material, such as polysilicon, of the gate conductive material layer 14 and the second conductive material layer 14a, which loss needs to be considered in design in a practical process.
In some embodiment methods, the thickness of the first thermal oxide layer 17 meets the thickness requirement of an interlayer film composed of the first thermal oxide layer 17.
In some embodiment methods, after forming the first thermal oxide layer 7, further comprising:
a deposition oxide layer is formed on the surface of the first thermal oxide layer 17 by a CVD deposition process, and an interlayer film is formed by laminating the first thermal oxide layer 17 and the deposition oxide layer. The deposited oxide layer is typically composed of a stack of phosphor glass (PSG) and borophosphor glass (BPSG).
After the interlayer film is formed, further comprising:
a via hole penetrating the interlayer film is formed.
The thickness of the first thermal oxide layer 17 satisfies the thickness requirement of an interlayer film composed of the first thermal oxide layer 17. In some embodiments can also be: the first thermal oxide layer 17 is formed as a bottom portion of the interlayer film, a deposition oxide layer is further formed on the surface of the first thermal oxide layer 17, and the interlayer film is formed by laminating the first thermal oxide layer 17 and the deposition oxide layer.
And forming a front metal layer, and patterning the front metal layer to form a source electrode and a grid electrode.
The layer of gate conductive material 14 is connected to the gate through a top corresponding via.
The source region 16 is connected to the source through a top corresponding via.
Then, a back side process is performed, the back side process comprising:
the semiconductor substrate is thinned. In the method according to the first embodiment of the present invention, the semiconductor substrate is heavily doped with the first conductivity type, and the thinned semiconductor substrate directly constitutes the back electrode region 11, i.e., the drain region. In some embodiments methods can also be: after the semiconductor substrate is thinned, back side ion implantation of the first conductivity type heavy doping is performed to form the back side electrode region 11.
A back metal layer is formed on the back surface of the back electrode region 11 and constitutes a back electrode.
The second conductive material layer 14a is a floating structure or the second conductive material layer 14a is connected to the back electrode.
Taking an N-type MOSFET as an example, the method of the first embodiment of the present invention is further described below with reference to parameters:
the semiconductor substrate is a heavily doped N-type substrate; it is desirable that the doping concentration of the semiconductor substrate be as high as possible, the resistivity be as low as possible, and the thickness of the semiconductor substrate be as thin as possible, so that not only the substrate resistance but also the thermal resistance of the chip can be reduced.
Currently, for phosphorus (phosphorus) doped semiconductor substrates, the resistivity of the substrate can reach 0.7mΩ×cm, while for Arsenic (arsenical) doped semiconductor substrates, the resistivity of the substrate can reach 1.1mΩ×cm. For the thickness of semiconductor substrates, the thinnest possible is currently up to 30 μm.
The first epitaxial layer 12a is set according to the requirement of the drift region 12, and the doping concentration and thickness of the drift region 12 determine the breakdown voltage of the device; the higher the breakdown voltage required by the device, the thicker the thickness of the drift region 12, and the higher the resistivity of the drift region 12; for a 600V device, the resistivity of the drift region 12 is typically around 13 Ω cm and the thickness of the drift region 12 is typically around 50 μm.
In the method of the first embodiment of the invention, only two lithography plates are used for the N-type MOSFET.
The trenches, i.e., the gate trench and the second trench, are defined by using a photolithography mask, and etching is performed to form the trenches under the definition of the photolithography mask, and a hard mask layer (HM) is usually formed before the etching process of the trenches, and the hard mask layer is usually an oxide layer.
In some example methods, the width of the trenches is typically 0.3 μm, the width between trenches is 0.7 μm, the corresponding step (Pitch) is 1.0 μm, and the depth of the trenches is also typically 1.0 μm.
After the trench etching is completed, an Oxide layer is then grown as the gate dielectric layer 13 and the second dielectric layer 13a, the Oxide layer is usually grown by thermal oxygen and the thickness is usually as followsBetween them.
Then filling the N-type heavily doped polysilicon, and then carrying out back etching (etch back), so that the polysilicon is filled in the grooves, and meanwhile, the Mesa regions (Mesa) between the grooves are not formed.
Then, the channel region is commonly injected, and some product channels can be realized by using a photoetching plate.
Then, a photolithography mask is used to perform source NP implantation.
Conventional Trench-gate (Trench) MOSFETs are now known, followed by deposition of an interlayer film (ILD), which is typically composed of PSG+BPSG. However, the deposited Oxide, the Interface of the Silicon and Oxide in the terminal area, the number of defects will be more, the product will beIs relatively poor in long-term reliability. In the method of the first embodiment of the present invention, after ion implantation of the source region 16, a layer of Oxide, i.e., a first thermal Oxide layer 17, is grown by using thermal oxygen, and the first thermal Oxide layer 17 consumes the Mesa region Mesa between the trench, i.e., the gate trench or the second trench, in a proportion of about per productionOxide of (C) is consumedSilicon (Silicon). Meanwhile, a certain amount of polysilicon is consumed; this need is a design consideration.
Some typical conditions for the thermal oxidation of the first thermal oxide layer 17 may be:
a.980 ℃ temperature, the growth thickness is
At a temperature of 1050 ℃ and a growth thickness of
A temperature of C.980 ℃ and a growth thickness of
The method of the first embodiment of the invention has the following advantages:
A. in the termination region, the Interface (Interface) between the Silicon, i.e. the first epitaxial layer 12, and the Oxide, i.e. the first thermal Oxide layer 17, is produced by thermal oxygen, and the quality of the Interface is well ensured.
B. The grown Oxide does not have any etching process in the subsequent step; the quality of the oxide layer is greatly ensured.
C. The grown Oxide will be directly part of the ILD, which may be completely replaced by this grown Oxide under certain conditions. Without requiring a subsequent oxide layer deposition.
D. Polysilicon of the trench gate is thermally oxidized, and the Profile of the polysilicon is repaired, so that the gate leakage of the device is optimized.
After forming the first thermal oxide layer 17, the following steps, like the conventional forming process of the Trench MOSFET, follow the forming of an interlayer film, i.e. ILD, depending on the thickness of the first thermal oxide layer 17, may be performed if the thickness of the first thermal oxide layer 17 is insufficient, if the thickness is greater than The first thermal oxide layer 17 may also be directly used as ILD.
Then via (CT) etching, metal deposition, etc. are performed. Thereby forming a complete Trench MOSFET.
The method of the first embodiment of the present invention can be equally applied to SGT MOSFETs, SJ MOSFETs, IGBTs, and the like. The first embodiment method of the present invention directly performs thermal growth of a layer of thick oxygen after NP formation and before CT formation. It reduces the number of defects at the termination Silicon and Oxide interface while it does not require an additional number of photolithography plates. It helps to promote the reliability of the product.
The manufacturing method of the structure for improving the reliability of the vertical power device according to the second embodiment of the present invention can form a vertical power device including a vertical superjunction power device, and the differences between the method according to the first embodiment of the present invention include:
as shown in fig. 4, in the method according to the second embodiment of the present invention, after the source region 16 is formed and before the first thermal oxide layer 17 is formed, the method further includes the steps of:
a superjunction structure is formed in the drift region 12, the superjunction structure being formed by alternating columns of the second conductivity type formed in selected regions of the drift region 12 and columns of the first conductivity type formed in the drift region 12 between the columns of the second conductivity type 18.
In some embodiment methods, the second conductivity type pillars 18 are formed by multiple second conductivity type ion implants. With a typical 80V SJ MOSFET, the P pillars, i.e., the second conductivity type pillars 18, are implanted with 5-10 ions at a single dose3e12～1e13cm 2 The energy of implantation is between 100 and 3500keV, and the implanted impurity is Boron. In the implementation process, the position of the P column is placed behind the NP to minimize the thermal process and reduce the lateral diffusion of the P column, thereby increasing the conduction channel of the N-type drift region.
In some embodiments, the method can also be: the step of forming the second conductivity type pillars 18 includes:
forming a superjunction groove;
the second conductivity type epitaxial layer is filled in the superjunction trench to form a second conductivity type pillar 18.
The method of filling the super-junction trench can make the depth of the second conductive type column 18 deeper, and is suitable for manufacturing vertical super-junction power devices with higher withstand voltage, for example, a 600V SJ MOSFET can be manufactured.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims (18)

1. The structure for improving the reliability of the vertical power device is characterized in that the vertical power device comprises a device unit area and a terminal area, wherein the terminal area surrounds the periphery of the device unit area;
forming a channel region doped with a second conductivity type on the surface region of the first epitaxial layer doped with the first conductivity type;
the first epitaxial layer at the bottom of the channel region is used as a drift region;
a back electrode region is formed at the bottom of the drift region, and a back electrode formed by a back metal layer is formed on the back of the back electrode region;
a plurality of parallel device units are formed in the device unit area; each device unit comprises a trench gate;
the trench gate comprises a gate trench, a gate dielectric layer formed on the inner side surface of the gate trench and a gate conductive material layer filled in the gate trench; the gate trench penetrates through the channel region, and the surface of the channel region laterally covered by the gate conductive material layer is used for forming a conductive channel;
each device unit further comprises a source region which is heavily doped with the first conductivity type, and the source region is formed on the surface of the channel region and is self-aligned with the corresponding side surface of the trench gate;
A plurality of second groove structures are included in the terminal region, the second groove structures comprise second grooves, second dielectric layers formed on inner side surfaces of the second grooves and second conductive material layers filled in the second grooves; the second trench passes through the channel region;
each gate trench and each second trench are arranged in parallel;
a first thermal oxide layer covers all regions of the termination region in which the first thermal oxide layer is formed by directly thermally oxidizing a material of the first epitaxial layer and a material of a second conductive material layer in a surface region of the channel region and the device cell region in which the first thermal oxide layer is formed by directly thermally oxidizing a material of the first epitaxial layer in a surface region of the source region, a material of the first epitaxial layer in a surface region of the channel region outside the source region, and a material of a gate conductive material layer;
the composition structure of the transverse withstand voltage terminal structure comprises a plurality of second groove structures, channel regions, drift regions and first thermal oxide layers which are transversely arranged, and the reliability of the vertical power device is improved by utilizing the interface characteristics between materials of the first thermal oxide layers and the first epitaxial layers and the continuous extending structure of the first thermal oxide layers in the terminal regions and the device unit regions without etching.
2. The structure for improving reliability of vertical power device of claim 1, wherein: impurities of the channel region and the source region are driven by a thermal process of thermal oxidation of the first thermal oxide layer.
3. The structure for improving reliability of vertical power device of claim 1, wherein: the thickness of the first thermal oxide layer meets the thickness requirement of an interlayer film, and the interlayer film consists of the first thermal oxide layer;
alternatively, the first thermal oxide layer is used as a bottom part of an interlayer film, a deposition oxide layer is further formed on the surface of the first thermal oxide layer, and the interlayer film is formed by laminating the first thermal oxide layer and the deposition oxide layer.
4. The structure for improving reliability of vertical power device of claim 3, wherein: the grid electrode conductive material layer is connected to a grid electrode formed by the front metal layer through a through hole which penetrates through the interlayer film and corresponds to the top of the grid electrode conductive material layer;
the source region is connected to a source electrode formed by the front metal layer through the through hole corresponding to the top;
the second conductive material layer is a floating structure or is connected to the back electrode.
5. The structure for improving reliability of vertical power device of claim 1, wherein: the vertical power device is a vertical superjunction power device, a superjunction structure is formed in the drift region, and the superjunction structure is formed by alternately arranging second conductive type columns formed in a selected region of the drift region and first conductive type columns formed in the drift region between the second conductive type columns.
6. The structure for improving reliability of vertical power device according to claim 5, wherein: the second conductive type column extends downwards from the top surface of the first epitaxial layer formed with the trench gate, the second trench structure, the channel region and the source region, and comprises a superposition structure of second conductive type ion implantation regions or comprises a second conductive type epitaxial layer filled in a super junction trench.
7. The structure for improving reliability of vertical power device according to claim 1 or 5, wherein: the vertical power device includes a MOSFET or an IGBT, the MOSFET including a trench gate MOSFET or an SGT MOSFET.
8. The structure for improving reliability of vertical power device of claim 1, wherein: the grid electrode groove and the second groove are provided with process structures which are formed simultaneously by adopting the same process;
The gate dielectric layer and the second dielectric layer are made of the same material and are formed simultaneously;
the gate conductive material layer and the second conductive material layer are formed of the same material and simultaneously.
9. The structure for improving reliability of vertical power device of claim 8, wherein: and the gate conductive material layer is made of polysilicon.
10. The manufacturing method of the structure for improving the reliability of the vertical power device is characterized by comprising the following steps of:
providing a semiconductor substrate, wherein a first epitaxial layer doped with a first conductivity type is formed on the front surface of the semiconductor substrate;
simultaneously forming a plurality of trench gates in a device cell region and a plurality of second trench structures in a termination region, the termination region surrounding a periphery of the device cell region; the trench gate comprises a gate trench, a gate dielectric layer formed on the inner side surface of the gate trench and a gate conductive material layer filled in the gate trench; the second groove structure comprises a second groove, a second dielectric layer formed on the inner side surface of the second groove and a second conductive material layer filled in the second groove; each gate trench and each second trench are arranged in parallel;
Performing ion implantation of a second conductivity type to form a channel region in a surface region of the first epitaxial layer of the device cell region and the termination region; the gate trench penetrates through the channel region, and the surface of the channel region laterally covered by the gate conductive material layer is used for forming a conductive channel; the second trench passes through the channel region;
performing ion implantation of heavy doping of the first conductivity type on the surface area of the channel region in the selected area of the device unit region to form a source region of each device unit, wherein the source region and the corresponding side surface of the trench gate are self-aligned;
performing thermal oxidation to form a first thermal oxide layer, wherein the first thermal oxide layer covers all areas of the terminal area and the device unit area, and in the terminal area, the first thermal oxide layer directly performs thermal oxidation to the material of the first epitaxial layer and the material of the second conductive material layer in the surface area of the channel area; in the device unit region, the first thermal oxidation layer directly performs the thermal oxidation formation on the material of the first epitaxial layer in the surface region of the source region, the material of the first epitaxial layer in the surface region of the channel region outside the source region, and the material of the gate conductive material layer; the composition structure of the transverse withstand voltage terminal structure comprises a plurality of second groove structures, channel regions, drift regions and first thermal oxide layers which are transversely arranged, and the reliability of the vertical power device is improved by utilizing the interface characteristics between materials of the first thermal oxide layers and the first epitaxial layers and the continuous extending structure of the first thermal oxide layers in the terminal regions and the device unit regions without etching.
11. The method of manufacturing a structure for improving reliability of a vertical power device of claim 10, wherein: impurities of the channel region and the source region are driven in by a thermal process of the thermal oxidation of the first thermal oxide layer.
12. The method of manufacturing a structure for improving reliability of a vertical power device of claim 10, wherein: the ion implantation of the channel region adopts full-scale common implantation or selective ion implantation defined by a photoetching plate;
the ion implantation of the source region adopts selective ion implantation defined by a photoetching plate.
13. The method of manufacturing a structure for improving reliability of a vertical power device of claim 10, wherein: the thickness of the first thermal oxide layer meets the thickness requirement of an interlayer film, and the interlayer film consists of the first thermal oxide layer;
alternatively, the method further comprises:
and forming a deposition oxide layer on the surface of the first thermal oxide layer by adopting a CVD deposition process, and forming the interlayer film by laminating the first thermal oxide layer and the deposition oxide layer.
14. The method of manufacturing a structure for improving reliability of a vertical power device of claim 13, further comprising:
Forming a through hole penetrating the interlayer film;
forming a front metal layer and patterning the front metal layer to form a source electrode and a grid electrode;
the grid electrode conductive material layer is connected to the grid electrode through the through holes corresponding to the tops;
the source region is connected to the source electrode through the through hole corresponding to the top;
the second conductive material layer is a floating structure or is connected to the back electrode.
15. The method of manufacturing a structure for improving reliability of a vertical power device of claim 10, wherein: the vertical power device is a vertical superjunction power device, and further comprises the steps after the source region is formed and before the first thermal oxide layer is formed:
a superjunction structure is formed in the drift region, the superjunction structure being formed by alternating columns of the second conductivity type formed in selected regions of the drift region and columns of the first conductivity type formed in the drift region between the columns of the second conductivity type.
16. The method of manufacturing a structure for improving reliability of a vertical power device of claim 15, wherein: the second conductive type column is formed by a plurality of second conductive type ion implantations;
Alternatively, the forming of the second conductivity type pillar includes:
forming a superjunction groove;
and filling a second conductive type epitaxial layer in the super junction groove to form the second conductive type column.
17. The method for manufacturing a structure for improving reliability of a vertical power device according to claim 10 or 15, wherein: the vertical power device includes a MOSFET or an IGBT, the MOSFET including a trench gate MOSFET or an SGT MOSFET.
18. The method of manufacturing a structure for improving reliability of a vertical power device of claim 10, wherein: and the gate conductive material layer is made of polysilicon.
CN202311625400.7A 2023-11-29 2023-11-29 Structure for improving reliability of vertical power device and manufacturing method thereof Pending CN117497596A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311625400.7A CN117497596A (en) 2023-11-29 2023-11-29 Structure for improving reliability of vertical power device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311625400.7A CN117497596A (en) 2023-11-29 2023-11-29 Structure for improving reliability of vertical power device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN117497596A true CN117497596A (en) 2024-02-02

Family

ID=89674626

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311625400.7A Pending CN117497596A (en) 2023-11-29 2023-11-29 Structure for improving reliability of vertical power device and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN117497596A (en)

Similar Documents

Publication Publication Date Title
JP2662217B2 (en) Vertical gate semiconductor device and method of manufacturing the same
JP5089284B2 (en) Semiconductor device having a space-saving edge structure
US8445958B2 (en) Power semiconductor device with trench bottom polysilicon and fabrication method thereof
US8735249B2 (en) Trenched power semiconductor device and fabrication method thereof
CN111509035B (en) Low-cost high-performance groove type power semiconductor device and preparation method thereof
CN109888005B (en) Reverse-conducting super-junction IGBT device and manufacturing method thereof
CN107342326B (en) Power semiconductor device capable of reducing on-resistance and manufacturing method thereof
KR20080032080A (en) Charge balance field effect transistor
TW202006956A (en) Power MOSFET with an integrated pseudo-Schottky diode in source contact trench
US9000516B2 (en) Super-junction device and method of forming the same
US6087224A (en) Manufacture of trench-gate semiconductor devices
CN111370463A (en) Trench gate power device and manufacturing method thereof
CN106129105B (en) Trench gate power MOSFET and manufacturing method
CN114038914A (en) Double-withstand-voltage semiconductor power device and preparation method thereof
CN117410347A (en) Super junction power device with low terminal area and preparation method
CN113889523B (en) Semiconductor device based on three-dimensional grid field plate structure and manufacturing method thereof
CN111200025A (en) Super junction device and manufacturing method thereof
CN112216743A (en) Trench power semiconductor device and manufacturing method
JP2941823B2 (en) Semiconductor device and manufacturing method thereof
CN117497596A (en) Structure for improving reliability of vertical power device and manufacturing method thereof
CN210156383U (en) Super junction power semiconductor device
US6228698B1 (en) Manufacture of field-effect semiconductor devices
CN112864248A (en) SGTMOSFET device and manufacturing method
CN112447844A (en) Method for manufacturing semiconductor device
JP2006332232A (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination