CN117492296A

CN117492296A - Array substrate and display panel

Info

Publication number: CN117492296A
Application number: CN202311418507.4A
Authority: CN
Inventors: 骆官水; 李子然; 苏东明; 张子豪
Original assignee: TCL Huaxing Photoelectric Technology Co Ltd; Huizhou China Star Optoelectronics Display Co Ltd
Current assignee: TCL Huaxing Photoelectric Technology Co Ltd; Huizhou China Star Optoelectronics Display Co Ltd
Priority date: 2023-10-27
Filing date: 2023-10-27
Publication date: 2024-02-02

Abstract

The application discloses an array substrate and a display panel. The array substrate is provided with a groove on one surface of the insulating layer, which is away from the substrate, and at least part of the pixel electrodes are arranged in the groove. Therefore, the height difference between the surface of the pixel electrode far away from the substrate and the surface of the insulating layer far away from the substrate can be reduced, so that the liquid crystal pretilt angle at the edge of the pixel electrode is consistent with the liquid crystal pretilt angle at the surface of the insulating layer. The pretilt angle of the liquid crystal at each position causes uniform light transmission at each position, so that the problems of light leakage caused by gradient of the edges of the pixel electrodes and contrast reduction caused by light leakage are solved, and the contrast of the display panel in dark state and low gray scale state is improved. By adopting the display panel comprising the array substrate, the contrast ratio can be improved, and the light transmission is more uniform.

Description

Array substrate and display panel

Technical Field

The application belongs to the technical field of display, and particularly relates to an array substrate and a display panel.

Background

As shown in fig. 1, the insulating layer in the current array substrate is a flat surface. The pixel electrode is arranged on the insulating layer, and liquid crystal molecules are filled on the pixel electrode after the cell is formed. The pretilt angle formed by the liquid crystal molecules located at the middle portion of the pixel electrode and the liquid crystal molecules located at the surface of the insulating layer is relatively uniform, about 1 °. Since the surface of the insulating layer, on which the pixel electrode is disposed, is a flat surface, the edge of the pixel electrode has a slope with respect to the surface of the insulating layer, so that the pretilt angle formed by the aligned liquid crystal molecules at the edge of the pixel electrode is larger, about 46 °. When the display panel including the array substrate is in a dark state or a low gray level state, light is easily leaked from the edges of the pixel electrodes due to the large pretilt angle of the liquid crystal at the edges of the pixel electrodes, resulting in a problem of reduced contrast of the display panel.

Therefore, there is a need for an array substrate that can make pretilt angles of liquid crystal molecules more uniform throughout, thereby alleviating the problem of contrast reduction caused by light leakage.

Disclosure of Invention

An object of the present application is to provide an array substrate, by reducing the difference in the height between the pixel electrode and the insulating layer, the pretilt angle of the liquid crystal on the surface of the pixel electrode, the edge of the pixel electrode and the surface of the insulating layer is consistent, so as to alleviate the problem of light leakage and the contrast reduction caused by the light leakage.

In order to solve the technical problem, the application provides an array substrate, which comprises a substrate, an array layer, an insulating layer and a pixel electrode which are sequentially stacked. Wherein the array layer includes a driving device. The insulation layer is provided with a through hole penetrating through the driving device, one surface of the insulation layer, which is away from the substrate, is provided with a groove, and the groove is circumferentially arranged on the periphery of the through hole. At least part of the pixel electrode is arranged in the groove, and the pixel electrode is electrically connected with the driving device through the through hole.

In some embodiments, the groove is at least partially arcuate.

In some embodiments, the arcuate surface is an arcuate surface having a radius of curvature greater than or equal to 5 microns.

In some embodiments, the pixel electrode is disposed entirely within the recess, and a surface of the pixel electrode facing away from the insulating layer is flush with a surface of the insulating layer facing away from the substrate.

In some embodiments, the groove comprises a first sub-groove and a second sub-groove, the second sub-groove in communication with the first sub-groove.

The pixel electrode comprises a main electrode and a branch electrode, one end of the branch electrode is connected with the main electrode, the main electrode is arranged in the first sub-groove, and the branch electrode is arranged in the second sub-groove.

In some embodiments, the groove further comprises a connection groove, through which the second sub-groove communicates with the through hole.

The pixel electrode further comprises a connecting electrode, one end of the connecting electrode is connected with the other end of the branch electrode, the other end of the connecting electrode is connected with the driving device, and the connecting electrode is arranged in the connecting groove and the through hole.

In some embodiments, the array layer comprises:

an active layer disposed on the substrate;

a first insulating layer disposed on the active layer;

the grid electrode is arranged on the first insulating layer;

the grid insulation layer is arranged on the grid, and a first via hole and a second via hole penetrating to the active layer are formed in the grid insulation layer;

the source drain layer is arranged on the gate insulating layer, the source drain layer comprises a source electrode and a drain electrode, the source electrode is connected to one side of the active layer through the first via hole, and the drain electrode is connected to the other side of the active layer through the second via hole so as to form the driving device.

The pixel electrode is connected with the drain electrode through the through hole.

In some embodiments, the insulating layer includes a second insulating layer disposed on the source drain layer. The insulating layer further includes a passivation layer disposed on the second insulating layer.

In some embodiments, the insulating layer is a passivation layer disposed on the source drain layer.

The application also provides a display panel, which comprises any one of the array substrates, a liquid crystal layer and a color film substrate, wherein the color film substrate is arranged opposite to the array substrate, and the liquid crystal layer is positioned between the color film substrate and the array substrate.

The liquid crystal layer comprises liquid crystal, the liquid crystal is arranged on one surface of the pixel electrode, which is far away from the substrate, and the liquid crystal is further arranged on one surface of the insulating layer, which is far away from the substrate, and the difference between the pretilt angle of the liquid crystal on one surface of the pixel electrode, which is far away from the substrate, and the absolute value of the pretilt angle of the liquid crystal on one surface of the insulating layer, which is far away from the substrate, is smaller than 10 degrees.

The array substrate provided by the embodiment of the application is provided with the groove on one surface of the insulating layer, which is away from the substrate, and at least part of pixel electrodes are arranged in the groove. Therefore, the height difference between the surface of the pixel electrode far away from the substrate and the surface of the insulating layer far away from the substrate can be reduced, so that the liquid crystal pretilt angle at the edge of the pixel electrode is consistent with the liquid crystal pretilt angle at the surface of the insulating layer. The pretilt angle of the liquid crystal on the surface of the pixel electrode is also consistent with that of the insulating layer. The pretilt angle of the liquid crystal at each position causes uniform light transmission at each position, so that the problems of light leakage caused by gradient of the edges of the pixel electrodes and contrast reduction caused by light leakage are solved, and the contrast of the display panel in dark state and low gray scale state is improved. The embodiment of the application also provides a display panel comprising the array substrate, which has the advantages of improved contrast and more uniform light transmission.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic cross-sectional structure of an array substrate of the prior art;

fig. 2 is a schematic cross-sectional structure of an array substrate according to an embodiment of the present disclosure;

FIG. 3 is a schematic cross-sectional view of another embodiment of an array substrate;

fig. 4 is a scanning electron microscope characterization diagram of a groove of an array substrate provided in an embodiment of the present application;

fig. 5 is a schematic structural diagram of a groove of an array substrate according to an embodiment of the present disclosure;

fig. 6 is a schematic top view of an array substrate according to an embodiment of the present disclosure;

fig. 7 is a schematic cross-sectional structure of the liquid crystal at a and disposed at a in fig. 6;

fig. 8 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram of step 30 in FIG. 8;

FIG. 10 is a schematic diagram of the structure of step 40 in FIG. 8;

FIG. 11 is a scanning electron microscope characterization of the photoresist of step 30 of FIG. 8;

fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present application.

Reference numerals: a display panel 1000; an array substrate 100; a liquid crystal layer 200; a color film substrate 300;

a substrate 110; an array layer 120; a driving device E; an active layer 121; a first insulating layer 122; a gate electrode 123; a gate insulating layer 124; a source drain layer 125; a source 1251; a drain 1252; an insulating layer 130; a second insulating layer 131; a passivation layer 132; a pixel electrode 140; a pixel electrode material layer 140'; a backbone electrode 141; a branch electrode 142; a sub-dry electrode 143; a connection electrode 144; a liquid crystal 201;

a photoresist M; a boss M1; a recessed portion M2; a concave-convex structure W; a protection point D;

an opening K; a through hole H; a groove U; a first sub-groove U1; a second sub-groove U2; a third sub-groove U3; a connection groove U4; a first via T1; a second via T2; a first gas G1; a second gas G2; a third gas G3; pretilt angle α; a first direction X; a second direction Y.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.

It should be noted that, in the description of the present application, it should be understood that the directions or positional relationships indicated by "upper", "lower", "front", "rear", "left", "right", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements to be referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.

Referring to fig. 2, fig. 2 is a schematic structural diagram of an array substrate 100 according to an embodiment of the disclosure. The array substrate 100 includes a base 110, an array layer 120, an insulating layer 130, and a pixel electrode 140, which are sequentially stacked, wherein the array layer 120 includes a driving device E. The insulating layer 130 is provided with a through hole H penetrating to the driving device E. The insulating layer 130 is provided with a recess U on a side facing away from the substrate 110. The groove U is circumferentially arranged on the periphery of the through hole H. At least part of the pixel electrode 140 is disposed in the groove U. The through hole H exposes a portion of the driving device E, and the pixel electrode 140 is electrically connected to the driving device E through the through hole H.

In the array substrate 100 provided in this embodiment, a groove U is formed on a surface of the insulating layer 130 facing away from the substrate 110, and at least a portion of the pixel electrode 140 is disposed in the groove U. Thereby, a difference in height between the surface of the pixel electrode 140 away from the substrate 110 and the surface of the insulating layer 130 away from the substrate 110 can be reduced, so that the pretilt angle of the liquid crystal at the edge of the pixel electrode 140 is identical to the pretilt angle of the liquid crystal at the surface of the insulating layer 130. The pretilt angle of the liquid crystal on the surface of the pixel electrode 140 is also identical to that of the insulating layer 130. The pretilt angle of the liquid crystal at each position causes uniform light transmission at each position, so that the problems of light leakage caused by gradient of the edge of the pixel electrode 140 and contrast reduction caused by light leakage are solved, and the contrast of the display panel in a dark state and a low gray level state is improved. Pretilt angle refers to the angle formed between the long axis of the liquid crystal molecules and the alignment layer, in which the liquid crystal molecules are aligned on the alignment layer. Referring to fig. 7, with reference to a direction perpendicular to a plane of the substrate 110, a pretilt angle α in the present application refers to an angle of a long axis of a liquid crystal molecule deviating from the reference direction.

Specifically, the array layer 120 includes an active layer 121, a first insulating layer 122, a gate electrode 123, a gate insulating layer 124, and a source drain layer 125, which are sequentially stacked. The gate insulating layer 124 is provided with a first via T1 and a second via T2 penetrating to the active layer 121. The source drain layer 125 includes a source electrode 1251 and a drain electrode 1252. The source electrode 1251 is connected to one side of the active layer 121 through a first via T1, and the drain electrode 1252 is connected to the other side of the active layer 121 through a second via T2 to constitute a driving device E. The pixel electrode 140 is connected to the drain electrode 1252 through a via hole H.

In the embodiment of the present application, the driving device E is a thin film transistor to supply driving power to the operating devices disposed on the array substrate 100. Alternatively, the driving device E may be a thin film transistor of other structures, such as a bottom gate thin film transistor, a double gate thin film transistor, or the like. The present application is not limited in this regard.

In the present embodiment, the insulating layer 130 includes a second insulating layer 131. The second insulating layer 131 is disposed on the source/drain layer 125 to prevent the source/drain layer 125 from shorting with the pixel electrode 140 disposed on the source/drain layer 125 and failing. The insulating layer 130 further includes a passivation layer 132, where the passivation layer 132 is disposed on the second insulating layer 131, and on the basis of insulation, a metal layer in the driving device E may be protected, so that the source drain layer 125, the active layer 121, and the gate electrode 123 are not easily oxidized to delay the corrosion rate.

Optionally, the insulating layer 130 may also include a planarization layer. The planarization layer may be used to planarize the film surface, thereby making the film thickness disposed on the planarization layer uniform and reducing film defects.

Referring to fig. 3, fig. 3 is a schematic cross-sectional structure of an array substrate 100 according to an embodiment of the disclosure. Fig. 3 differs from fig. 2 in that: the insulating layer 130 is a passivation layer 132. A passivation layer 132 is disposed on the source drain layer 125. It is understood that only one passivation layer 132, which may be insulating, may be provided to insulate the source and drain layers 125 and the pixel electrode 140 and protect the metal layer in the driving device E. Meanwhile, a film layer can be saved, and the thickness of the array substrate 100 can be reduced.

Referring to fig. 4 and fig. 5, fig. 4 is a diagram illustrating a scanning electron microscope characterization of a groove U of an array substrate 100 according to an embodiment of the present application. It should be noted that fig. 4 is a representation of the process before the grooves U have been formed, the pixel electrodes 140 have not been formed, and the photoresist M has not been stripped. The left side of fig. 4 is a groove U and the right side is shown as photoresist M. Fig. 5 is a schematic structural diagram of a groove U of the array substrate 100 according to an embodiment of the present disclosure. In this embodiment, the groove U is at least partially a cambered surface.

In the manufacturing process, a photoresist M needs to be disposed on the insulating layer 130 as a mask to pattern the insulating layer 130 to form the grooves U. Since the photoresist M having the cambered surface concave portion M2 is easier to manufacture and has higher precision, the groove U formed by etching the insulating layer 130 using the photoresist M as a mask also includes a cambered surface. Specifically, the groove U is at least partially a cambered surface. The pixel electrode 140 is disposed in the insulating layer 130 along with the sagging arc groove U, so that a difference in topography height between the surface of the pixel electrode 140 away from the substrate 110 and the surface of the insulating layer 130 away from the substrate 110 is reduced, thereby making the pretilt angle α of the liquid crystal of the pixel electrode 140 surface, the pixel electrode 140 edge, and the insulating layer 130 surface uniform. The liquid crystal light leakage at the edge of the pixel electrode 140 is alleviated.

In the embodiment of the application, the arc surface is an arc surface, and the radius of curvature R of the arc surface is greater than or equal to 5 micrometers (μm). The radius of curvature R referred to in the present application refers to the principal curvature of the arc surface curvature. The principal curvature refers to the degree to which an arc surface is curved along its normal direction at a point on the arc surface. The radius of curvature R of the circular arc surface in this application is the radius of curvature R of the principal curvature of the circular arc surface. The larger the radius of curvature R of the circular arc surface, the more uniform the depth d1 of the groove U, and thus the more uniform the thickness of the pixel electrode 140 disposed in the groove U. Since uniformity of thickness of the pixel electrode 140 affects uniformity of an electric field, the larger the radius of curvature R, the more uniform the thickness of the pixel electrode 140, and the more uniform the electric field intensity between the pixel electrode 140 and the common electrode, and thus the liquid crystal between the pixel electrode 140 and the common electrode is inverted to be uniform and displayed uniformly.

Alternatively, the radius of curvature R of the circular arc surface may be 5.15 μm to 7.38 μm. Specifically, the radius of curvature R of the circular arc surface may be 5.15 μm, 5.2 μm, 5.5 μm, 5.68 μm, 5.9 μm, 6.05 μm, 6.2 μm, 6.36 μm, 6.4 μm, 6.88 μm, 7.013 μm, 7.256 μm, 7.38 μm or the like. In this embodiment, the radius of curvature R of the circular arc surface is 7.013 μm.

Optionally, the uniformity of the recess U may be further improved by adjusting parameters of the exposure process or material composition of the photoresist M, so that the thickness of the pixel electrode 140 is more uniform.

Since the pixel electrode 140 is disposed in the groove U, the width d2 of the groove U and the width of the pixel electrode 140 are equal. In the present embodiment, the width d2 of the groove U is 3 μm, but the present application is not limited thereto. In view of the manufacturing accuracy, both the positive and negative tolerance of the width d2 of the groove U are 0.3 μm. The width d2 of the groove U may be 2.5 μm, 3.5 μm, 4 μm, etc. according to actual needs. As shown in FIG. 4, the depth d1 of the groove U was 0.16 μm, and both the positive and negative tolerances were 0.02 μm. The depth d1 of the groove U in the present application refers to the maximum depth of the groove U, i.e. the height between the bottommost portion of the cambered groove U and the surface of the insulating layer 130 away from the substrate 110. The actual groove U depth d1 of the present embodiment is 0.1623 μm and the thickness of the pixel electrode 140 is 0.06 μm. It is understood that the pixel electrode 140 is formed in the groove U, and thus the pixel electrode 140 includes a bottom portion having a cambered surface, and is attached to the bottom portion of the groove U. Alternatively, the pixel electrode 140 may be entirely recessed into the groove U of the insulating layer 130. That is, the pixel electrode 140 is completely disposed in the recess U, and a surface of the pixel electrode 140 facing away from the insulating layer 130 is flush with a surface of the insulating layer 130 facing away from the substrate 110. The surface of the pixel electrode 140 facing away from the insulating layer 130 is flush with the surface of the insulating layer 130 facing away from the substrate 110, such that a difference in height between the side of the pixel electrode 140 facing away from the substrate 110 and the side of the insulating layer 130 facing away from the substrate 110 is eliminated. The surface of the insulating layer 130 far from the substrate 110 and the surface of the pixel electrode 140 far from the substrate 110 are flat, and the difference between the pretilt angles α of the liquid crystals is further reduced, so that the pretilt angles α of the liquid crystals are equal. Therefore, the light transmittance of the liquid crystal at each position is consistent, and the display uniformity is improved.

Referring to fig. 6 and 7, fig. 6 is a schematic top view of an array substrate 100 according to an embodiment of the present application, and fig. 7 is a schematic cross-sectional structure of a liquid crystal at a and disposed at a in fig. 6. In this embodiment, the first direction X and the second direction Y are disposed to intersect. The groove U includes a first sub-groove U1, a second sub-groove U2, and a third sub-groove U3. The first sub-groove U1 and the third sub-groove U3 are arranged at intervals along the first direction X, and the first sub-groove U1 and the third sub-groove U3 extend along the second direction Y. The plurality of second sub-grooves U2 are arranged at intervals along the second direction Y, the second sub-grooves U2 are communicated with the first sub-grooves U1, and part of the second sub-grooves U2 are communicated with the third sub-grooves U3.

The pixel electrode 140 includes a main electrode 141, a sub-main electrode 143, and a sub-main electrode 142. In this embodiment, the electrode includes a main electrode 141 and two auxiliary electrodes 143, and the two auxiliary electrodes 143 are located at two sides of the main electrode 141. The sub-dry electrodes 143 and the main electrode 141 are arranged at intervals in the first direction X and extend in the second direction Y. The plurality of branch electrodes 142 are arranged at intervals along the second direction Y. One end of the branch electrode 142 is connected to the main electrode 141, and the other end of the branch electrode 142 is connected to the sub-electrode 143. The main electrode 141 is disposed in the first sub-groove U1, the branch electrode 142 is disposed in the second sub-groove U2, and the sub-electrode 143 is disposed in the third sub-groove U3.

It can be understood that the pixel electrodes 140 including the main electrode 141, the auxiliary electrode 143 and the branch electrode 142 are disposed in the grooves U on the insulating layer 130, and a surface of the pixel electrode 140 away from the substrate 110 is flat in topography transition with a surface of the insulating layer 130 away from the substrate 110. So that the pretilt angle α of the liquid crystal disposed at either the edge of the main electrode 141, the edge of the sub-electrode 143 or the edge of the sub-electrode 142 coincides with the pretilt angle α of the liquid crystal on the surface of the insulating layer 130. The situation height difference caused by accumulation of the pixel electrode 140 at the connection position of the first sub-groove U1 port, the second sub-groove U2 port or the third sub-groove U3 port is avoided, and the difference of the liquid crystal pretilt angles alpha is avoided to be large.

The groove U further includes a connection groove U4. Part of the second sub-groove U2 communicates with the through hole H through the connection groove U4. In this embodiment, part of the second sub-grooves U2 are communicated with the third sub-groove U3, the connecting groove U4 is communicated with two second sub-grooves U2, and the rest of the second sub-grooves U2 are closed. The pixel electrode 140 further includes a connection electrode 144. One end of the connection electrode 144 is connected to the other end of the branch electrode 142, and the other end of the connection electrode 144 is connected to the driving device E. The connection electrode 144 is disposed in the connection groove U4 and the through hole H.

Specifically, the connection groove U4 includes a connection section groove and an end groove. The second sub-groove U2 is communicated with the end groove through the connecting section groove. The end groove is arranged around the through hole H and is communicated with the through hole H. The connection electrode 144 includes a connection portion, an intermediate portion, and a through hole H portion. One end of the connection part is connected to the other end of the branch electrode 142, the other end of the connection part is connected to the middle part, and the middle part is connected to the through hole H part. In this embodiment, the connection electrode 144 includes two connection portions respectively connected to the other ends of the two branch electrodes 142.

The connection electrode 144 is adjacent to the branch electrode 142, and thus the electric field of the connection electrode 144 has an influence on the liquid crystal deflection. The connecting electrode 144 is placed in the connecting groove U4, so that uneven electric field caused by stacking at the U opening of the groove when the connecting electrode 144 is connected with the branch electrode 142 can be avoided. While the connection groove U4 may guide the connection electrode 144 to the through hole H so that the connection electrode 144 is disposed in the through hole H to be connected with the driving device E.

Referring to fig. 8 and 9, fig. 8 is a flowchart of a method for manufacturing the array substrate 100 according to the embodiment of fig. 2, and fig. 9 is a schematic structural diagram of each step in fig. 8. The application provides a preparation method of an array substrate 100, which comprises the following steps:

step S10, providing a substrate 110;

step S20, sequentially forming an array layer 120 and an insulating layer 130 on a substrate 110, the array layer 120 including a driving device E;

step S30, forming a through hole H penetrating to the driving device E on the insulating layer 130, forming a groove U on one surface of the insulating layer 130 away from the substrate 110, wherein the groove U is circumferentially arranged on the periphery of the through hole H;

in step S40, the pixel electrode 140 is formed in the groove U, and at least a portion of the pixel electrode 140 is located in the groove U. The pixel electrode 140 is electrically connected to the driving device E through the via hole H.

In the method for manufacturing the array substrate 100 according to the embodiment of the present application, the array substrate 100 according to the embodiment of fig. 2 is taken as an example, but is not limited thereto.

The preparation method of the array substrate 100 has simple preparation steps, and the prepared array substrate 100 can improve the contrast ratio of the display panel 1000.

The method for manufacturing the array substrate 100 of the embodiment of fig. 2 is described below.

Referring to fig. 8 to 11, in step S10, a substrate 110 is provided.

Specifically, the substrate 110 may be one of a glass substrate 110, a silicon substrate 110, a sapphire substrate 110, or a silicon dioxide substrate 110, but is not limited thereto.

The operation of step S20 is then performed.

In step S20, an array layer 120 and an insulating layer 130 are sequentially formed on a substrate 110, the array layer 120 including a driving device E.

Alternatively, the array layer 120 includes an active layer 121, a first insulating layer 122, a gate electrode 123, a gate insulating layer 124, and a source drain layer 125 (not shown in fig. 9 to 10) which are sequentially stacked. The gate insulating layer 124 is provided with a first via T1 and a second via T2 penetrating to the active layer 121. The source drain layer 125 includes a source electrode 1251 and a drain electrode 1252. Source 1251The drain electrode 1252 is connected to one side of the active layer 121 through the first via hole T1 and to the other side of the active layer 121 through the second via hole T2 to constitute a driving device E. The pixel electrode 140 is connected to the drain electrode 1252 through a via hole H. The insulating layer 130 includes a second insulating layer 131 and a passivation layer 132. The second insulating layer 131 is disposed on the source drain layer 125. The passivation layer 132 is disposed on the second insulating layer 131. The material of the second insulating layer 131 may be at least one of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide, or may be an organic material, which is not limited thereto. The passivation layer 132 may be made of silicon nitride (SiNx), silicon oxide (SiO ₂ ) Or one or a combination of several of silicon oxynitride (SiON), and can also be organic materials such as polyvinyl chloride (Polyvinyl Chloride, PVC) and the like.

The operation of step S30 is then performed.

In step S30, a through hole H penetrating to the driving device E is formed in the insulating layer 130, and a groove U is formed on a surface of the insulating layer 130 facing away from the substrate 110, where the groove U is circumferentially disposed on a peripheral side of the through hole H.

Specifically, referring to fig. 9, step S30 includes steps S31 to S33 in order:

first, the operation of step S31 is performed.

Referring to fig. 11, the protruding portion M1 and the recessed portion M2 of the photoresist M are shown in fig. 11. In step S31, a photoresist M is formed on a surface of the insulating layer 130 away from the substrate 110. The photoresist M includes an opening K, a convex portion M1, and a concave portion M2. The opening K exposes the insulating layer 130, the recess M2 is disposed on a peripheral side of the opening K, the protrusion M1 is connected to the recess M2, and the protrusion M1 is located on a side of the recess M2 away from the opening K.

In this embodiment, the photoresist M is exposed and developed, and the photoresist M forms an opening K, a convex portion M1, and a concave portion M2. The recess M2 includes an arc surface, so that the recess U formed after etching the recess M2 also includes an arc surface.

The operation of step S32 is then performed.

In step S32, the region of the insulating layer 130 corresponding to the opening K is etched to form a via H. The through hole H exposes a portion of the driving device E.

The region of the insulating layer 130 corresponding to the opening K of the photoresist M is a region formed by the through hole H, the region of the insulating layer 130 corresponding to the recess M2 is a region formed by the groove U, and the remaining regions of the insulating layer 130 not forming the through hole H and the groove U correspond to the region of the protrusion M1.

The region of the insulating layer 130 corresponding to the opening K is etched to form a via H, and the remaining portion of the insulating layer 130 is not etched due to the protection by the photoresist M.

The through hole H exposes a portion of the driving device E. In this embodiment, the driving device E is a thin film transistor. The structure of the thin film transistor is not limited and may be a top gate thin film transistor as shown in fig. 2. The thin film transistor may be a bottom gate thin film transistor, a single gate thin film transistor, a double gate thin film transistor, or the like. The driving device E may also be other driving devices E. Alternatively, the portion of the driving device E exposed is the drain electrode 1252 of the driving device E or a contact electrode electrically connected to the drain electrode 1252. The drain 1252 of the driving device E is located at the array layer 120. Alternatively, the pixel electrode 140 is directly connected to the drain electrode 1252 of the driving device E. The via H penetrates the insulating layer 130 to the array layer 120, exposing the drain electrode 1252 of the driving device E, so that the pixel electrode 140 is connected to the drain electrode 1252 of the driving device E. Alternatively, the pixel electrode 140 is connected to a contact electrode of the driving device E. The contact electrode of the driving device E is disposed on the insulating layer 130 and connected to the drain electrode 1252 of the driving device E. The pixel electrode 140 is electrically connected to the drain electrode 1252 through a contact electrode. The connection method of the pixel electrode 140 and the drain electrode 1252 of the driving device E is not limited, and the pixel electrode 140 and the drain electrode 1252 of the driving device E may be electrically connected.

The operation of step S33 is then performed.

In step S33, the photoresist M and the insulating layer 130 are etched by using the mixed gas of the first gas G1 and the second gas G2 to form a groove U, where the groove U is located on the peripheral side of the through hole H.

The first gas G1 of the mixed gas is used to ash the photoresist M. That is, the first gas G1 may thin the convex portion M1 and remove the concave portion M2. The second gas G2 is used to etch the exposed insulating layer 130 to form the recess U. The first gas G1 thins the protruding portion M1, removes the recessed portion M2, and etches the insulating layer 130 with the second gas G2, thereby greatly simplifying the process, forming the arc-shaped groove U of the insulating layer 130 in one step, and improving the manufacturing efficiency of the array substrate 100.

In the present embodiment, the first gas G1 is oxygen (O ₂ ) Other gases that can ash the photoresist M may be used. The second gas G2 may be chlorine (Cl) ₂ ) Nitrogen trifluoride (NF) ₃ ) Sulfur hexafluoride (SF) ₆ ) Or carbon tetrafluoride (CF) ₄ ) One or a combination of several of these gases, as long as the second gas G2 can dry etch the insulating layer 130.

In the present embodiment, the mixed gas includes a first gas G1O ₂ And a second gas G2SF ₆ 。SF ₆ May react with the insulating layer 130. SF under the same conditions ₆ The rate of etching the insulating layer 130 is relatively fast. Since the surface of the insulating layer 130 forming the groove U portion is shielded by the recess M2, the first gas G1O is used ₂ Thinning the convex part M1, removing the concave part M2, and simultaneously adopting SF ₆ The exposed insulating layer 130 after the concave part M2 is removed by rapid etching can form the groove U with good appearance, so that the preparation efficiency of the array substrate 100 is greatly improved, and the situation that the groove U cannot be formed is avoided.

Also, in step S32, a via hole H exposing the drain 1252 or the contact electrode is formed. SF under the same conditions ₆ The etching metal rate is slower, SF is adopted ₆ As the second gas G2, the drain electrode 1252 made of metal or the contact electrode may be reduced in loss in the process.

Thus, the operation of step S30 is completed, followed by the operation of step S40.

Specifically, referring to fig. 10, step S40 includes steps S41 to S44 in order:

in step S41, the insulating layer 130 is bombarded with the third gas G3, so that the particles sputtered by the insulating layer 130 form the protection points D on the protruding portions M1 of the photoresist M.

The third gas G3 may be argon (Ar), or other gases that may plasma bombard the insulating layer 130 to form the protection point D. In this embodiment, ar bombards the insulating layer 130, and the sputtered particles of the insulating layer 130 fall on the protruding portion M1 of the photoresist M to form a protection point D.

The operation of step S42 is then performed.

In step S42, the raised portion M1 of the photoresist M is ashed using the first gas G1 with the guard point D as a mask, and the uneven structure W is formed on the raised portion M1.

Since the first gas G1 does not etch the insulating layer 130, the raised portions M1 of the photoresist M are ashed with the first gas G1 using the guard points D formed by the particles of the insulating layer 130 as a mask for the raised portions M1, thereby forming the uneven structure W.

The operation of step S43 is then performed.

In step S43, a pixel electrode material layer 140' is formed on the insulating layer 130. The pixel electrode material layer 140 'covers the protrusion M1, the groove U, and the through hole H, and the pixel electrode material layer 140' is disposed to be disconnected in the region of the concave-convex structure W.

It can be understood that the bump structure W is formed at the bump M1, the pixel electrode material layer 140 'falls on the bump structure W, and the pixel electrode material layer 140' is broken at the bump structure W to form a gap due to a step formed by the bump structure W. The pixel electrode material layer 140' forms a gap at the concave-convex structure W to facilitate the subsequent peeling of the convex portion M1. The pixel electrode material layer 140' formed at the recess U and at the via hole H serves as the pixel electrode 140.

The operation of step S44 is then performed.

In step S44, the photoresist M and the pixel electrode material layer 140' on the protrusion M1 are stripped to form the pixel electrode 140.

Specifically, a stripping solution is added to strip the photoresist M. Since the pixel electrode material layer 140 'forms a gap at the concave-convex structure W, the stripping liquid can fully contact with the photoresist M below through the gap of the pixel electrode material layer 140' at the concave-convex structure W, on the one hand, the stripping efficiency of the photoresist M is improved, and on the other hand, the photoresist M can be completely stripped. Since the photoresist M is completely stripped, the shielding of light by the photoresist M is reduced, thereby improving the transmittance of light passing through the array substrate 100. The pixel electrode material layer 140 'located on the protrusion M1 is removed as the photoresist M is stripped, and the pixel electrode material layer 140' located at the groove U and the through hole H forms the pixel electrode 140. By forming the pixel electrode 140 at the groove U such that the pixel electrode 140 is disposed in the insulating layer 130, a difference in height between a surface of the pixel electrode 140 away from the substrate 110 and a surface of the insulating layer 130 away from the substrate 110 is reduced, so that a pretilt angle α of liquid crystal at an edge of the pixel electrode 140 is consistent with a pretilt angle α of liquid crystal at a surface of the insulating layer 130, light leakage at an edge of the pixel electrode 140 is reduced, and uniformity of light transmission of the display panel 1000 as a whole is improved.

Thus, the fabrication of the array substrate 100 of the present application is completed.

Referring to fig. 12, the present application further provides a display panel 1000, including any one of the above array substrates 100 or including any one of the above array substrates 100 prepared by the preparation method. The display panel 1000 further includes a liquid crystal layer 200 and a color film substrate 300. The color film substrate 300 is disposed opposite to the array substrate 100. The liquid crystal layer 200 is located between the color film substrate 300 and the array substrate 100.

The liquid crystal layer 200 includes liquid crystal. The liquid crystal is disposed on a side of the pixel electrode 140 away from the substrate 110, and also disposed on a side of the insulating layer 130 away from the substrate 110. The difference between the absolute value of the pretilt angle α of the liquid crystal at the side of the pixel electrode 140 remote from the substrate 110 and the pretilt angle α of the liquid crystal at the side of the insulating layer 130 remote from the substrate 110 is less than 10 degrees.

Alternatively, the difference between the absolute value of the pretilt angle α of the liquid crystal located at the side of the pixel electrode 140 remote from the substrate 110 and the pretilt angle α of the liquid crystal located at the side of the insulating layer 130 remote from the substrate 110 is less than 10 °, 8 °, 7 °, 5 °, 3 °, 2 °, 1.5 °, 1.2 °, 1 °, 0.6 °, 0.5 °, 0.3 °, or 0.2 °. It will be appreciated that the smaller the difference between the absolute value of the pretilt angle α of the liquid crystal on the side of the pixel electrode 140 away from the substrate 110 and the pretilt angle α of the liquid crystal on the side of the insulating layer 130 away from the substrate 110, the more uniform the angle of deflection of the liquid crystal under the influence of the electric field force, the more uniform the transmitted light, thereby reducing light leakage in the dark state or the low gray state and improving display uniformity. In the embodiment of the present application, the pretilt angle α of the liquid crystal of the pixel electrode 140 away from the surface of the substrate 110, the pretilt angle α of the liquid crystal of the edge of the pixel electrode 140, and the pretilt angle α of the insulating layer 130 away from the surface of the substrate 110 are all between 0.5 ° and 1.5 °. That is, the liquid crystal pretilt angle α of the present embodiment may be 0.5 °, 0.6 °, 0.7 °, 0.8 °, 0.9 °, 1 °, 1.1 °, 1.2 °, 1.3 °, 1.4 °, or 1.5 °. The difference between the absolute value of the pretilt angle α of the liquid crystal on the side of the pixel electrode 140 away from the substrate 110 and the pretilt angle α of the liquid crystal on the side of the insulating layer 130 away from the substrate 110 in this embodiment is less than 1 °, so as to effectively improve light leakage in a dark state or a low gray scale state and display uniformity.

The array substrate 100, the method for manufacturing the same, and the display panel 1000 provided in the present application are described in detail above.

The array substrate provided by the embodiment of the application is provided with the groove on one surface of the insulating layer far away from the substrate, and the pixel electrode is arranged in the groove. Therefore, the height difference between the surface of the pixel electrode far away from the substrate and the surface of the insulating layer far away from the substrate can be reduced, so that the liquid crystal pretilt angle at the edge of the pixel electrode is consistent with the liquid crystal pretilt angle at the surface of the insulating layer. The pretilt angle of the liquid crystal on the surface of the pixel electrode is also consistent with that of the insulating layer. The pretilt angle of the liquid crystal at each position causes uniform light transmission at each position, so that the problems of light leakage caused by gradient of the edges of the pixel electrodes and contrast reduction caused by light leakage are solved, and the contrast of the display panel in dark state and low gray scale state is improved. The embodiment of the application also provides a preparation method of the array substrate, which saves preparation steps and can improve the contrast ratio of the display panel by using the prepared array substrate. The embodiment of the application also provides a display panel comprising the array substrate, which has the advantages of improved contrast and more uniform light transmission.

Specific examples are set forth herein to illustrate the principles and embodiments of the present application, and the description of the examples above is only intended to assist in understanding the methods of the present application and their core ideas. It should be noted that it would be obvious to those skilled in the art that various improvements and modifications can be made to the present application without departing from the principles of the present application, and such improvements and modifications fall within the scope of the claims of the present application.

Claims

1. An array substrate is characterized by comprising a substrate, an array layer, an insulating layer and a pixel electrode which are sequentially stacked,

the array layer includes a driving device;

the insulation layer is provided with a through hole penetrating to the driving device, one surface of the insulation layer, which is away from the substrate, is provided with a groove, and the groove is circumferentially arranged on the periphery of the through hole;

at least part of the pixel electrode is arranged in the groove, and the pixel electrode is electrically connected with the driving device through the through hole.

2. The array substrate of claim 1, wherein the recess is at least partially arcuate.

3. The array substrate of claim 2, wherein the arc surface is an arc surface, and a radius of curvature of the arc surface is greater than or equal to 5 microns.

4. The array substrate of claim 1, wherein the pixel electrode is disposed entirely within the recess, and a surface of the pixel electrode facing away from the insulating layer is flush with a surface of the insulating layer facing away from the substrate.

5. The array substrate of claim 1, wherein the groove comprises a first sub-groove and a second sub-groove, the second sub-groove in communication with the first sub-groove;

6. The array substrate of claim 5, wherein the groove further comprises a connection groove through which the second sub-groove communicates with the through hole;

7. The array substrate of claim 1, wherein the array layer comprises:

an active layer disposed on the substrate;

a first insulating layer disposed on the active layer;

the grid electrode is arranged on the first insulating layer;

the source drain layer is arranged on the grid insulating layer, the source drain layer comprises a source electrode and a drain electrode, the source electrode is connected to one side of the active layer through the first via hole, and the drain electrode is connected to the other side of the active layer through the second via hole so as to form the driving device;

8. The array substrate of claim 7, wherein the insulating layer comprises a second insulating layer disposed on the source drain layer;

the insulating layer further includes a passivation layer disposed on the second insulating layer.

9. The array substrate of claim 7, wherein the insulating layer is a passivation layer, and the passivation layer is disposed on the source drain layer.

10. A display panel, characterized in that the display panel comprises the array substrate according to any one of claims 1 to 9, and further comprises a liquid crystal layer and a color film substrate, wherein the color film substrate is arranged opposite to the array substrate, and the liquid crystal layer is positioned between the color film substrate and the array substrate;