US20230122931A1 - Array substrate and manufacturing method thereof - Google Patents

Array substrate and manufacturing method thereof Download PDF

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US20230122931A1
US20230122931A1 US17/045,186 US202017045186A US2023122931A1 US 20230122931 A1 US20230122931 A1 US 20230122931A1 US 202017045186 A US202017045186 A US 202017045186A US 2023122931 A1 US2023122931 A1 US 2023122931A1
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layer
array substrate
manufacturing
liner
etching treatment
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US11791351B2 (en
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Zhiwei Tan
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TCL China Star Optoelectronics Technology Co Ltd
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TCL China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
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    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Definitions

  • the present disclosure relates to the field of display technologies, and particularly relates to an array substrate and a manufacturing method of the array substrate.
  • Thin film transistor liquid crystal displays (TFT-LCDs) occupy a leading position in a current flat panel display market due to their small sizes, low power consumption, and no radiation.
  • TFT-LCDs Thin film transistor liquid crystal displays
  • 4-mask process is widely used in industry and has a significant effect of saving processes.
  • a structure made by the copper manufacturing process is generally composed of a copper conductive layer and a liner layer (generally molybdenum or titanium). Due to a slow etching speed of the liner layer in a conventional etching solution system, it is necessary to extend etching time after the copper conductive layer is etched completely, so as to completely etch the liner layer and prevent metal residue.
  • CD loss critical dimension loss
  • the 4-mask process has a larger CD loss of the metal layer, resulting in a greater loss of the aperture ratio, and thus applications of the 4-mask process in the 8K display panels are limited.
  • a new array substrate and a manufacturing method of the array substrate need to be provided to solve the above technical problems.
  • An array substrate and a manufacturing method of the array substrate provided in the present disclosure solve technical problems that due to a slow etching speed of a liner layer in a conventional etching solution system, a CD loss of a copper conductive layer is too large, which results in a low aperture ratio.
  • An embodiment of the present disclosure provides a manufacturing method of an array substrate, including following steps:
  • S 10 providing a substrate, and sequentially laminating a first metal layer, an insulating layer, an amorphous silicon layer, an ohmic contact layer, a second metal layer, and a photoresist layer on the substrate, wherein the second metal layer includes a liner layer and a copper conductive layer sequentially laminated on the ohmic contact layer;
  • time periods for performing the first wet etching treatment and the second wet etching treatment on the copper conductive layer range between 50 seconds and 60 seconds respectively, and a material of the liner layer includes molybdenum.
  • an etching solution used in the first wet etching treatment and the second wet etching treatment on the copper conductive layer is a hydrogen peroxide solution
  • a material of the liner layer includes titanium or molybdenum titanium alloy.
  • an etching gas used in the first dry etching treatment on the liner layer, the ohmic contact layer, and the amorphous silicon layer includes a gaseous mixture containing sulfur hexafluoride and chlorine.
  • a mixing ratio of the sulfur hexafluoride and the chlorine is 1:10.
  • an edge of the source electrode and an edge of the drain electrode are flush with an edge of the liner layer.
  • the first metal layer includes gate electrodes and signal lines arranged at intervals from the gate electrodes.
  • the photoresist layer is formed by a positive photoresist.
  • An embodiment of the present disclosure provides a manufacturing method of an array substrate, including following steps:
  • S 10 providing a substrate, and sequentially laminating a first metal layer, an insulating layer, an amorphous silicon layer, an ohmic contact layer, a second metal layer, and a photoresist layer on the substrate, wherein the second metal layer includes a liner layer and a copper conductive layer sequentially laminated on the ohmic contact layer;
  • time periods for performing the first wet etching treatment and the second wet etching treatment on the copper conductive layer range between 50 seconds and 60 seconds respectively, and a material of the liner layer includes molybdenum.
  • an etching solution used in the first wet etching treatment and the second wet etching treatment on the copper conductive layer is a hydrogen peroxide solution
  • a material of the liner layer includes titanium or molybdenum titanium alloy.
  • an etching gas used in the first dry etching treatment on the liner layer, the ohmic contact layer, and the amorphous silicon layer includes a gaseous mixture containing sulfur hexafluoride and chlorine.
  • a mixing ratio of the sulfur hexafluoride and the chlorine is 1:10.
  • an edge of the source electrode and an edge of the drain electrode are flush with an edge of the liner layer.
  • the first metal layer includes gate electrodes and signal lines arranged at intervals from the gate electrodes.
  • the photoresist layer is formed by a positive photoresist.
  • a material of the first metal layer includes molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or a combination of above metals.
  • a material of the insulating layer is one of silicon nitride, silicon oxide, and silicon oxynitride.
  • An embodiment of the present disclosure provides the array substrate, manufactured by the above manufacturing method of the array substrate, including:
  • the ohmic contact layer disposed on the amorphous silicon layer
  • the source electrode and the drain electrode disposed on the liner layer, wherein the channel is arranged between the source electrode and the drain electrode, materials of the source electrode and the drain electrode consist of the copper conductive layer, and an edge of the source electrode and an edge of the drain electrode are flush with an edge of the liner layer.
  • a material of the liner layer is one of molybdenum, titanium, and molybdenum titanium alloy.
  • Beneficial effects of the present disclosure are: in the array substrate and the manufacturing method of the array substrate provided in the present disclosure, during a traditional 4-mask process, when the first wet etching and the second wet etching are performed on the second metal layer, the wet etching is stopped after the copper conductive layer is merely etched completely. At this time, the liner layer is retained completely. Because a wet etching speed of the liner layer is slow, the etching time of the wet etching and the CD loss can be greatly reduced, and the CD loss is smaller. Meanwhile, etching steps to the liner layer are added in a conventional dry etching process, so an entire CD loss of the second metal layer can be reduced to reduce a CD loss of metals and improve the aperture ratio.
  • FIG. 1 is a flow chart of a manufacturing method of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 2 A — FIG. 2 G are schematic views during a process of the manufacturing method of the array substrate provided by an embodiment of the present disclosure.
  • FIG. 3 is a sectional schematic view of the array substrate provided by an embodiment of the present disclosure.
  • mount can mean a permanent connection, a detachable connection, or an integrated connection. It can mean a mechanical connection, an electrical connection, or can communicate with each other. It can mean a direct connection, an indirect connection by an intermediate, or an inner communication or an interaction between two elements. Those skilled in the art should understand the specific meanings in the present disclosure according to specific situations.
  • a structure in which a first feature is “on” or “beneath” a second feature may include an embodiment in which the first feature directly contacts the second feature and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature does not directly contact the second feature.
  • a first feature “on,” “above,” or “on top of” a second feature may include an embodiment in which the first feature is right “on,” “above,” or “on top of” the second feature and may also include an embodiment in which the first feature is not right “on,” “above,” or “on top of” the second feature, or just means that the first feature has a sea level elevation greater than the sea level elevation of the second feature.
  • first feature “beneath,” “below,” or “on bottom of” a second feature may include an embodiment in which the first feature is right “beneath,” “below,” or “on bottom of” the second feature and may also include an embodiment in which the first feature is not right “beneath,” “below,” or “on bottom of” the second feature, or just means that the first feature has a sea level elevation less than the sea level elevation of the second feature.
  • the present disclosure herein provides many different embodiments or examples for realizing different structures of the present disclosure.
  • components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present disclosure.
  • reference numbers and/or letters may be repeated in different examples of the present disclosure. Such repetitions are for simplification and clearness, which per se do not indicate the relations of the discussed embodiments and/or settings.
  • the present disclosure provides examples of various specific processes and materials, but the applicability of other processes and/or application of other materials may be appreciated by a person skilled in the art.
  • the present disclosure is directed towards the array substrate and the manufacturing method of the array substrate provided in the prior art. Since the etching speed of the liner layer under the conventional etching solution system is relatively slow, the CD loss of the copper conductive layer is too large, which in turn leads to a low aperture ratio. The embodiments of the present disclosure can solve this defect.
  • an embodiment of the present disclosure provides a manufacturing method of an array substrate, including following steps:
  • S 10 providing a substrate 10 , and sequentially laminating a first metal layer 20 , an insulating layer 30 , an amorphous silicon layer 40 , an ohmic contact layer 50 , a second metal layer 60 , and a photoresist layer 70 on the substrate 10 , wherein the second metal layer 60 includes a liner layer 601 and a copper conductive layer 602 sequentially laminated on the ohmic contact layer 50 .
  • the above film layers may be sequentially formed on the substrate 10 by deposition, sputtering, or coating.
  • a raw material of the substrate 10 may be one of a glass substrate, a quartz substrate, and a resin substrate, etc.
  • the first metal layer 20 is disposed on the substrate 10 , and a material of the first metal layer 20 may be made of molybdenum, aluminum, aluminum nickel alloy, molybdenum tungsten alloy, chromium, or copper, or a combination of the above metals.
  • the first metal layer 20 is treated by means of a yellow light process to form gate electrodes and signal lines arranged at intervals from the gate electrodes.
  • the signal lines include scanning lines providing scanning signals for thin film transistors.
  • the insulating layer covers the first metal layer 20 and the substrate 10 , and a material of the insulating layer 30 is one of silicon nitride, silicon oxide, and silicon oxynitride.
  • the amorphous silicon layer 40 covers the insulating layer 30 to form an active layer.
  • the ohmic contact layer 50 covers the amorphous silicon layer 40 to prevent the second metal layer 60 from directly contacting with the amorphous silicon layer 40 .
  • the second metal layer 60 covers the ohmic contact layer 50 , and the second metal layer 60 includes the liner layer 601 and the copper conductive layer 602 sequentially laminated on the ohmic contact layer 50 .
  • the copper conductive layer 602 is used to form a source electrode 6021 and a drain electrode 6022 of the array substrate. Because copper particles in the copper conductive layer 602 are prone to diffuse into the ohmic contact layer 50 and the amorphous silicon layer 40 under the copper conductive layer 602 , which affects conductive characteristics of the copper conductive layer 602 , the liner layer 601 is arranged between the copper conductive layer 602 and the ohmic contact layer 50 .
  • an etching speed of the copper conductive layer 602 is faster than an etching speed of the liner layer 601 , in the embodiment of the present disclosure, a wet etching treatment is firstly performed on the copper conductive layer 602 , and after the copper conductive layer 602 is completely etched, the liner layer 601 still remains intact due to its slow etching speed or no etching, thereby preventing a CD loss of the copper conductive layer 602 from being too large and leading to a low aperture ratio when the etching of the copper conductive layer 601 is completed.
  • a material of the liner layer 601 includes molybdenum, titanium, or molybdenum titanium alloy. Above-mentioned purposes can be achieved by selecting a matching etching solution or controlling an etching time according to the material of the liner layer 601 .
  • the etching solution selected for the first wet etching treatment may be a copper acid etching solution.
  • time periods for performing the first wet etching treatment and the second wet etching treatment on the copper conductive layer 602 range between 50 seconds and 60 seconds respectively, during the period, the copper conductive layer 602 has been etched completely, while the liner layer is hardly etched due to the slow etching speed.
  • this method can reduce the etching time of the wet etching greatly.
  • the etching solution selected for performing the first wet etching treatment and the second wet etching treatment on the copper conductive layer 602 may be a hydrogen peroxide solution. Because the titanium or the molybdenum titanium alloy hardly reacts with the hydrogen peroxide solution, when the copper conductive layer 602 is etched, the liner layer 601 is also not etched.
  • the first dry etching treatment is performed on the liner layer 601 . That is to say, in a conventional dry etching process, an additional step for etching the liner layer 601 added can reduce an entire CD loss of the second metal layer 60 , so as to reduce the CD loss of the metals and improve the aperture ratio.
  • the liner layer 601 , the ohmic contact layer 50 , and the amorphous silicon layer 40 may be etched by a same dry etching treatment. And because above-mentioned processes are performed in a chamber of the same machine, no additional engineering sites are added, which improves production efficiency.
  • an etching gas used in the first dry etching treatment on the liner layer 601 , the ohmic contact layer 50 , and the amorphous silicon layer 40 includes a gaseous mixture containing sulfur hexafluoride and chlorine. Good etching effects may be obtained by using the gaseous mixture.
  • a mixing ratio of the sulfur hexafluoride and the chlorine is 1:10.
  • the ashing treatment is performed on the photoresist layer 70 positioned in the first region 100 to reduce a thickness of the photoresist layer 70 in the first region 100 or remove the photoresist layer 70 in the first region 100 completely, so as to expose the copper conductive layer 602 in the first region 100 and to make preparations for subsequent second wet etching treatment on the copper conductive layer 602 .
  • the copper conductive layer 602 positioned at the first region 100 is etched to form the source electrode 6021 and the drain electrode 6022 .
  • the photoresist layer 70 is formed by a positive photoresist.
  • a gas used in the ashing treatment is oxygen.
  • an edge of the source electrode 6021 and an edge of the drain electrode 6022 are flush with an edge of the liner layer 601 to guarantee the aperture ratio.
  • the photoresist layer 70 is peeled off from the second metal layer 60 , and then subsequent film layers are manufactured, such as pixel electrodes, etc.
  • the array substrate is a color filter on array (COA) substrate, a color resistance layer and a black matrix layer, etc. may further be manufactured.
  • COA color filter on array
  • an array substrate provided by an embodiment of the present disclosure is manufactured by the above manufacturing method.
  • the array substrate includes a substrate 10 , a first metal layer 20 disposed on the substrate 10 , an insulating layer 30 disposed on the first metal layer 20 , an amorphous silicon layer 40 disposed on the insulating layer 30 , an ohmic contact layer 50 disposed on the amorphous silicon layer 40 , a liner layer 601 disposed on the ohmic contact layer 50 , and a source electrode 6021 and a drain electrode 6022 disposed on the liner layer 601 .
  • the first metal layer 20 includes gate electrodes and signal lines arranged at intervals from the gate electrodes.
  • Material of the source electrode 6021 and the drain electrode 6022 consist of a copper conductive layer 602 .
  • a material of the liner layer 601 is one of molybdenum, titanium, and molybdenum titanium alloy. An edge of the source electrode 6021 and an edge of the drain electrode 6022 are flush with an edge of the liner layer 601 , which can reduce the CD loss of the copper conductive layer 602 greatly and guarantee an aperture ratio.
  • the beneficial effects of the present disclosure are: in the array substrate and the manufacturing method of the array substrate provided in the present disclosure, during a traditional 4-mask process, when the first wet etching and the second wet etching are performed on the second metal layer, the wet etching is stopped after the copper conductive layer is merely etched completely. At this time, the liner layer is retained completely. Because a wet etching speed of the liner layer is slow, the etching time of the wet etching and the CD loss can be greatly reduced, and the CD loss is smaller. Meanwhile, etching steps to the liner layer are added in a conventional dry etching process, so an entire CD loss of the second metal layer can be reduced to reduce a CD loss of metals and improve the aperture ratio.

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Abstract

The present disclosure provides an array substrate and a manufacturing method of the array substrate. In the manufacturing method of the array substrate, during performing a first wet etching and a second wet etching on a second metal layer, the wet etching is stopped when a copper conductive layer is merely etched completely. Because a wet etching speed of a liner layer is slow, an etching time of the wet etching and a CD loss of the copper conductive layer can be greatly reduced, and the CD loss is relatively small. Meanwhile, an entire CD loss of the second metal layer can be reduced, and an aperture ratio can be improved.

Description

    FIELD OF INVENTION
  • The present disclosure relates to the field of display technologies, and particularly relates to an array substrate and a manufacturing method of the array substrate.
    • BACKGROUND OF INVENTION
  • Thin film transistor liquid crystal displays (TFT-LCDs) occupy a leading position in a current flat panel display market due to their small sizes, low power consumption, and no radiation. At present, 4-mask process is widely used in industry and has a significant effect of saving processes.
  • With continuous upgrade of requirements for panels, 8K display panels have become a main direction for development of large-size panels. With improvement of resolution and sizes, a copper manufacturing process not only becomes a necessary technology, but also makes a copper thickness increasingly thicker. A structure made by the copper manufacturing process is generally composed of a copper conductive layer and a liner layer (generally molybdenum or titanium). Due to a slow etching speed of the liner layer in a conventional etching solution system, it is necessary to extend etching time after the copper conductive layer is etched completely, so as to completely etch the liner layer and prevent metal residue. However, this way leads to an excessively large critical dimension loss (CD loss) of the copper conductive layer, and the large CD loss causes a line width of a metal layer to be set too large, resulting in a low aperture ratio of the 8K display panels and a substantial increase in energy consumption.
  • In addition, because the metal layer needs to undergo two wet etching treatments, the 4-mask process has a larger CD loss of the metal layer, resulting in a greater loss of the aperture ratio, and thus applications of the 4-mask process in the 8K display panels are limited.
  • In summary, a new array substrate and a manufacturing method of the array substrate need to be provided to solve the above technical problems.
    • Technical Problems
  • An array substrate and a manufacturing method of the array substrate provided in the present disclosure solve technical problems that due to a slow etching speed of a liner layer in a conventional etching solution system, a CD loss of a copper conductive layer is too large, which results in a low aperture ratio.
    • Technical Solutions
  • In order to solve the above problems, the present disclosure provides technical solutions as followings:
  • An embodiment of the present disclosure provides a manufacturing method of an array substrate, including following steps:
  • S10: providing a substrate, and sequentially laminating a first metal layer, an insulating layer, an amorphous silicon layer, an ohmic contact layer, a second metal layer, and a photoresist layer on the substrate, wherein the second metal layer includes a liner layer and a copper conductive layer sequentially laminated on the ohmic contact layer;
  • S20: using the photoresist layer as a shielding layer and performing a first wet etching treatment on the copper conductive layer to expose a part of the liner layer;
  • S30: using the photoresist layer as the shielding layer and performing a first dry etching treatment on the liner layer, the ohmic contact layer, and the amorphous silicon layer;
  • S40: performing an ashing treatment on the photoresist layer positioned in a first region to expose a part of the copper conductive layer, and performing a second wet etching treatment on the copper conductive layer to expose the liner layer positioned in the first region, wherein a gas used in the ashing treatment is oxygen;
  • S50: using the photoresist layer as the shielding layer and performing a second dry etching treatment on the liner layer and the ohmic contact layer to form an active layer, a source electrode, a drain electrode, and a channel positioned between the source electrode and the drain electrode; and
  • S60: peeling off the photoresist layer.
  • According to the manufacturing method of the array substrate provided in an embodiment of the present disclosure, in the step S20 and the step S40, time periods for performing the first wet etching treatment and the second wet etching treatment on the copper conductive layer range between 50 seconds and 60 seconds respectively, and a material of the liner layer includes molybdenum.
  • According to the manufacturing method of the array substrate provided in an embodiment of the present disclosure, in the step S20 and the step S40, an etching solution used in the first wet etching treatment and the second wet etching treatment on the copper conductive layer is a hydrogen peroxide solution, and a material of the liner layer includes titanium or molybdenum titanium alloy.
  • According to the manufacturing method of the array substrate provided in an embodiment of the present disclosure, in the step S30, an etching gas used in the first dry etching treatment on the liner layer, the ohmic contact layer, and the amorphous silicon layer includes a gaseous mixture containing sulfur hexafluoride and chlorine.
  • According to the manufacturing method of the array substrate provided in an embodiment of the present disclosure, a mixing ratio of the sulfur hexafluoride and the chlorine is 1:10.
  • According to the manufacturing method of the array substrate provided in an embodiment of the present disclosure, an edge of the source electrode and an edge of the drain electrode are flush with an edge of the liner layer.
  • According to the manufacturing method of the array substrate provided in an embodiment of the present disclosure, the first metal layer includes gate electrodes and signal lines arranged at intervals from the gate electrodes.
  • According to the manufacturing method of the array substrate provided in an embodiment of the present disclosure, the photoresist layer is formed by a positive photoresist.
  • An embodiment of the present disclosure provides a manufacturing method of an array substrate, including following steps:
  • S10: providing a substrate, and sequentially laminating a first metal layer, an insulating layer, an amorphous silicon layer, an ohmic contact layer, a second metal layer, and a photoresist layer on the substrate, wherein the second metal layer includes a liner layer and a copper conductive layer sequentially laminated on the ohmic contact layer;
  • S20: using the photoresist layer as a shielding layer and performing a first wet etching treatment on the copper conductive layer to expose a part of the liner layer;
  • S30: using the photoresist layer as the shielding layer and performing a first dry etching treatment on the liner layer, the ohmic contact layer, and the amorphous silicon layer;
  • S40: performing an ashing treatment on the photoresist layer positioned in a first region to expose a part of the copper conductive layer, and performing a second wet etching treatment on the copper conductive layer to expose the liner layer positioned in the first region;
  • S50: using the photoresist layer as the shielding layer and performing a second dry etching treatment on the liner layer and the ohmic contact layer to form an active layer, a source electrode, a drain electrode, and a channel positioned between the source electrode and the drain electrode; and
  • S60: peeling off the photoresist layer.
  • According to the manufacturing method of the array substrate provided in an embodiment of the present disclosure, in the step S20 and the step S40, time periods for performing the first wet etching treatment and the second wet etching treatment on the copper conductive layer range between 50 seconds and 60 seconds respectively, and a material of the liner layer includes molybdenum.
  • According to the manufacturing method of the array substrate provided in an embodiment of the present disclosure, in the step S20 and the step S40, an etching solution used in the first wet etching treatment and the second wet etching treatment on the copper conductive layer is a hydrogen peroxide solution, and a material of the liner layer includes titanium or molybdenum titanium alloy.
  • According to the manufacturing method of the array substrate provided in an embodiment of the present disclosure, in the step S30, an etching gas used in the first dry etching treatment on the liner layer, the ohmic contact layer, and the amorphous silicon layer includes a gaseous mixture containing sulfur hexafluoride and chlorine.
  • According to the manufacturing method of the array substrate provided in an embodiment of the present disclosure, a mixing ratio of the sulfur hexafluoride and the chlorine is 1:10.
  • According to the manufacturing method of the array substrate provided in an embodiment of the present disclosure, an edge of the source electrode and an edge of the drain electrode are flush with an edge of the liner layer.
  • According to the manufacturing method of the array substrate provided in an embodiment of the present disclosure, the first metal layer includes gate electrodes and signal lines arranged at intervals from the gate electrodes.
  • According to the manufacturing method of the array substrate provided in an embodiment of the present disclosure, the photoresist layer is formed by a positive photoresist.
  • According to the manufacturing method of the array substrate provided in an embodiment of the present disclosure, a material of the first metal layer includes molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or a combination of above metals.
  • According to the manufacturing method of the array substrate provided in an embodiment of the present disclosure, a material of the insulating layer is one of silicon nitride, silicon oxide, and silicon oxynitride.
  • An embodiment of the present disclosure provides the array substrate, manufactured by the above manufacturing method of the array substrate, including:
  • the substrate;
  • the first metal layer disposed on the substrate;
  • the insulating layer disposed on the first metal layer;
  • the amorphous silicon layer disposed on the insulating layer;
  • the ohmic contact layer disposed on the amorphous silicon layer;
  • the liner layer disposed on the ohmic contact layer; and
  • the source electrode and the drain electrode disposed on the liner layer, wherein the channel is arranged between the source electrode and the drain electrode, materials of the source electrode and the drain electrode consist of the copper conductive layer, and an edge of the source electrode and an edge of the drain electrode are flush with an edge of the liner layer.
  • According to the array substrate provided in an embodiment of the present disclosure, a material of the liner layer is one of molybdenum, titanium, and molybdenum titanium alloy.
    • BENEFICIAL EFFECTS
  • Beneficial effects of the present disclosure are: in the array substrate and the manufacturing method of the array substrate provided in the present disclosure, during a traditional 4-mask process, when the first wet etching and the second wet etching are performed on the second metal layer, the wet etching is stopped after the copper conductive layer is merely etched completely. At this time, the liner layer is retained completely. Because a wet etching speed of the liner layer is slow, the etching time of the wet etching and the CD loss can be greatly reduced, and the CD loss is smaller. Meanwhile, etching steps to the liner layer are added in a conventional dry etching process, so an entire CD loss of the second metal layer can be reduced to reduce a CD loss of metals and improve the aperture ratio.
    • DESCRIPTION OF DRAWINGS
  • The accompanying drawings to be used in the description of embodiments of the present disclosure or prior art will be described in brief to more clearly illustrate the technical solutions of the embodiments or the prior art. The accompanying drawings described below are only part of the embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained from these drawings without creative work.
  • FIG. 1 is a flow chart of a manufacturing method of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 2A—FIG. 2G are schematic views during a process of the manufacturing method of the array substrate provided by an embodiment of the present disclosure.
  • FIG. 3 is a sectional schematic view of the array substrate provided by an embodiment of the present disclosure.
    •  DETAILED DESCRIPTION OF EMBODIMENTS
  • The following description of the various embodiments is provided to illustrate the specific embodiments. Directional terms described by the present disclosure, such as “top”, “bottom”, “front”, “back”, “left”, “right”, “inner”, “outer”, “side”, “vertical”, “level”, etc., are only directions by referring to the accompanying drawings, and thus the used terms are used only for the purpose of describing embodiments of the present disclosure and are not intended to be limiting of the present disclosure. In the drawings, units with similar structures are labeled with the same reference number.
  • In the description of the present disclosure, it should be understood that terms such as “center,” “longitudinal,” “lateral,” “length,” “width,” “thickness,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inside,” “outside,” “clockwise,” “counter-clockwise” as well as derivative thereof should be construed to refer to the orientation as then described or as shown in the drawings under discussion. These relative terms are for convenience of description, do not require that the present disclosure be constructed or operated in a particular orientation, and shall not be construed as causing limitations to the present disclosure. In addition, terms such as “first” and “second” are used herein for purposes of description and are not intended to indicate or imply relative importance or significance. Thus, features limited by “first”, “second”, and “third” are intended to indicate or imply including one or more than one these features. In the description of the present disclosure, “a plurality of” relates to two or more than two, unless otherwise specified.
  • In the description of the present disclosure, it should be noted that unless there are express rules and limitations, the terms such as “mount,” “connect,” and “bond” should be comprehended in broad sense. For example, it can mean a permanent connection, a detachable connection, or an integrated connection. It can mean a mechanical connection, an electrical connection, or can communicate with each other. It can mean a direct connection, an indirect connection by an intermediate, or an inner communication or an interaction between two elements. Those skilled in the art should understand the specific meanings in the present disclosure according to specific situations.
  • In the description of the present disclosure, unless specified or limited otherwise, it should be noted that, a structure in which a first feature is “on” or “beneath” a second feature may include an embodiment in which the first feature directly contacts the second feature and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature does not directly contact the second feature. Furthermore, a first feature “on,” “above,” or “on top of” a second feature may include an embodiment in which the first feature is right “on,” “above,” or “on top of” the second feature and may also include an embodiment in which the first feature is not right “on,” “above,” or “on top of” the second feature, or just means that the first feature has a sea level elevation greater than the sea level elevation of the second feature. While first feature “beneath,” “below,” or “on bottom of” a second feature may include an embodiment in which the first feature is right “beneath,” “below,” or “on bottom of” the second feature and may also include an embodiment in which the first feature is not right “beneath,” “below,” or “on bottom of” the second feature, or just means that the first feature has a sea level elevation less than the sea level elevation of the second feature.
  • The present disclosure herein provides many different embodiments or examples for realizing different structures of the present disclosure. In order to simplify the disclosure of the present disclosure, components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present disclosure. Furthermore, reference numbers and/or letters may be repeated in different examples of the present disclosure. Such repetitions are for simplification and clearness, which per se do not indicate the relations of the discussed embodiments and/or settings. Moreover, the present disclosure provides examples of various specific processes and materials, but the applicability of other processes and/or application of other materials may be appreciated by a person skilled in the art.
  • The present disclosure is directed towards the array substrate and the manufacturing method of the array substrate provided in the prior art. Since the etching speed of the liner layer under the conventional etching solution system is relatively slow, the CD loss of the copper conductive layer is too large, which in turn leads to a low aperture ratio. The embodiments of the present disclosure can solve this defect.
  • As shown in FIG. 1 , an embodiment of the present disclosure provides a manufacturing method of an array substrate, including following steps:
  • S10: providing a substrate 10, and sequentially laminating a first metal layer 20, an insulating layer 30, an amorphous silicon layer 40, an ohmic contact layer 50, a second metal layer 60, and a photoresist layer 70 on the substrate 10, wherein the second metal layer 60 includes a liner layer 601 and a copper conductive layer 602 sequentially laminated on the ohmic contact layer 50.
  • Specifically, as shown in FIG. 2A, the above film layers may be sequentially formed on the substrate 10 by deposition, sputtering, or coating. A raw material of the substrate 10 may be one of a glass substrate, a quartz substrate, and a resin substrate, etc. The first metal layer 20 is disposed on the substrate 10, and a material of the first metal layer 20 may be made of molybdenum, aluminum, aluminum nickel alloy, molybdenum tungsten alloy, chromium, or copper, or a combination of the above metals.
  • The first metal layer 20 is treated by means of a yellow light process to form gate electrodes and signal lines arranged at intervals from the gate electrodes. The signal lines include scanning lines providing scanning signals for thin film transistors. The insulating layer covers the first metal layer 20 and the substrate 10, and a material of the insulating layer 30 is one of silicon nitride, silicon oxide, and silicon oxynitride. The amorphous silicon layer 40 covers the insulating layer 30 to form an active layer. The ohmic contact layer 50 covers the amorphous silicon layer 40 to prevent the second metal layer 60 from directly contacting with the amorphous silicon layer 40.
  • The second metal layer 60 covers the ohmic contact layer 50, and the second metal layer 60 includes the liner layer 601 and the copper conductive layer 602 sequentially laminated on the ohmic contact layer 50. Wherein, the copper conductive layer 602 is used to form a source electrode 6021 and a drain electrode 6022 of the array substrate. Because copper particles in the copper conductive layer 602 are prone to diffuse into the ohmic contact layer 50 and the amorphous silicon layer 40 under the copper conductive layer 602, which affects conductive characteristics of the copper conductive layer 602, the liner layer 601 is arranged between the copper conductive layer 602 and the ohmic contact layer 50.
  • S20: using the photoresist layer 70 as a shielding layer and performing a first wet etching treatment on the copper conductive layer 602 to expose a part of the liner layer 601.
  • Specifically, as shown in FIG. 2B, because an etching speed of the copper conductive layer 602 is faster than an etching speed of the liner layer 601, in the embodiment of the present disclosure, a wet etching treatment is firstly performed on the copper conductive layer 602, and after the copper conductive layer 602 is completely etched, the liner layer 601 still remains intact due to its slow etching speed or no etching, thereby preventing a CD loss of the copper conductive layer 602 from being too large and leading to a low aperture ratio when the etching of the copper conductive layer 601 is completed.
  • Furthermore, a material of the liner layer 601 includes molybdenum, titanium, or molybdenum titanium alloy. Above-mentioned purposes can be achieved by selecting a matching etching solution or controlling an etching time according to the material of the liner layer 601.
  • For example, when the material of the liner layer 601 is molybdenum, the etching solution selected for the first wet etching treatment may be a copper acid etching solution. By controlling time periods for performing the first wet etching treatment and the second wet etching treatment on the copper conductive layer 602 range between 50 seconds and 60 seconds respectively, during the period, the copper conductive layer 602 has been etched completely, while the liner layer is hardly etched due to the slow etching speed. Compared with an etching time ranging between 120 seconds and 130 seconds for the first wet etching in the prior art, this method can reduce the etching time of the wet etching greatly.
  • As another example, when the material of the liner layer 601 is molybdenum titanium alloy, the etching solution selected for performing the first wet etching treatment and the second wet etching treatment on the copper conductive layer 602 may be a hydrogen peroxide solution. Because the titanium or the molybdenum titanium alloy hardly reacts with the hydrogen peroxide solution, when the copper conductive layer 602 is etched, the liner layer 601 is also not etched.
  • S30: using the photoresist layer 70 as the shielding layer and performing a first dry etching treatment on the liner layer 601, the ohmic contact layer 50, and the amorphous silicon layer 40.
  • As shown in FIG. 2C, after the copper conductive layer 602 in the step S20 is etched completely, the first dry etching treatment is performed on the liner layer 601. That is to say, in a conventional dry etching process, an additional step for etching the liner layer 601 added can reduce an entire CD loss of the second metal layer 60, so as to reduce the CD loss of the metals and improve the aperture ratio. At the same time, in the embodiment of the present disclosure, the liner layer 601, the ohmic contact layer 50, and the amorphous silicon layer 40 may be etched by a same dry etching treatment. And because above-mentioned processes are performed in a chamber of the same machine, no additional engineering sites are added, which improves production efficiency.
  • Furthermore, an etching gas used in the first dry etching treatment on the liner layer 601, the ohmic contact layer 50, and the amorphous silicon layer 40 includes a gaseous mixture containing sulfur hexafluoride and chlorine. Good etching effects may be obtained by using the gaseous mixture.
  • Preferably, in the gaseous mixture, a mixing ratio of the sulfur hexafluoride and the chlorine is 1:10.
  • S40: performing an ashing treatment on the photoresist layer positioned in a first region 100 to expose a part of the copper conductive layer 602, and performing a second wet etching treatment on the copper conductive layer 602 to expose the liner layer 601 positioned in the first region 100.
  • Specifically, as shown in FIG. 2D, the ashing treatment is performed on the photoresist layer 70 positioned in the first region 100 to reduce a thickness of the photoresist layer 70 in the first region 100 or remove the photoresist layer 70 in the first region 100 completely, so as to expose the copper conductive layer 602 in the first region 100 and to make preparations for subsequent second wet etching treatment on the copper conductive layer 602.
  • As shown in FIG. 2E, the copper conductive layer 602 positioned at the first region 100 is etched to form the source electrode 6021 and the drain electrode 6022. Wherein the photoresist layer 70 is formed by a positive photoresist. A gas used in the ashing treatment is oxygen.
  • It should be noted that, principles of the second wet etching treatment for the copper conductive layer 602 in the step S40 are the same as principles of the first wet etching treatment for the copper conductive layer 602 in the step S20. For details, please refer to above related descriptions of the step S20 in the embodiment of the present disclosure, which will not be repeated herein.
  • S50: using the photoresist layer 70 as the shielding layer and performing a second dry etching treatment on the liner layer 601 and the ohmic contact layer 6 to form an active layer, a source electrode 6021, a drain electrode 6022, and a channel positioned between the source electrode 6021 and the drain electrode 6022.
  • Specifically, as shown in FIG. 2F, in the first region 100, an edge of the source electrode 6021 and an edge of the drain electrode 6022 are flush with an edge of the liner layer 601 to guarantee the aperture ratio.
  • Similarly, principles of the second dry etching treatment for the liner layer 601 and the ohmic contact layer 50 in the step S50 are the same as principles of the first dry etching treatment for the liner layer 601, the ohmic contact layer 50, and the amorphous silicon layer 40 in the step S30. For details, please refer to above related descriptions of the step S30 in the embodiment of the present disclosure, which will not be repeated herein.
  • S60: peeling off the photoresist layer 70.
  • Specifically, as shown in FIG. 2G, the photoresist layer 70 is peeled off from the second metal layer 60, and then subsequent film layers are manufactured, such as pixel electrodes, etc. When the array substrate is a color filter on array (COA) substrate, a color resistance layer and a black matrix layer, etc. may further be manufactured.
  • As shown in FIG. 3 , an array substrate provided by an embodiment of the present disclosure is manufactured by the above manufacturing method. The array substrate includes a substrate 10, a first metal layer 20 disposed on the substrate 10, an insulating layer 30 disposed on the first metal layer 20, an amorphous silicon layer 40 disposed on the insulating layer 30, an ohmic contact layer 50 disposed on the amorphous silicon layer 40, a liner layer 601 disposed on the ohmic contact layer 50, and a source electrode 6021 and a drain electrode 6022 disposed on the liner layer 601.
  • Specifically, the first metal layer 20 includes gate electrodes and signal lines arranged at intervals from the gate electrodes. Material of the source electrode 6021 and the drain electrode 6022 consist of a copper conductive layer 602. A material of the liner layer 601 is one of molybdenum, titanium, and molybdenum titanium alloy. An edge of the source electrode 6021 and an edge of the drain electrode 6022 are flush with an edge of the liner layer 601, which can reduce the CD loss of the copper conductive layer 602 greatly and guarantee an aperture ratio.
  • The beneficial effects of the present disclosure are: in the array substrate and the manufacturing method of the array substrate provided in the present disclosure, during a traditional 4-mask process, when the first wet etching and the second wet etching are performed on the second metal layer, the wet etching is stopped after the copper conductive layer is merely etched completely. At this time, the liner layer is retained completely. Because a wet etching speed of the liner layer is slow, the etching time of the wet etching and the CD loss can be greatly reduced, and the CD loss is smaller. Meanwhile, etching steps to the liner layer are added in a conventional dry etching process, so an entire CD loss of the second metal layer can be reduced to reduce a CD loss of metals and improve the aperture ratio.
  • In summary, although the present disclosure has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those of ordinary skill in the art can make various changes and retouching without departing from the spirit and scope of the present disclosure. Therefore, a protection scope of the present disclosure is subject to a scope defined by the claims.

Claims (20)

What is claimed is:
1. A manufacturing method of an array substrate, comprising following steps:
S10: providing a substrate, and sequentially laminating a first metal layer, an insulating layer, an amorphous silicon layer, an ohmic contact layer, a second metal layer, and a photoresist layer on the substrate, wherein the second metal layer comprises a liner layer and a copper conductive layer sequentially laminated on the ohmic contact layer;
S20: using the photoresist layer as a shielding layer and performing a first wet etching treatment on the copper conductive layer to expose a part of the liner layer;
S30: using the photoresist layer as the shielding layer and performing a first dry etching treatment on the liner layer, the ohmic contact layer, and the amorphous silicon layer;
S40: performing an ashing treatment on the photoresist layer positioned in a first region to expose a part of the copper conductive layer, and performing a second wet etching treatment on the copper conductive layer to expose the liner layer positioned in the first region, wherein a gas used in the ashing treatment is oxygen;
S50: using the photoresist layer as the shielding layer and performing a second dry etching treatment on the liner layer and the ohmic contact layer to form an active layer, a source electrode, a drain electrode, and a channel positioned between the source electrode and the drain electrode; and
S60: peeling off the photoresist layer.
2. The manufacturing method of the array substrate in claim 1, wherein in the step S20 and the step S40, time periods for performing the first wet etching treatment and the second wet etching treatment on the copper conductive layer range between 50 seconds and 60 seconds respectively, and a material of the liner layer comprises molybdenum.
3. The manufacturing method of the array substrate in claim 1, wherein in the step S20 and the step S40, an etching solution used in the first wet etching treatment and the second wet etching treatment on the copper conductive layer is a hydrogen peroxide solution, and a material of the liner layer comprises titanium or molybdenum titanium alloy.
4. The manufacturing method of the array substrate in claim 1, wherein in the step S30, an etching gas used in the first dry etching treatment on the liner layer, the ohmic contact layer, and the amorphous silicon layer comprises a gaseous mixture containing sulfur hexafluoride and chlorine.
5. The manufacturing method of the array substrate in claim 4, wherein a mixing ratio of the sulfur hexafluoride and the chlorine is 1:10.
6. The manufacturing method of the array substrate in claim 1, wherein an edge of the source electrode and an edge of the drain electrode are flush with an edge of the liner layer.
7. The manufacturing method of the array substrate in claim 1, wherein the first metal layer comprises gate electrodes and signal lines arranged at intervals from the gate electrodes.
8. The manufacturing method of the array substrate in claim 1, wherein the photoresist layer is formed by a positive photoresist.
9. A manufacturing method of an array substrate, comprising following steps:
S10: providing a substrate, and sequentially laminating a first metal layer, an insulating layer, an amorphous silicon layer, an ohmic contact layer, a second metal layer, and a photoresist layer on the substrate, wherein the second metal layer comprises a liner layer and a copper conductive layer sequentially laminated on the ohmic contact layer;
S20: using the photoresist layer as a shielding layer and performing a first wet etching treatment on the copper conductive layer to expose a part of the liner layer;
S30: using the photoresist layer as the shielding layer and performing a first dry etching treatment on the liner layer, the ohmic contact layer, and the amorphous silicon layer;
S40: performing an ashing treatment on the photoresist layer positioned in a first region to expose a part of the copper conductive layer, and performing a second wet etching treatment on the copper conductive layer to expose the liner layer positioned in the first region;
S50: using the photoresist layer as the shielding layer and performing a second dry etching treatment on the liner layer and the ohmic contact layer to form an active layer, a source electrode, a drain electrode, and a channel positioned between the source electrode and the drain electrode; and
S60: peeling off the photoresist layer.
10. The manufacturing method of the array substrate in claim 9, wherein in the step S20 and the step S40, time periods for performing the first wet etching treatment and the second wet etching treatment on the copper conductive layer range between 50 seconds and 60 seconds respectively, and a material of the liner layer comprises molybdenum.
11. The manufacturing method of the array substrate in claim 9, wherein in the step S20 and the step S40, an etching solution used in the first wet etching treatment and the second wet etching treatment on the copper conductive layer is a hydrogen peroxide solution, and a material of the liner layer comprises titanium or molybdenum titanium alloy.
12. The manufacturing method of the array substrate in claim 9, wherein in the step S30, an etching gas used in the first dry etching treatment on the liner layer, the ohmic contact layer, and the amorphous silicon layer comprises a gaseous mixture containing sulfur hexafluoride and chlorine.
13. The manufacturing method of the array substrate in claim 12, wherein a mixing ratio of the sulfur hexafluoride and the chlorine is 1:10.
14. The manufacturing method of the array substrate in claim 9, wherein an edge of the source electrode and an edge of the drain electrode are flush with an edge of the liner layer.
15. The manufacturing method of the array substrate in claim 9, wherein the first metal layer comprises gate electrodes and signal lines arranged at intervals from the gate electrodes.
16. The manufacturing method of the array substrate in claim 9, wherein the photoresist layer is formed by a positive photoresist.
17. The manufacturing method of the array substrate in claim 9, wherein a material of the first metal layer comprises molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or a combination of above metals.
18. The manufacturing method of the array substrate in claim 9, wherein a material of the insulating layer is one of silicon nitride, silicon oxide, and silicon oxynitride.
19. The array substrate, manufactured by the manufacturing method of the array substrate in claim 9, comprising:
the substrate;
the first metal layer disposed on the substrate;
the insulating layer disposed on the first metal layer;
the amorphous silicon layer disposed on the insulating layer;
the ohmic contact layer disposed on the amorphous silicon layer;
the liner layer disposed on the ohmic contact layer; and
the source electrode and the drain electrode disposed on the liner layer, wherein the channel is arranged between the source electrode and the drain electrode, materials of the source electrode and the drain electrode consist of a copper conductive layer, and an edge of the source electrode and an edge of the drain electrode are flush with an edge of the liner layer.
20. The array substrate in claim 19, wherein a material of the liner layer is one of molybdenum, titanium, and molybdenum titanium alloy.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7229569B1 (en) * 1999-06-18 2007-06-12 Lg. Philips Lcd Co., Ltd. Etching reagent, and method for manufacturing electronic device substrate and electronic device
US20200135767A1 (en) * 2018-10-24 2020-04-30 HKC Corporation Limited Method for fabricating array substrate, array substrate and display

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7521366B2 (en) * 2001-12-12 2009-04-21 Lg Display Co., Ltd. Manufacturing method of electro line for liquid crystal display device
KR100866976B1 (en) * 2002-09-03 2008-11-05 엘지디스플레이 주식회사 Liquid Crystal Display and mathod for fabricating of the same
US20120009777A1 (en) * 2010-07-07 2012-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. UBM Etching Methods
CN103295970B (en) * 2013-06-05 2015-04-29 京东方科技集团股份有限公司 Array substrate and manufacturing method thereof and display device
CN105047723B (en) 2015-09-18 2017-12-19 京东方科技集团股份有限公司 A kind of thin film transistor (TFT), its preparation method, array base palte and display device
CN110112071B (en) * 2019-06-10 2022-02-08 北海惠科光电技术有限公司 Preparation method of thin film transistor, thin film transistor and display device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7229569B1 (en) * 1999-06-18 2007-06-12 Lg. Philips Lcd Co., Ltd. Etching reagent, and method for manufacturing electronic device substrate and electronic device
US20200135767A1 (en) * 2018-10-24 2020-04-30 HKC Corporation Limited Method for fabricating array substrate, array substrate and display
US10727256B2 (en) * 2018-10-24 2020-07-28 HKC Corporation Limited Method for fabricating array substrate, array substrate and display

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