JPH11233782A - Manufacture of tft array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing inversely staggered channel- etched thin film transistor array by which a channel section can be etched without increasing the number of processes, nor giving any plasma damage to the channel section in etching, nor allowing an etching gas to remain in the channel section. SOLUTION: In a method for manufacturing, a TFT array, a channel section 12 is formed by stripping a photoresist film 7 which is used at the time of forming source and drain electrodes 8 and 9 as a means for forming the channel section 12 with a liquid chemical prepared by diluting a stripping agent containing an amine component as a main component with pure water by using the electrodes 8 and 9 as a mask. Therefore, adverse influences of plasma damages and residual gases in the channel section 12 can be avoided without increasing the number of processes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for manufacturing a TFT array, and more particularly, to a method for manufacturing an inverted staggered channel etch type thin film transistor array.

[0002]

2. Description of the Related Art A conventional method for manufacturing a reverse staggered channel etch type thin film transistor array using undoped amorphous silicon will be described in the order of manufacturing steps with reference to FIGS. FIG. 3A is a plan view showing a main part of one pixel portion in a state where the liquid crystal display device is completed, and FIG. 3B is a sectional view taken along line AA of FIG. 3A. FIGS. 4 and 5 are cross-sectional views showing manufacturing steps from completion of the liquid crystal display device to the state shown in FIG.

First, as shown in FIG. 4A, a metal film such as tantalum, chromium, molybdenum, or tungsten is formed on a transparent insulating substrate 1 such as glass, and the gate electrode 2 is formed through a photolithography process. After forming scan lines (not shown), a gate insulating film 3 made of a silicon nitride film is formed by plasma enhanced chemical vapor deposition. After this,
Undoped amorphous silicon and n-type amorphous silicon are continuously formed, and an island-shaped undoped amorphous silicon layer 4 and an n-type amorphous silicon layer 5 that intersect with the gate electrode are formed through a photolithography process. . The gate insulating film 3 may be formed by laminating a silicon nitride film on a silicon oxide film formed in advance by sputtering, or the gate electrode 2 and the scanning line may be formed of an anodically oxidizable metal film such as tantalum or molybdenum. In some cases, these surfaces may be anodized to form an insulating film and used as a part of the gate insulating film 3. Thereafter, a contact hole (not shown) for taking a terminal in the gate insulating film 3 is opened through a photolithography process, and a metal film 6 made of, for example, chromium is formed to a thickness of about 140 nm by a sputtering method. I do.

[0004] Next, through a photolithography process, a portion serving as a source / drain electrode and a signal line is shown in FIG.
As shown in FIG. 1B, a photoresist film 7 is formed, and a fluorine-based gas or a mixed gas containing a fluorine-based gas, for example, a mixed gas of carbon tetrafluoride (CF4) and oxygen (O2) is used as a mask. The film 6 is dry-etched to form a source electrode 8 and a drain electrode 9. Next, after the photoresist 7 is peeled off, as shown in FIG. 5A, a transparent conductive film such as ITO (Indium Tin Oxide, hereinafter referred to as ITO) or the like is formed, and through a photolithography process. The pixel electrode 10 is formed. At the same time, the signal line 11 is formed while leaving the transparent conductive film as a signal line. Finally, using the source / drain electrodes as a mask, the n-type amorphous silicon layer 5 and the undoped amorphous silicon layer 4 in the channel portion are formed as shown in FIG. Carbon chloride (CCl4)
Using the etching gas as an etching gas, dry etching is performed until the undoped amorphous silicon layer 4 is removed from the surface by a depth of about 50 nm to form the channel portion 12. Thus, the channel-etch thin film transistor of FIG. 3B is obtained.

[0005]

As described above, in the step of digging the channel portion, after the display electrode is formed, the n-type amorphous silicon layer 5 and the undoped amorphous silicon layer 5 in the channel portion are formed using the source / drain electrodes as a mask. A dry etching method is used in which the layer 4 is etched with an etching gas such as sulfur hexafluoride (SF6) or carbon tetrachloride (CCl4), but this method may cause plasma damage to the channel portion 12 during etching. In addition, since ionized or radicalized etching gas remains on the surface of the channel portion 12, a leak current is generated when the transistor is operated. When displaying a gray screen (referred to as halftone display) in which the gate voltage is displayed near the intermediate value of the operating voltage range, this causes a problem of causing display unevenness on the screen.

The n-type amorphous silicon layer 5 in the channel portion
As an etching method of the undoped amorphous silicon layer 4, in addition to the above-described dry etching method, a mixed aqueous solution of hydrofluoric acid and nitric acid, a mixed solution of hydrofluoric acid / nitric acid and phosphoric acid,
Alternatively, there is a wet etching method using an organic alkali solution. However, a mixed aqueous solution of hydrofluoric acid and nitric acid, or a mixed solution of hydrofluoric acid / nitric acid and phosphoric acid is used not only for the channel portion but also for a gate insulating film, a source / drain electrode composed of a metal film, a pixel electrode composed of an ITO film, and a signal electrode. There is a drawback that the etching selectivity with respect to the line is low and not practical.

An object of the present invention is to provide a reverse staggered channel etch type thin film transistor array in which etching of a channel portion is performed without increasing the number of steps, and plasma damage to the channel portion at the time of etching and no etching gas remain in the channel portion. It is to provide a manufacturing method.

[0008]

According to a method of manufacturing a TFT array of the present invention, a step of forming a gate electrode for selectively covering the surface of an insulating substrate and depositing a gate insulating film over the entire surface; Depositing an undoped semiconductor layer on the film, depositing a doped semiconductor layer on the undoped semiconductor layer, removing an unnecessary portion of the doped semiconductor layer and the undoped semiconductor layer so that the island intersects the gate electrode. Forming a metal film over the entire surface of the insulating substrate including the island-shaped semiconductor layer; removing unnecessary portions of the metal film to form a pair of source / drain electrodes Forming a transparent conductive film on the entire surface of the insulating substrate including the pair of source / drain electrodes; and forming a pixel electrode by removing unnecessary portions of the transparent conductive film. Forming a channel portion in the undoped semiconductor layer by removing the entire doped semiconductor layer and a part of the undoped semiconductor layer using the pair of source / drain electrodes as a mask. Is performed by removing the unnecessary portion of the metal film and forming a pair of source / drain electrodes by removing the photoresist used in the steps after the step using a predetermined removing liquid, Further, the predetermined stripping solution is dimethyl sulfoxide 70
%, Monoethanolamine 30% mixed solution with pure water
It is characterized by being a chemical solution diluted to 11 or 12.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to FIG.
This will be described with reference to the drawings.

First, after a gate electrode 2 and scanning lines (not shown) are formed on a transparent insulating substrate 1 such as glass, a photoresist film 7 is formed, and the metal film 6 is dry-etched using this as a mask. The manufacturing process up to the formation of the source electrode 8 and the drain electrode 9 is the same as in FIG.

Next, the photoresist film 7 is stripped using a stripping solution containing an amine component as a main component. Then, simultaneously with the dissolution of the photoresist 7, the etching of the n-type amorphous silicon layer 5 exposed between the source and drain electrodes proceeds. FIG. 1 (a) shows a cross-sectional view of the thin film transistor during the progress. Further, as the dissolution of the photoresist film 7 and the etching of the n-type amorphous silicon layer 5 progress, the photoresist film 7 is completely peeled off, and the etching reaches the undoped amorphous silicon layer 4. Thereafter, after washing with pure water and drying, the channel portion 12 is formed simultaneously with the removal of the photoresist 7 on the source / drain electrodes as shown in FIG. 1 (b).

The process of forming the channel portion 12 using the above-mentioned stripping solution will be described in more detail.

After forming the source electrode 8 and the drain electrode 9 by etching the metal film 6 using the photoresist film 7 as a mask, the photoresist film 7 is removed. In this case, dimethyl sulfoxide 70%, monoethanol Dilute the mixed solution of amine 30% with pure water and adjust the pH
Using the chemical solution adjusted to 2, dipping or spraying is performed at a solution temperature of about 70 ° C. Then, since the etching rate of the amorphous silicon film becomes faster, etching is performed from the surface of the n-type amorphous silicon layer 5 exposed between the source electrode 8 and the drain electrode 9 as shown in FIG. Progresses. Even if the photoresist 7 is stripped, the etching of the n-type amorphous silicon layer 5 is continued using the source electrode 8 and the drain electrode 9 as a mask, and reaches the undoped amorphous silicon layer 4. Further etching is continued, and when the undoped amorphous silicon layer 4 is removed from the surface by a depth of about 50 nm, cleaning is performed with pure water or the like to terminate the etching, and as shown in FIG. 12 are formed.

As described above, since the channel portion can be formed by utilizing the peeling of the photoresist at the time of forming the source / drain electrodes, not only the conventional dry etching can be omitted, but also the damage of the plasma to the channel portion by the dry etching can be reduced. The etching gas can be prevented from remaining in the channel portion, and leakage during operation of the transistor can be prevented.

Next, a second embodiment of the present invention will be described.
This will be described with reference to FIG.

In the first embodiment of the present invention, the channel portion is dug by removing the photoresist after the formation of the source / drain electrodes. However, it can be performed after the formation of the pixel electrodes. That is, after forming the source / drain electrodes, an ITO film serving as a pixel electrode and a signal line is formed by an argon sputtering method, the photoresist film 13 is patterned and etched by a wet etching method, and then a photoresist as a protective film is formed. When the film 13 is peeled, a dipping process or a spraying process is performed using a chemical solution obtained by diluting a stripping solution containing an amine component as a main component with pure water in the same manner as in the first embodiment of the present invention. Then, as shown in FIG. 2 (a),
Photoresist film 13 on pixel electrode 10 and signal line 11
Is dissolved, and the n-type amorphous silicon layer 5 exposed between the source electrode 8 and the drain electrode 9 is etched using the source electrode 8 and the drain electrode 9 as a mask. Even if the photoresist on the pixel electrode 10 and the signal line 11 is stripped, the etching of the n-type amorphous silicon layer 5 continues using the source electrode 8 and the drain electrode 9 as a mask,
It reaches the undoped amorphous silicon layer 4. When the etching is further continued and the undoped amorphous silicon layer 4 is removed from the surface by a depth of about 50 nm, the etching is completed by performing cleaning with pure water or the like, and FIG. 2 (b)
The channel portion 12 is formed as shown in FIG.

As described above, similarly to the first embodiment, it is possible to obtain a transistor having stable characteristics without leakage during operation without performing dry etching that adversely affects the channel portion.

[0018]

As described above, according to the method of manufacturing a TFT array of the present invention, the photoresist used at the time of forming the source / drain electrodes is replaced with an amine in the usual process of producing an inverted staggered channel etch type thin film transistor array. The channel can be formed at the same time by stripping the stripping solution containing the component as the main component using a chemical solution diluted with pure water, so that plasma damage to the channel due to dry etching and adverse effects due to residual gas in the channel are reduced. Not
A great effect is obtained that the conventional etching step for forming the channel portion can be omitted.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an inverted staggered channel etch transistor according to a manufacturing method of a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of an inverted staggered channel etch transistor according to a manufacturing method of a second embodiment of the present invention.

FIG. 3 is a plan view of an inverted staggered channel etch transistor obtained by a conventional manufacturing method.

FIG. 4 is a cross-sectional view showing a method for manufacturing a conventional inverted staggered channel etch transistor in the order of steps.

FIG. 5 is a sectional view showing a step following FIG. 4;

[Explanation of symbols]

 Reference Signs List 1 insulating substrate 2 gate electrode 3 gate insulating film 4 undoped amorphous silicon layer 5 n-type amorphous silicon layer 6 metal film 7, 13 photoresist film 8 source electrode 9 drain electrode 10 pixel electrode 11 signal line 12 channel portion

Claims (6)

[Claims] A step of forming a gate electrode for selectively covering a surface of an insulating substrate and depositing a gate insulating film over the entire surface; a step of depositing an undoped semiconductor layer on the gate insulating film; Depositing a doped semiconductor layer on a semiconductor layer; removing unnecessary portions of the doped semiconductor layer and the undoped semiconductor layer to form an island-shaped semiconductor layer so as to intersect with the gate electrode; Forming a metal film over the entire surface of the insulating substrate including a semiconductor layer, removing unnecessary portions of the metal film to form a pair of source / drain electrodes, and including the pair of source / drain electrodes. A method of manufacturing a TFT array, comprising: a step of forming a transparent conductive film over the entire surface of an insulating substrate; and a step of forming a pixel electrode by removing unnecessary portions of the transparent conductive film. Forming a channel portion in the undoped semiconductor layer by removing the entire doped semiconductor layer and part of the undoped semiconductor layer using the pair of source / drain electrodes as a mask, removing unnecessary portions of the metal film; T is performed by stripping the photoresist used in the steps after the step of forming the pair of source / drain electrodes using a predetermined stripping solution.
A method for manufacturing an FT array. 2. The method according to claim 1, wherein the photoresist is used as a mask for forming the pair of source / drain electrodes in the step of removing unnecessary portions of the metal film to form the pair of source / drain electrodes. The manufacturing method of the TFT array described in the above. 3. The method of manufacturing a TFT array according to claim 1, wherein said photoresist is used as a mask for forming said pixel electrode in a step of forming a pixel electrode by removing an unnecessary portion of said transparent conductive film. . 4. The method for manufacturing a TFT array according to claim 1, wherein the predetermined stripping solution is a chemical solution obtained by diluting a mixed solution of dimethyl sulfoxide 70% and monoethanolamine 30% to pH 11 to 12 with pure water. 5. The method of manufacturing a TFT array according to claim 4, wherein the temperature of the chemical solution is in a range of 68 to 72 ° C. 6. The shape of the channel portion is such that the TFT array is immersed in the predetermined stripping solution to remove a part of the undoped semiconductor layer using the pair of source / drain electrodes as a mask. 5. The method for manufacturing a TFT array according to claim 4, wherein the method is obtained by taking out from the predetermined stripping solution and washing with pure water.