CN117457733A - 高电子迁移率晶体管及其制作方法 - Google Patents

高电子迁移率晶体管及其制作方法 Download PDF

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CN117457733A
CN117457733A CN202311395428.6A CN202311395428A CN117457733A CN 117457733 A CN117457733 A CN 117457733A CN 202311395428 A CN202311395428 A CN 202311395428A CN 117457733 A CN117457733 A CN 117457733A
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gallium nitride
drain
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gate
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黄信川
叶治东
张峻铭
陈柏荣
廖文荣
侯俊良
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United Microelectronics Corp
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United Microelectronics Corp
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Abstract

本发明公开一种高电子迁移率晶体管及其制作方法，其中该高电子迁移率晶体管包含一基底；一缓冲层，位于所述基底上；一氮化镓通道层，位于所述缓冲层上；一氮化铝镓层，位于所述氮化镓通道层上；一栅极凹陷，位于所述氮化铝镓层中；一源极区域和一漏极区域，位于所述栅极凹陷的相对两侧；一氮化镓源极层和一氮化镓漏极层分别成长于所述源极区域和所述漏极区域内的所述氮化铝镓层上；以及一P型氮化镓栅极层，位于所述栅极凹陷内和所述栅极凹陷上。

Description

高电子迁移率晶体管及其制作方法
本申请是中国发明专利申请(申请号：201911086103.3，申请日：2019年11月08日，发明名称：高电子迁移率晶体管及其制作方法)的分案申请。
技术领域
本发明涉及半导体技术领域，特别是涉及一种氮化镓(GaN)高电子迁移率晶体管(high-electron mobility transistor，HEMT)及其制作方法。
背景技术
氮化镓高电子迁移率晶体管常被应用于高频的高功率放大器元件，其具有高击穿电压、高饱和电子移动速度及高温操作的特性。
典型的HEMT中，在半导体异质结处产生二维电子气(2DEG)。2DEG代表了非常薄的导电层，该导电层具有高度可移动且高度集中的电荷载流子，该电荷载流子可在该导电层的两个维度上自由移动，但被垂直于该导电层的第三维度上的移动所限制。
目前该技术领域仍需要通过提供具有高耐压性或高阈值电压(Vt)和低导通阻值(Ron)的HEMT，来克服现有技术中的缺点和不足。
发明内容
本发明的主要目的在提供具有高耐压性或高阈值电压(Vt)和低导通阻值(Ron)的高电子迁移率晶体管，以克服现有技术中的缺点和不足。
本发明一方面提供了一种高电子迁移率晶体管，包含一基底；一缓冲层，位于所述基底上；一氮化镓通道层，位于所述缓冲层上；一氮化铝镓层，位于所述氮化镓通道层上；一栅极凹陷，位于所述氮化铝镓层中；一源极区域和一漏极区域，位于所述栅极凹陷的相对两侧；一氮化镓源极层和一氮化镓漏极层分别成长于所述源极区域和所述漏极区域内的所述氮化铝镓层上；以及一P型氮化镓栅极层，位于所述栅极凹陷内和所述栅极凹陷上。
根据本发明实施例，其中所述氮化镓源极层和所述氮化镓漏极层是由N++掺杂氮化镓所构成的。
根据本发明实施例，其中所述氮化镓源极层和所述氮化镓漏极层是由氮化铟镓所构成的。
根据本发明实施例，其中所述栅极凹陷贯穿所述氮化铝镓层。
根据本发明实施例，其中所述栅极凹陷未贯穿所述氮化铝镓层，又其中在所述栅极凹陷底部的所述氮化铝镓层的剩余厚度小于或等于2nm。
根据本发明实施例，所述高电子迁移率晶体管另包含：一重生长氮化铝镓膜，位于所述氮化铝镓层上、所述氮化镓源极层和所述氮化镓漏极层上，和所述栅极凹陷的内表面上。
根据本发明实施例，其中所述重生长氮化铝镓膜的厚度小于2nm。
根据本发明实施例，所述高电子迁移率晶体管另包含：一保护层，覆盖所述重生长氮化铝镓膜和所述P型氮化镓栅极层。
根据本发明实施例，所述高电子迁移率晶体管另包含：一栅极接触，贯穿所述保护层，并直接接触所述P型氮化镓栅极层。
根据本发明实施例，所述高电子迁移率晶体管另包含：一源极接触和一漏极接触，贯穿所述保护层，并分别直接接触所述氮化镓源极层和所述氮化镓漏极层。
本发明另一方面提供了一种形成高电子迁移率晶体管的方法，包含：提供一基底；在所述基底上形成一缓冲层；在所述缓冲层上形成一氮化镓通道层；在所述氮化镓通道层上形成一氮化铝镓层；分别于一源极区域和一漏极区域内的所述氮化铝镓层上形成一氮化镓源极层和一氮化镓漏极层；在所述源极区域和所述漏极区域之间的所述氮化铝镓层中形成一栅极凹陷；以及于所述栅极凹陷内和所述栅极凹陷上形成一P型氮化镓栅极层。
根据本发明实施例，其中所述氮化镓源极层和所述氮化镓漏极层是由N++掺杂氮化镓所构成的。
根据本发明实施例，其中所述氮化镓源极层和所述氮化镓漏极层是由氮化铟镓所构成的。
根据本发明实施例，其中所述栅极凹陷贯穿所述氮化铝镓层。
根据本发明实施例，其中所述栅极凹陷未贯穿所述氮化铝镓层，又其中在所述栅极凹陷底部的所述氮化铝镓层的剩余厚度小于或等于2nm。
根据本发明实施例，所述方法另包含：在所述氮化铝镓层上、所述氮化镓源极层和所述氮化镓漏极层上，和所述栅极凹陷的内表面上，形成一重生长氮化铝镓膜。
根据本发明实施例，其中所述重生长氮化铝镓膜的厚度小于2nm。
根据本发明实施例，所述方法另包含：形成一保护层，覆盖所述重生长氮化铝镓膜和所述P型氮化镓栅极层。
根据本发明实施例，所述方法另包含：形成一栅极接触，贯穿所述保护层，并直接接触所述P型氮化镓栅极层。
根据本发明实施例，所述方法另包含：形成一源极接触和一漏极接触，贯穿所述保护层，并分别直接接触所述氮化镓源极层和所述氮化镓漏极层。
附图说明
图1为本发明实施例所绘示的一种高电子迁移率晶体管的剖面示意图；
图2至图8为本发明实施例所绘示的一种高电子迁移率晶体管的制作方法的示意图。
主要元件符号说明
1高电子迁移率晶体管
100基底
102缓冲层
104氮化镓通道层
106氮化铝镓层
108重生长氮化铝镓膜
110栅极凹陷
112 P型氮化镓栅极层
112G P型氮化镓层
120氮化镓层
121氮化镓源极层
122氮化镓漏极层
130保护层
140介电层
200绝缘结构
S源极区域
D漏极区域
CG栅极接触
CS源极接触
CD漏极接触
2DEG二维电子云
具体实施方式
在下文中，将参照附图说明细节，该些附图中的内容也构成说明书细节描述的一部分，并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使该领域的一般技术人士得以具以实施。
当然，也可采行其他的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述不应被视为是限制，反之，其中所包含的实施例将由随附的权利要求来加以界定。
请参阅图1，其为依据本发明实施例所绘示的一种高电子迁移率晶体管的剖面示意图。如图1所示，高电子迁移率晶体管1包含一基底100、一缓冲层102，设于所述基底100上、一氮化镓通道层104，位于所述缓冲层102上、一氮化铝镓层106，位于所述氮化镓通道层104上；一栅极凹陷110，位于所述氮化铝镓层106中；一源极区域S和一漏极区域D，位于所述栅极凹陷110的相对两侧；一氮化镓源极层121和一氮化镓漏极层122分别成长于所述源极区域S和所述漏极区域D内的所述氮化铝镓层106上；以及一P型氮化镓栅极层112，位于所述栅极凹陷110内和所述栅极凹陷110上。
根据本发明实施例，所述高电子迁移率晶体管1可以另包含一重生长氮化铝镓膜108，位于所述氮化铝镓层106上、所述氮化镓源极层121和所述氮化镓漏极层122上，和所述栅极凹陷110的内表面上。
根据本发明实施例，所述高电子迁移率晶体管1可以另包含一保护层130，覆盖所述重生长氮化铝镓膜108和所述P型氮化镓栅极层112。例如，保护层130可以包含氮化硅或氧化铝等，但不限于此。此外，在保护层130上可以形成一介电层140，例如，氧化硅等，但不限于此。
根据本发明实施例，所述高电子迁移率晶体管1可以另包含一绝缘结构200，例如沟槽绝缘结构，环绕着由图案化的氮化镓通道层104和图案化的氮化铝镓层106构成的岛状主动(有源)区域。
根据本发明实施例，所述氮化镓源极层121和所述氮化镓漏极层122可以是由N++掺杂氮化镓所构成的。根据本发明另一实施例，其中所述氮化镓源极层121和所述氮化镓漏极层122可以是由氮化铟镓所构成的。
根据本发明实施例，所述栅极凹陷110贯穿所述氮化铝镓层106，显露出部分的氮化镓通道层104。根据本发明另一实施例，所述栅极凹陷110未贯穿所述氮化铝镓层106，此时，在所述栅极凹陷110底部的所述氮化铝镓层106的剩余厚度小于或等于2nm，在此厚度范围下，不会在所述氮化铝镓层106正下方处形成二维电子云(2DEG)。
根据本发明实施例，所述重生长氮化铝镓膜108的厚度小于2nm。
根据本发明实施例，所述高电子迁移率晶体管1另包含一栅极接触CG，贯穿所述保护层130，并直接接触所述P型氮化镓栅极层112。根据本发明实施例，所述高电子迁移率晶体管1另包含一源极接触CS和一漏极接触CD，贯穿所述保护层130，并分别直接接触所述氮化镓源极层121和所述氮化镓漏极层122。
本发明结构上的特征在于所述高电子迁移率晶体管1具有N++掺杂氮化镓或氮化铟镓所构成的氮化镓源极层121和氮化镓漏极层122，同时具有栅极凹陷110，而将P型氮化镓栅极层112设置于所述栅极凹陷110内和所述栅极凹陷110上。此外，所述高电子迁移率晶体管1具有重生长氮化铝镓膜108，位于所述氮化铝镓层106上、所述氮化镓源极层121和所述氮化镓漏极层122上，和所述栅极凹陷110的内表面上。结合以上特征，本发明高电子迁移率晶体管1得以实现高耐压性或高阈值电压(Vt)和低导通阻值(Ron)的HEMT，克服了现有技术中的缺点和不足。
请参阅图2至图8，其为依据本发明实施例所绘示的一种高电子迁移率晶体管的制作方法的示意图，图中仍以相同的标示符号来表示相同的元件、层、区域或材料。
如图2所示，首先提供基底100，例如，硅基底。接着，依序在基底100的表面上以外延方法形成缓冲层102、氮化镓通道层104、氮化铝镓层106和氮化镓层120，其中，依据本发明一实施例，所述氮化镓层120可以是N++掺杂氮化镓层。依据本发明一实施例，所述氮化镓层120可以是氮化铟镓层。在氮化镓通道层104中，靠近氮化铝镓层106处，会形成二维电子云(2DEG)。
接着，如图3所示，进行光学光刻和蚀刻制作工艺，将所述氮化镓层120图案化，分别于源极区域S和漏极区域D内的所述氮化铝镓层106上形成氮化镓源极层121和氮化镓漏极层122。如前所述，例如，所述氮化镓层120可以是N++掺杂氮化镓层，如此实现降低源极和漏极电阻的发明目的。此外，在in-situ生长N++掺杂氮化镓层的金属有机化学气相沉积(MOCVD)过程中，掺质浓度和活化热预算(activation thermal budget)可以被有效的控制。
如图4所示，进行另一次的光学光刻和蚀刻制作工艺，在所述源极区域S和所述漏极区域D之间的所述氮化铝镓层106中形成栅极凹陷110。根据本发明实施例，所述栅极凹陷110贯穿所述氮化铝镓层106，显露出部分的氮化镓通道层104。根据本发明另一实施例，所述栅极凹陷110未贯穿所述氮化铝镓层106，此时，在所述栅极凹陷110底部的所述氮化铝镓层106的剩余厚度小于或等于2nm，在此厚度范围下，不会在所述氮化铝镓层106正下方处形成二维电子云(2DEG)。
如图5所示，接着于所述氮化铝镓层106上、所述氮化镓源极层121和所述氮化镓漏极层122上，和所述栅极凹陷110的内表面上，形成重生长氮化铝镓膜108。根据本发明实施例，其中所述重生长氮化铝镓膜108的厚度小于2nm。所述重生长氮化铝镓膜108可以修补先前蚀刻步骤中造成的表面损害。然后，继续在重生长氮化铝镓膜108表面生长出P型氮化镓层112G。
如图6所示，接着进行另一次的光学光刻和蚀刻制作工艺，将P型氮化镓层112G图案化成P型氮化镓栅极层112。所述P型氮化镓栅极层112形成于所述栅极凹陷110内和所述栅极凹陷110上。
如图7所示，接着形成绝缘结构200，例如沟槽绝缘结构，环绕着由图案化的氮化镓通道层104和图案化的氮化铝镓层106构成的岛状主动区域。然后，形成保护层130，覆盖所述重生长氮化铝镓膜108和所述P型氮化镓栅极层112。例如，保护层130可以包含氮化硅或氧化铝等，但不限于此。
随后，如图8所示，在保护层130上形成介电层140，例如，氧化硅等，但不限于此。然后，形成栅极接触CG，贯穿所述保护层130，并直接接触所述P型氮化镓栅极层112，形成源极接触CS和漏极接触CD，贯穿所述保护层130，并分别直接接触所述氮化镓源极层121和所述氮化镓漏极层122。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (11)

1.一种高电子迁移率晶体管，其特征在于，包含：
基底；
氮化镓通道层，位于所述基底上；
氮化铝镓层，位于所述氮化镓通道层上；
栅极凹陷，位于所述氮化铝镓层中；
源极区域和漏极区域，位于所述栅极凹陷的相对两侧；
氮化镓源极层和氮化镓漏极层，分别成长于所述源极区域和所述漏极区域内的所述氮化铝镓层上；
P型氮化镓栅极层，位于所述栅极凹陷内和所述栅极凹陷上；以及
重生长氮化铝镓膜，位于所述氮化铝镓层上、所述氮化镓源极层和所述氮化镓漏极层上、和所述栅极凹陷的内表面上。
2.如权利要求1所述的高电子迁移率晶体管，其中所述氮化镓源极层和所述氮化镓漏极层是由N++掺杂氮化镓所构成的。
3.如权利要求1所述的高电子迁移率晶体管，其中所述氮化镓源极层和所述氮化镓漏极层是由氮化铟镓所构成的。
4.如权利要求1所述的高电子迁移率晶体管，其中所述栅极凹陷贯穿所述氮化铝镓层。
5.如权利要求1所述的高电子迁移率晶体管，其中所述栅极凹陷未贯穿所述氮化铝镓层，又其中在所述栅极凹陷底部的所述氮化铝镓层的厚度小于或等于2nm。
6.如权利要求1所述的高电子迁移率晶体管，其中另包含：
缓冲层，位于所述基底上，其中所述氮化镓通道层位于所述缓冲层上。
7.如权利要求1所述的高电子迁移率晶体管，其中所述重生长氮化铝镓膜的厚度小于2nm。
8.如权利要求7所述的高电子迁移率晶体管，另包含：
保护层，覆盖所述重生长氮化铝镓膜和所述P型氮化镓栅极层。
9.如权利要求8所述的高电子迁移率晶体管，其中所述保护层包含氮化硅或氧化硅。
10.如权利要求8所述的高电子迁移率晶体管，另包含：
栅极接触，贯穿所述保护层，并直接接触所述P型氮化镓栅极层。
11.如权利要求8所述的高电子迁移率晶体管，另包含：
源极接触和漏极接触，贯穿所述保护层，并分别直接接触所述氮化镓源极层和所述氮化镓漏极层。
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