CN117438373A - 一种去除dram杂质的方法 - Google Patents
一种去除dram杂质的方法 Download PDFInfo
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- CN117438373A CN117438373A CN202210819136.XA CN202210819136A CN117438373A CN 117438373 A CN117438373 A CN 117438373A CN 202210819136 A CN202210819136 A CN 202210819136A CN 117438373 A CN117438373 A CN 117438373A
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- dram
- polysilicon
- polysilicon contacts
- impurities
- etching
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000012535 impurity Substances 0.000 title claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000011065 in-situ storage Methods 0.000 claims description 8
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 238000004140 cleaning Methods 0.000 claims description 7
- 238000005108 dry cleaning Methods 0.000 claims description 5
- 238000001704 evaporation Methods 0.000 claims description 2
- 239000000356 contaminant Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000007747 plating Methods 0.000 abstract description 2
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 24
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 12
- 239000007789 gas Substances 0.000 description 10
- 238000007740 vapor deposition Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- UOACKFBJUYNSLK-XRKIENNPSA-N Estradiol Cypionate Chemical compound O([C@H]1CC[C@H]2[C@H]3[C@@H](C4=CC=C(O)C=C4CC3)CC[C@@]21C)C(=O)CCC1CCCC1 UOACKFBJUYNSLK-XRKIENNPSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000003723 Smelting Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011066 ex-situ storage Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
Abstract
本发明涉及DRAM制造技术领域，公开了一种去除DRAM杂质的方法，对DRAM的多晶硅触点蒸镀时，同时进行蚀刻。本发明解决了现有技术存在的触点电阻较大、容易对良率造成影响的问题。
Description
技术领域
本发明涉及DRAM制造技术领域，具体是一种去除DRAM杂质的方法。
背景技术
现有技术中，为了形成DRAM Cell Contact，在Cell通过Dry Etching(干法刻蚀)形成Contact Profile，去除自然氧化膜，而进行Wet Cleaning(湿法清洁)。追加进行DryCleaning(干法清洁)，进行自然氧化膜强化条件。以后对利用PH3的Doped Poly(掺杂多晶硅)进行Depo(蒸镀)，进行填充Contact的过程。
DRAM的Cell Contact和Active界面之间的电阻问题持续发生。
为了改善它，用Curing界面的方法大量灵活运用自然氧化膜控制等，但是仍然是数十KΩ的标准，引起电阻问题，对良率造成影响。
发明内容
为克服现有技术的不足，本发明提供了一种去除DRAM杂质的方法，解决现有技术存在的触点电阻较大、容易对良率造成影响的问题。
本发明解决上述问题所采用的技术方案是：
一种去除DRAM杂质的方法，对DRAM的多晶硅触点蒸镀时，同时进行蚀刻。
作为一种优选的技术方案，对DRAM的多晶硅触点蚀刻时，利用加热的HBr气体去除自然氧化物。
作为一种优选的技术方案，HBr气体的温度为450℃～550℃。
作为一种优选的技术方案，对DRAM的多晶硅触点蚀刻时，还可以加入NF3、HF气体。
作为一种优选的技术方案，采用SiH4及PH3对DRAM的多晶硅触点蒸镀。
作为一种优选的技术方案，采用湿法清洁或干法清洁对DRAM的多晶硅触点蒸镀。
作为一种优选的技术方案，对DRAM的多晶硅触点蚀刻时，还采用等离子体进行清洁。
作为一种优选的技术方案，利用加热的HBr气体去除自然氧化物时，在熔炉内进行原位反应(原位反应即In-situ，指：将本来需要分开在不同设备进行的两道工艺，使其在同一设备同道工艺里依次进行完成)。
本发明相比于现有技术，具有以下有益效果：
本发明通过界面Native oxide的去除，从Si surface(硅表面)的Epi(外延层)生成效果提升，触点电阻减少50％以上，良率改善2％～3％；而且清洁效果更佳；解决了现有技术存在的触点电阻较大、容易对良率造成影响的问题。
附图说明
图1为现有技术的工艺步骤示意图；
图2为本发明的工艺步骤示意图；
图3为自然氧化层位置示意图。
具体实施方式
下面结合实施例及附图，对本发明作进一步的详细说明，但本发明的实施方式不限于此。
实施例1
如图1至图3所示，本发明是在对多晶硅触点单元(Cell Contact Poly)进行Depo之前，将用Ex-situ进行Dry Cleaning的方式以在蒸镀设备内用In-situ进行的方式进行。
如图1所示，现有技术中形成Cell Contact的工序步骤如下：
进行干法蚀刻→Etch后Clean→多晶硅触点(Contact Poly)蒸镀前湿法清洁→多晶硅触点蒸镀。
如图2所示，经本发明的改良后，虽然工序步骤类似，但是在多晶硅触点蒸镀Process为了去除Native Oxide(自然氧化层)，将HBr气体(溴化氢气体)进行Pre Flow(预流)，in-situ(同时)进行蒸镀。
将HBr在450℃以上的高温下利用Heat通过Chemical反应去除Native Ox的方法，为了激活HBr Chemical反应而利用Plasma(等离子体)时，HBr的Clean效果增强。
用改良方法进行Process之后，改良点是通过界面(Active Si和Poly的界面)Native oxide的完美去除，从Si surface(硅表面)的Epi(外延层)生成效果提升和触点电阻减少50％以上，Cold Yield(良率)改善2％～3％。
对一般进行的湿法清洁或干法清洁进行蒸镀的工艺和用In-situ进行是核心，将HBr在450℃以上的高温下利用Heat去除Native Oxide(如图3所示)是重要的发明方案。
本发明在DRAM的多晶硅触点蒸镀时，用流动HBr气体，用同时去除Native oxide，连续进行PH3 Doped Poly的方法。
本发明中，HBr气体的处理温度包含450℃～550℃的范围。
本发明中，包含HBr气体之外的NF3、HF等和SiO2相互反应的气体。
本发明中，HBr的反应包含单纯利用Heat的方法和利用等离子体。
本发明中，进行HBr的设备包括在Furnace(熔炉)Type(即进行原位反应，在Furnace里进行In-situ process)和Single Type进行。
如上所述，可较好地实现本发明。
本说明书中所有实施例公开的所有特征，或隐含公开的所有方法或过程中的步骤，除了互相排斥的特征和/或步骤以外，均可以以任何方式组合和/或扩展、替换。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制，依据本发明的技术实质，在本发明的精神和原则之内，对以上实施例所作的任何简单的修改、等同替换与改进等，均仍属于本发明技术方案的保护范围之内。
Claims (8)
1.一种去除DRAM杂质的方法，其特征在于，对DRAM的多晶硅触点蒸镀时，同时进行蚀刻。
2.根据权利要求1所述的一种去除DRAM杂质的方法，其特征在于，对DRAM的多晶硅触点蚀刻时，利用加热的HBr气体去除自然氧化物。
3.根据权利要求2所述的一种去除DRAM杂质的方法，其特征在于，HBr气体的温度为450℃～550℃。
4.根据权利要求3所述的一种去除DRAM杂质的方法，其特征在于，对DRAM的多晶硅触点蚀刻时，还可以加入NF3、HF气体。
5.根据权利要求4所述的一种去除DRAM杂质的方法，其特征在于，采用SiH4及PH3对DRAM的多晶硅触点蒸镀。
6.根据权利要求5所述的一种去除DRAM杂质的方法，其特征在于，采用湿法清洁或干法清洁对DRAM的多晶硅触点蒸镀。
7.根据权利要求1至6任一项所述的一种去除DRAM杂质的方法，其特征在于，对DRAM的多晶硅触点蚀刻时，还采用等离子体进行清洁。
8.根据权利要求7所述的一种去除DRAM杂质的方法，其特征在于，利用加热的HBr气体去除自然氧化物时，在熔炉内进行原位反应。
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