CN117410325A - Planar silicon carbide IGBT device, manufacturing method thereof and electronic equipment - Google Patents

Planar silicon carbide IGBT device, manufacturing method thereof and electronic equipment Download PDF

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Publication number
CN117410325A
CN117410325A CN202311267422.0A CN202311267422A CN117410325A CN 117410325 A CN117410325 A CN 117410325A CN 202311267422 A CN202311267422 A CN 202311267422A CN 117410325 A CN117410325 A CN 117410325A
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China
Prior art keywords
layer
silicon carbide
igbt device
semiconductor structure
buffer layer
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CN202311267422.0A
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Chinese (zh)
Inventor
王二俊
田晓丽
刘新宇
王鑫华
白云
杨成樾
汤益丹
郝继龙
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN202311267422.0A priority Critical patent/CN117410325A/en
Publication of CN117410325A publication Critical patent/CN117410325A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices

Abstract

The invention discloses a planar silicon carbide IGBT device, a manufacturing method thereof and electronic equipment, and relates to the technical field of semiconductors, so that the turn-off time and turn-off power consumption of the device are reduced, and the turn-off speed of the device is improved. The planar silicon carbide IGBT device comprises: and the first semiconductor structure and the second semiconductor structure are bonded together from top to bottom. The first semiconductor structure includes a drift layer, a current spreading layer formed over the drift layer, and a front side transistor cell. The second semiconductor structure comprises an ohmic contact layer, a current collecting layer and a buffer layer which are sequentially formed on the ohmic contact layer, a groove is etched on one side, facing the drift layer, of the buffer layer, and a polycrystalline silicon layer is deposited in the groove. The material of the buffer layer comprises silicon carbide, and the polycrystalline silicon layer and the buffer layer form a heterojunction structure. The manufacturing method of the planar silicon carbide IGBT device is used for manufacturing the planar silicon carbide IGBT device.

Description

Planar silicon carbide IGBT device, manufacturing method thereof and electronic equipment
Technical Field
The invention relates to the technical field of semiconductors, in particular to a planar silicon carbide IGBT device, a manufacturing method thereof and electronic equipment.
Background
The third generation wide bandgap semiconductor silicon carbide (SiC) has the characteristics of larger band gap, higher critical breakdown field strength, higher thermal conductivity, higher electron saturation speed and the like, and has wide research value and application value in power electronic devices. Silicon carbide insulated gate bipolar transistor (SiC IGBT) fuses the advantages of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and bipolar transistor (Bipolar Junction Transistor, BJT), has the advantages of working under high frequency, high voltage and heavy current, and is widely applied to the strong electric control fields of ship drive, rail transit, smart grid, alternating current frequency conversion, aerospace, wind power generation, new energy, motor transmission, automobiles and the like.
In practical application, the IGBT has two basic structures, i.e., a planar gate structure and a trench gate structure, respectively. And because the silicon carbide material has high hardness and high corrosion resistance, a groove structure with a smooth interface is difficult to form in the process, so that the main structure of the IGBT based on SiC is a planar gate structure. For a SiC IGBT device, the introduced conduction modulation effect greatly reduces the on-resistance and the on-loss, but excessive carriers exist in the device, and when the SiC IGBT device is turned off, a great deal of time is required to wait for the excessive carriers to be compounded, so that a depletion region is formed, and finally the device is turned off, so that the turn-off time and the turn-off loss of the device are greatly improved.
Based on this, how to reduce the turn-off time and turn-off power consumption of the planar silicon carbide IGBT becomes a problem to be solved.
Disclosure of Invention
The invention aims to provide a planar silicon carbide IGBT device, a manufacturing method thereof and electronic equipment, so as to reduce the turn-off time and turn-off power consumption of the device and improve the turn-off speed of the device.
In a first aspect, the present invention provides a planar silicon carbide IGBT device comprising a first semiconductor structure and a second semiconductor structure bonded together from top to bottom. The first semiconductor structure includes a drift layer, a current spreading layer formed over the drift layer, and a front side transistor cell. The second semiconductor structure comprises an ohmic contact layer, a current collecting layer and a buffer layer which are sequentially formed on the ohmic contact layer, a groove is etched on one side, facing the drift layer, of the buffer layer, and a polycrystalline silicon layer is deposited in the groove. The material of the buffer layer comprises silicon carbide, and the polycrystalline silicon layer and the buffer layer form a heterojunction structure.
Compared with the prior art, in the planar silicon carbide IGBT device provided by the invention, the first semiconductor structure and the second semiconductor structure are directly bonded to form, the buffer layer of the second semiconductor structure is etched with the groove, the material of the buffer layer comprises silicon carbide (SiC), the groove is filled with the polycrystalline silicon layer formed by the polycrystalline silicon (Si) material, and the heterojunction of SiC/Si can be formed at the buffer layer area, because the forbidden band width of silicon is far smaller than that of silicon carbide, the potential well of electrons and holes can be formed at the interface of the first semiconductor structure and the second semiconductor structure, and when the device is turned off, the heterojunction can store a large amount of surplus carriers, meanwhile, the smaller forbidden band width can enable the recombination speed of the carriers to be faster, the reduction speed of the surplus carriers in the device can be further accelerated, and the depletion area can be promoted to be formed rapidly, so that the turn-off time and turn-off loss of the IGBT device are reduced.
Therefore, the planar silicon carbide IGBT device provided by the invention can obviously reduce the turn-off time and turn-off loss of the IGBT device, does not influence the breakdown voltage and the gate oxide electric field intensity of the IGBT device, is matched with the traditional device in the device preparation process, and better realizes the compromise between the forward turn-on voltage drop and the turn-off loss of the device.
In a second aspect, the present invention further provides a method for manufacturing a planar silicon carbide IGBT device, where the method is used for manufacturing the planar silicon carbide IGBT device according to the first aspect, and the method for manufacturing the planar silicon carbide IGBT device includes:
providing a first semiconductor structure; wherein the first semiconductor structure includes a drift layer, a current spreading layer and a front side transistor cell formed in sequence over the drift layer.
Providing a second semiconductor substructure; the second semiconductor substructure comprises a current collecting layer and a buffer layer, a groove is etched on one side of the buffer layer, facing the drift layer, and a polysilicon layer is deposited in the groove. The material of the buffer layer comprises silicon carbide, and the polycrystalline silicon layer and the buffer layer form a heterojunction structure.
And bonding the first semiconductor structure and the second semiconductor substructure through the drift layer and the buffer layer.
And forming an ohmic contact layer on one side of the current collection layer, which is away from the buffer layer, so as to obtain a second semiconductor structure, thereby forming the IGBT device.
The beneficial effects of the method for manufacturing a planar silicon carbide IGBT device according to the second aspect of the present invention are the same as those of the planar silicon carbide IGBT device according to the above-described first aspect, and will not be described here again.
In a third aspect, the present invention further provides an electronic device, including the planar silicon carbide IGBT device according to the first aspect.
The beneficial effects of the electronic device provided in the third aspect of the present invention are the same as those of the planar silicon carbide IGBT device described in the foregoing first aspect, and are not repeated here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
fig. 1 is a schematic cross-sectional structure of a planar silicon carbide IGBT device according to an embodiment of the invention;
fig. 2 is a comparison graph of turn-off curves of an IGBT device provided by the embodiment of the invention and an existing IGBT device under the same bias condition;
FIG. 3 is a graph showing the comparison of turn-off curves of an IGBT device according to an embodiment of the present invention and an existing IGBT device under different turn-on voltage drops
FIG. 4 is a flow chart of a method for manufacturing a planar silicon carbide IGBT device in an embodiment of the invention;
fig. 5 to 21 are schematic cross-sectional structures corresponding to steps of fabricating a planar silicon carbide IGBT device according to an embodiment of the invention.
Reference numerals:
1-a first semiconductor structure, 11-a drift layer,
12-current spreading layer, 13-front side transistor cells,
10-first substrate, 131-P-well region,
132-active region, 133-gate structure,
1321-N + source region 1322-P + The source region is formed by a first region,
1331-gate oxide, 1332-gate polysilicon,
1333-gate mask layer, 1334-first metal layer,
1335-second metal layer, 2-second semiconductor structure,
21-ohmic contact layer, 22-collector layer,
23-buffer layer, 24-polysilicon layer,
20-second substrate 25-mask layer.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned. In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. The meaning of "a number" is one or more than one unless specifically defined otherwise.
The SiC IGBT combines the advantages of the MOSFET and the BJT, and controls the switching of the BJT through the MOS tube, so that the input impedance of the IGBT device is large. When turned off, the thyristor structure has a higher breakdown voltage. When the IGBT is conducted, the internal PIN structure introduces a conductivity modulation effect, forward conduction voltage drop is reduced, and overall power consumption is smaller, so that the whole IGBT device has the advantage of working under high frequency, high voltage and high current, and is widely applied to the strong electric control fields of ship driving, rail transit, smart power grids, alternating current frequency conversion, aerospace, wind power generation, new energy, motor transmission, automobiles and the like.
Because of early process defects, the P-type silicon carbide substrate is difficult to form, research groups are mainly focused on research and preparation of the P-type IGBT, but electron mobility in the silicon carbide is far greater than that of holes, so in recent years, along with progress of process development, attention is focused on the N-type IGBT. In the early stage, the main concern is between the blocking characteristic and the conduction voltage drop of the device until the U.S. CREE company produces an N-type IGBT with the breakdown voltage reaching 27kV, the breakdown characteristic has reached the expectation, the center of gravity of the whole device design shifts to the trade-off of the reliability and the device performance, and the dynamic characteristic of the device is more and more important in the SiC IGBT.
The IGBT has two basic structures, a planar gate structure and a trench gate structure, respectively. Although the trench gate IGBT eliminates a Junction Field-Effect Transistor (JFET) region, reduces resistance, improves channel density, and greatly improves on characteristics, the silicon carbide material itself is hard and corrosion resistant, and it is difficult to form a trench structure with a smooth interface in the process, so in practical application, the SiC IGBT has a planar gate structure as a main structure. For a SiC IGBT device, the introduced conduction modulation effect greatly reduces the on-resistance and the on-loss, but excessive carriers exist in the device, when the SiC IGBT device is turned off, a great deal of time is required to wait for the excessive carriers to be compounded to form a depletion region, and finally the device is turned off, so that the turn-off time and the turn-off loss of the device are greatly improved.
In order to solve the above technical problem, as shown in fig. 1, an embodiment of the present invention provides a planar silicon carbide IGBT device, which includes a first semiconductor structure 1 and a second semiconductor structure 2 bonded together from top to bottom. The first semiconductor structure 1 includes a drift layer 11, a current spreading layer 12 formed over the drift layer 11, and a front side transistor cell 13. The second semiconductor structure 2 includes an ohmic contact layer 21, a collector layer 22 and a buffer layer 23 sequentially formed on the ohmic contact layer 21, the buffer layer 23 having a trench etched toward the drift layer 11, and a polysilicon layer 24 deposited in the trench. The material of the buffer layer 23 includes silicon carbide, and the polysilicon layer 24 and the buffer layer 23 form a heterojunction structure.
As can be seen from the specific structure of the planar silicon carbide IGBT device, the first semiconductor structure 1 and the second semiconductor structure 2 are directly bonded, and a trench is etched in the buffer layer 23 of the second semiconductor structure 2, the material of the buffer layer 23 includes silicon carbide (SiC), the polysilicon layer 24 formed by polysilicon (Si) material is filled in the trench, and a SiC/Si heterojunction can be formed at the buffer layer 23 region, because the forbidden band width of silicon is far smaller than the forbidden band width of silicon carbide, so that a potential well of electrons and holes can be formed at the interface of the first semiconductor structure 1 and the second semiconductor structure 2, when the device is turned off, the heterojunction can store a large amount of excess carriers, and meanwhile, the smaller forbidden band width can enable the recombination speed of carriers to be faster, further speed up the reduction speed of the excess carriers in the device, and promote the rapid formation of a depletion region, thereby reducing the turn-off time and turn-off loss of the IGBT device.
In one possible implementation, the dimension of the polysilicon layer 24 along the stacking direction of the second semiconductor structure 2 ranges from 0.5 μm to 2 μm. By way of example, the stacking direction of the second semiconductor structure 2 may be regarded as a thickness direction, and the thickness of the polysilicon layer 24 may be 0.5 μm, 0.9 μm, 1.3 μm, 1.7 μm, or 2 μm, which is not particularly limited in the embodiment of the present invention.
In one possible implementation, the dimension of the polysilicon layer 24 ranges from 0.5 μm to 2 μm in a direction perpendicular to the stacking direction of the second semiconductor structure 2. By way of example, the direction perpendicular to the stacking direction of the second semiconductor structure 2 may be regarded as a width direction, and the polysilicon layer 24 may also have a width of 0.5 μm, 0.9 μm, 1.3 μm, 1.7 μm or 2 μm, which is not particularly limited in the embodiment of the present invention.
To further illustrate the advantages of the planar silicon carbide IGBT provided by embodiments of the invention over existing planar gate SiC IGBT structures, fig. 2 and 3 illustrate turn-off curves under the same electrode bias conditions using simulation software. Wherein the width and thickness of the polysilicon are respectively 0.5 μm and 0.5 μm.
In FIG. 2, the left vertical axis represents the gate current I CE The unit is ampere (A), the right vertical axis represents the gate voltage V CE The horizontal axis represents Time, and the units are microseconds (μs). As can be seen from fig. 2, the gate voltages of the two structures drop at the same time point, which means that the turn-off of the two structures starts at the same time, the current of the IGBT device provided by the application drops to 0 more quickly, the time is 232 nanoseconds (ns), and 325 nanoseconds (ns) are required for turning off the existing IGBT device, so that the IGBT device provided by the application can turn off more quickly, and similarly, the turn-off loss is further reduced. FIG. 3 shows the turn-off loss curves for two devices with different turn-on voltage drops, in FIG. 3 the vertical axis represents the turn-off loss E off The unit is megajoules (mJ), and the horizontal axis represents the conduction voltage drop V F As can be seen from fig. 3, the IGBT device provided in the present application has better turn-on characteristics, and therefore, the present application can realize a compromise performance of turn-on characteristics and turn-off loss.
Therefore, the planar silicon carbide IGBT device provided by the embodiment of the invention can obviously reduce the turn-off time and turn-off loss of the IGBT device, does not influence the breakdown voltage and the electric field strength of the gate oxide of the IGBT device, is matched with the traditional device in the device preparation process, and better realizes the compromise between the forward turn-on voltage drop and the turn-off loss of the device.
In one possible implementation, the front side transistor unit 13 includes: p-well region 131; the P-well region 131 is formed by performing ion implantation on the current spreading layer 12. An active region 132 formed in the P-well region 131. A gate structure 133 is formed over the active region 132.
As shown in fig. 1, the front-side transistor unit 13 is formed over the current spreading layer 12, and the current spreading layer 12 can promote spreading of the current so that the current spreads as uniformly as possible over the entire IGBT device. The P-well region 131 is formed at a side of the current spreading layer 12 far from the drift layer 11, after Al ion implantation is performed on the current spreading layer 12, the P-well region 131 is formed, al ions and N ions are implanted at an upper surface of the P-well region 131 to form an n+ source region 1321 and a p+ source region 1322, respectively, and a gate structure 133 is formed above the n+ source region 1321 and the p+ source region 1322, and finally, a front transistor unit 13 is formed, so that the IGBT device can receive a control voltage through the front transistor unit 13, thereby driving the IGBT device to be turned on or off.
As shown in fig. 4, the embodiment of the present invention further provides a method for manufacturing a planar silicon carbide IGBT device, where the method for manufacturing a planar silicon carbide IGBT device is used for manufacturing the planar silicon carbide IGBT device, and the method for manufacturing the planar silicon carbide IGBT device includes:
s100: providing a first semiconductor structure 1; wherein the first semiconductor structure 1 comprises a drift layer 11, a current spreading layer 12 and a front side transistor cell 13 formed in sequence above the drift layer 11.
Referring to fig. 5 to 12, in one possible implementation, S100: providing a first semiconductor structure 1, comprising the steps of:
s101: a first substrate 10 is provided.
It will be appreciated that the specific structure of the substrate may be set according to the actual application scenario, and is not specifically limited herein. Specifically, the base may be a silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, a germanium silicon substrate, a germanium substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or the like, on which any result is not formed, or may be a base on which some structure is formed.
The first substrate 10 may be, for example, doped at a concentration of 5×10 16 ～1×10 17 cm -3 Horizontal N-type 4H-SiC substrate.
S102: a drift layer 11 is epitaxially grown on the first substrate 10.
For example, the doping concentration may be 5×10 16 ～1×10 17 cm -3 The C-plane of the horizontal N-type 4H-SiC substrate (i.e., the upper surface of the first base 10) is epitaxially grown with chemical vapor deposition (Chemical Vapor Deposition, CVD) to form a drift layer 11, and the doping concentration of the drift layer 11 may be 4×10 14 cm -3 The thickness of the drift layer 11 may be 110 μm.
S103: an ion implantation process is performed on the side of the drift layer 11 facing away from the first substrate 10 to form a current spreading layer 12.
Illustratively, the N-type current spreading layer 12 is formed by implanting N ions at the side of the drift layer 11 facing away from the first substrate 10, i.e. the front surface of the epitaxial layer of the drift layer 11, and the doping concentration of the N-type current spreading layer 12 may be 8×10 15 cm -3 The thickness of the N-type current spreading layer 12 may be 2 μm.
S104: a front-side transistor cell 13 is formed on the current spreading layer 12.
Specifically, forming the front-side transistor cell 13 on the current spreading layer 12 includes the substeps of:
substep A1: ion implantation is performed on the side of the current spreading layer 12 facing away from the drift layer 11 to form a P-well region 131.
Specifically, the P-well region 131 is prepared on the upper surface of the current spreading layer 12 by multiple ion implantations, for example, multiple boron ion implantations to form P-well regions 131 of different depths, or multiple Al ion implantations to form P-well regions 131 of different depths.
Substep A2: an ion implantation process is performed on the side of the P-well region 131 away from the drift layer 11 to form an active region 132.
Specifically, as shown in fig. 5, the active region 132 includes an n+ source region 1321 and a p+ source region 1322 formed on the P well region 131, the p+ source region 1322 and the n+ source region 1321 are prepared on the P well region 131 by ion implantation, for example, the p+ source region 1322 is formed by implanting Al ions, and the n+ source region 1321 is formed by implanting N ions.
Substep A3: a gate structure 133 is formed over the active region 132.
As shown in fig. 6, a gate oxide layer 1331 is formed on the active region 132 by thermal oxidation, and the gate oxide layer 1331 may cover the entire current spreading layer 12 to protect the current spreading layer 12 from being etched during a subsequent etching process. The thickness of the gate oxide layer 1331 may be 50nm to 60nm, and exemplary thicknesses of the gate oxide layer 1331 may be 50nm,51nm,53nm,55nm,57nm, or 60nm, which is not particularly limited in the embodiment of the present invention.
As shown in fig. 7, a gate polysilicon layer 1332 is deposited over the gate oxide layer 1331.
As shown in fig. 8, a gate mask layer 1333 is formed over the gate polysilicon layer 1332, and the gate mask layer 1333 and the gate oxide layer 1331 may be silicon dioxide thin film layers, which are not particularly limited in the embodiment of the present invention.
As shown in fig. 9, after the gate polysilicon layer 1332 and the gate oxide layer 1331 are etched by using the gate mask layer 1333, passivation treatment is further required to be performed on the gate polysilicon layer 1332 and the gate oxide layer 1331 to form a passivation layer, so that stability of the front transistor unit 13 is further improved, and then the gate structure 133 is formed. It should be appreciated that the etched channel should expose at least the n+ source region 1321 and the p+ source region 1322 to facilitate depositing metal on the active region 132 to form a front ohmic contact.
As shown in fig. 10, a first metal layer 1334 is deposited over the n+ source regions 1321 and the p+ source regions 1322, and the material of the first metal layer 1334 may be, for example, metallic nickel.
As shown in fig. 11, a second metal layer 1335 is deposited over the first metal layer 1334 and subjected to a high temperature annealing process after metal stripping at the corresponding locations to form front ohmic contacts. The material of the second metal layer 1335 may be, for example, metal titanium, metal aluminum, or an alloy of metal titanium and metal aluminum, which is not particularly limited in the embodiment of the present invention.
S105: the first substrate 10 is removed.
As shown in fig. 12, N under the drift layer 11 is polished off by chemical mechanical polishing (Chemical Mechanical Polishing, CMP) + SiC substrate structure, thereby completing the preparation of the first semiconductor structure 1.
S200: providing a second semiconductor substructure; the second semiconductor substructure includes a collector layer 22 and a buffer layer 23, where a trench is etched in a side of the buffer layer 23 facing the drift layer 11, and a polysilicon layer 24 is deposited in the trench. The material of the buffer layer 23 includes silicon carbide, and the polysilicon layer 24 and the buffer layer 23 form a heterojunction structure.
Referring to fig. 13 to 21, S200: providing a second semiconductor substructure, comprising the steps of:
s201: a second substrate 20 is provided.
It should be understood that the second substrate 20 may be the same substrate structure as the first substrate 10, or may be different substrate structures according to practical situations, which is not limited in particular in the embodiment of the present invention. In particular, the second substrate 20 may be doped at a concentration of 5×10 16 ～1×10 17 cm -3 Horizontal N-type 4H-SiC substrate.
S202: a collector layer 22 is epitaxially grown on the second substrate 20.
For example, the doping concentration may be 5×10 16 ～1×10 17 cm -3 The C-side of the horizontal N-type 4H-SiC substrate (i.e., the upper surface of the second base 20) is epitaxially grown by CVD to form a collector layer 22, which collector layer 22 may be a P-type heavily doped silicon carbide material layer (P + -SiC), the doping concentration may be 1 x 10 19 cm -3 The thickness may be 5 μm.
S203: a buffer layer 23 is epitaxially grown on the collector layer 22.
Exemplary, as shown in FIG. 13, the dopant concentration may be 1X 10 19 cm -3 Epitaxially grow a layer of 1.5X10 doping concentration on the P-type heavily doped collector layer 22 17 cm -3 Buffer layer 23 having a thickness of 2.5um, buffer layer 23 may be an N-type silicon carbide material layer (N-SiC).
S204: the buffer layer 23 is etched away from the collector layer 22 using a mask to form a trench.
As shown in fig. 14, a mask layer 25 is deposited on the side of the buffer layer 23 facing away from the collector layer 22, and the mask layer 25 may be made of silicon dioxide.
As shown in fig. 15, a trench is formed by performing an etching process on a portion where polysilicon is to be deposited using silicon dioxide as a mask layer 25.
S205: a polysilicon layer 24 is deposited within the trench.
As shown in fig. 16, a polysilicon layer 24 is deposited in the trench to form a backside SiC/Si heterojunction structure. By way of example, the thickness and width of the polysilicon layer 24 may be 0.5 μm.
As shown in fig. 17, the excess mask layer 25 and polysilicon layer 24 are polished away.
S300: the first semiconductor structure 1 and the second semiconductor substructure are subjected to a bonding process via the drift layer 11 and the buffer layer 23.
As shown in fig. 18 and 19, the drift layer 11 and the buffer layer 23 are directly bonded at a low temperature, so that the first semiconductor structure 1 and the second semiconductor substructure form a unitary structure.
As shown in fig. 20, the second substrate 20 also needs to be removed after the bonding process is performed on the first semiconductor structure 1 and the second semiconductor substructure. Illustratively, the N-type 4H-SiC substrate in the overall structure is removed.
S400: an ohmic contact layer 21 is formed on a side of the collector layer 22 facing away from the buffer layer 23, resulting in a second semiconductor structure 2 to form an IGBT device.
As shown in fig. 21, after a metal layer is deposited on the back surface and metal is stripped at a corresponding position, an ohmic contact layer 21 is formed through a laser annealing process, and the metal material of the ohmic contact layer 21 may be metallic titanium, metallic aluminum or an alloy of metallic titanium and metallic aluminum.
The beneficial effects of the method for manufacturing the planar silicon carbide IGBT device provided by the embodiment of the invention are the same as those of the planar silicon carbide IGBT device provided by the embodiment, and are not repeated here.
In addition, in the planar silicon carbide IGBT device provided by the embodiment of the invention, the upper half part structure and the lower half part structure form the device integral structure in a direct bonding mode, etching operation is performed on the back surface, the deposited polysilicon layer 24 forms a heterojunction structure, doping operation is not required to be performed on the deposited polysilicon layer 24, after the device is formed by bonding, preparation of the device is completed by depositing metal, excessive carriers under the conduction condition can be stored through the heterojunction structure, meanwhile, the composite speed in the heterojunction structure is improved, and the turn-off speed of the IGBT device is greatly improved.
The embodiment of the invention also provides electronic equipment, which comprises the planar silicon carbide IGBT device provided by the embodiment. The electronic device may be a terminal device or a communication device, but is not limited thereto.
Further, the terminal equipment comprises a mobile phone, a smart phone, a tablet computer, a computer, an artificial intelligent device, a mobile power supply and the like. The communication device includes a base station and the like, but is not limited thereto.
The beneficial effects of the electronic device provided by the embodiment of the invention are the same as those of the planar silicon carbide IGBT device provided by the embodiment, and the description is omitted here.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.

Claims (10)

1. A planar silicon carbide IGBT device, the planar silicon carbide IGBT device comprising: a first semiconductor structure and a second semiconductor structure bonded together from top to bottom;
the first semiconductor structure includes a drift layer, a current spreading layer formed over the drift layer, and a front side transistor cell;
the second semiconductor structure comprises an ohmic contact layer, a current collecting layer and a buffer layer which are sequentially formed on the ohmic contact layer, a groove is etched on one side, facing the drift layer, of the buffer layer, and a polycrystalline silicon layer is deposited in the groove;
the material of the buffer layer comprises silicon carbide, and the polycrystalline silicon layer and the buffer layer form a heterojunction structure.
2. The planar silicon carbide IGBT device of claim 1 wherein the polysilicon layer has a dimension in the stacking direction of the second semiconductor structure in the range of 0.5 μm to 2 μm.
3. The planar silicon carbide IGBT device of claim 1 wherein the polysilicon layer has a dimension in the direction perpendicular to the stacking direction of the second semiconductor structures in the range of 0.5 μm to 2 μm.
4. The planar silicon carbide IGBT device of claim 1 wherein the front side transistor cells comprise:
a P well region; the P well region is formed by performing ion implantation treatment on the current expansion layer;
an active region formed in the P-well region;
and a gate structure formed over the active region.
5. A method for manufacturing a planar silicon carbide IGBT device according to any one of claims 1 to 4, the method comprising:
providing a first semiconductor structure; wherein the first semiconductor structure comprises a drift layer, a current spreading layer and a front transistor unit which are sequentially formed above the drift layer;
providing a second semiconductor substructure; the second semiconductor substructure comprises a current collecting layer and a buffer layer, a groove is etched on one side of the buffer layer facing the drift layer, and a polysilicon layer is deposited in the groove; the material of the buffer layer comprises silicon carbide, and the polycrystalline silicon layer and the buffer layer form a heterojunction structure;
bonding the first semiconductor structure and the second semiconductor substructure through the drift layer and the buffer layer;
and forming an ohmic contact layer on one side of the current collection layer, which is away from the buffer layer, so as to obtain a second semiconductor structure, thereby forming the IGBT device.
6. The method of fabricating a planar silicon carbide IGBT device of claim 5 wherein the providing a first semiconductor structure comprises:
providing a first substrate;
epitaxially growing the drift layer on the first substrate;
performing ion implantation treatment on one side of the drift layer, which is away from the first substrate, to form the current expansion layer;
forming the front side transistor cell on the current spreading layer;
and removing the first substrate.
7. The method of fabricating a planar silicon carbide IGBT device of claim 6 wherein forming the front side transistor cells on the current spreading layer comprises:
performing ion implantation treatment on one side of the current expansion layer, which is away from the drift layer, to form a P well region;
performing ion implantation treatment on one side of the P well region far away from the drift layer to form an active region;
a gate structure is formed over the active region.
8. The method of fabricating a planar silicon carbide IGBT device of claim 5 wherein the providing a second semiconductor substructure comprises:
providing a second substrate;
epitaxially growing the collector layer on the second substrate;
epitaxially growing the buffer layer on the collector layer;
etching one side, away from the current collecting layer, of the buffer layer by using a mask to form a groove;
and depositing the polysilicon layer in the groove.
9. The method of fabricating a planar silicon carbide IGBT device of claim 8 wherein after the bonding process of the first semiconductor structure and the second semiconductor substructure through the drift layer and the buffer layer, before forming an ohmic contact layer on a side of the collector layer facing away from the buffer layer, the method further comprises:
and removing the second substrate.
10. An electronic device comprising the planar silicon carbide IGBT device according to any one of claims 1 to 4.
CN202311267422.0A 2023-09-27 2023-09-27 Planar silicon carbide IGBT device, manufacturing method thereof and electronic equipment Pending CN117410325A (en)

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