CN117316986A - Silicon carbide diode device and preparation method thereof - Google Patents

Silicon carbide diode device and preparation method thereof Download PDF

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Publication number
CN117316986A
CN117316986A CN202311405654.8A CN202311405654A CN117316986A CN 117316986 A CN117316986 A CN 117316986A CN 202311405654 A CN202311405654 A CN 202311405654A CN 117316986 A CN117316986 A CN 117316986A
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silicon carbide
region
epitaxial layer
contact metal
diode device
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Inventor
王正
杨程
万胜堂
王坤
陈鸿骏
赵耀
王毅
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Yangzhou Yangjie Electronic Co Ltd
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Yangzhou Yangjie Electronic Co Ltd
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Priority to CN202311405654.8A priority Critical patent/CN117316986A/en
Publication of CN117316986A publication Critical patent/CN117316986A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Crystallography & Structural Chemistry (AREA)
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  • Electrodes Of Semiconductors (AREA)

Abstract

A silicon carbide diode device and a method of making the same. To semiconductor devices. The silicon carbide epitaxial layer is arranged on the silicon carbide substrate, and the front electrode metal is arranged on the silicon carbide epitaxial layer; the top surface of the silicon carbide epitaxial layer is provided with a plurality of downward extending P region grooves, and a P type region is arranged in each P region groove; n region grooves are formed among the P-type regions; ohmic contact metal is arranged in the P-type region; the ohmic contact metal and the silicon carbide epitaxial layer are provided with Schottky junction contact metal; a front electrode metal is arranged above the Schottky junction contact metal; the conductivity types of the silicon carbide substrate and the silicon carbide epitaxial layer are both N type. The invention can reduce the on-resistance of the epitaxial layer of the device by forming two epitaxial layers with different doping concentrations, and further improve the current capacity of the device.

Description

Silicon carbide diode device and preparation method thereof
Technical Field
The present invention relates to semiconductor devices, and more particularly to a silicon carbide diode device and a method of making the same.
Background
As a third generation wide bandgap semiconductor material, silicon carbide has the material characteristics of wide bandgap, high critical breakdown field strength, small intrinsic carrier concentration, high electron saturation velocity, high thermal conductivity and the like compared with the traditional silicon-based material. The characteristics enable the silicon carbide device to have the advantages of higher application voltage, lower on-resistance, higher working temperature, higher power density and the like, and especially the silicon carbide device becomes the first choice in the future along with the technical development of the 800V platform in the field of new energy automobiles, the high-energy efficiency and low-loss in the field of photovoltaic energy storage inversion, the high-voltage quick-charging pile in the field of charging piles and the like.
Silicon carbide diodes are a device suitable for use in high power environments and are currently used primarily in the 650V to 1700V voltage regime. In order to realize larger application voltage, research on super junction silicon carbide JBS devices has been started in the industry, the reverse voltage resistance of the devices is improved under the condition that the thickness and doping concentration of the drift layer are not changed greatly, and the reliability and stability of the devices under the application condition of higher voltage are ensured. Although the reverse voltage endurance capability of the silicon carbide JBS can be greatly improved by the superjunction structure, the forward current capacity of the device is reduced, the conduction loss is improved, and the use is influenced.
Disclosure of Invention
The invention designs a silicon carbide diode device, improves the forward current capacity of a super junction silicon carbide JBS device, and provides a preparation method of the silicon carbide diode device.
The technical scheme of the invention is as follows:
a silicon carbide diode device comprises a silicon carbide substrate, a silicon carbide epitaxial layer and a front electrode metal which are sequentially arranged from bottom to top;
the top surface of the silicon carbide epitaxial layer is provided with a plurality of downward extending P region grooves, and a P type region is arranged in each P region groove;
n region grooves are formed among the P-type regions;
ohmic contact metal is arranged in the P-type region;
the ohmic contact metal and the silicon carbide epitaxial layer are provided with Schottky junction contact metal;
a front electrode metal is arranged above the Schottky junction contact metal;
specifically, the conductivity types of the silicon carbide substrate and the silicon carbide epitaxial layer are both N-type.
Specifically, the silicon carbide epitaxial layer comprises a silicon carbide drift layer and a silicon carbide epitaxial layer which are sequentially arranged from bottom to top.
Specifically, the pitches of the P-type regions are the same.
Specifically, the interval between the P-type regions is 2.5-3um.
A method of fabricating a silicon carbide diode device, comprising the steps of:
s100, growing a silicon carbide epitaxial layer on a silicon carbide substrate;
s200, forming a plurality of P region grooves on the silicon carbide epitaxial layer through an etching process;
s300, forming a P-type region in the P-region groove through ion implantation and high-temperature activation annealing;
s400, forming N-region grooves between adjacent P-region grooves by using an etching process;
s500, depositing metal Ni on a P-type region in a P-region groove, and forming ohmic contact metal through rapid thermal annealing;
s600, forming a Schottky junction contact metal by depositing metal Ti above the ohmic contact metal and the silicon carbide epitaxial layer and performing rapid thermal annealing;
and S700, depositing front electrode metal on the Schottky junction contact metal to be led out as an electrode.
Specifically, the depth of the N-region trench in the step S400 is 3/5-3/4 of the depth of the P-region trench.
Specifically, in step S300, al ions are implanted.
Compared with a super-junction silicon carbide JBS structure, the invention has the following effects:
according to the invention, the P region groove is etched on the silicon carbide JBS epitaxial layer, and the deep P type region is formed through ion implantation, so that the super junction structure is realized, the reverse voltage resistance of the silicon carbide JBS device is improved, and the probability of reverse breakdown of the device is reduced in advance. In order to ensure the forward current capacity of the device at the same time, a groove type Schottky junction contact is formed by etching, the contact area of the Schottky junction is increased, and the current capacity of the device is improved. In addition, the on-resistance of the epitaxial layer of the device can be reduced by forming two epitaxial layers with different doping concentrations, and the current capacity of the device is further improved.
Drawings
Fig. 1 is a schematic diagram of the structure of an epitaxial layer grown in step S100;
fig. 2 is a schematic structural diagram of step S200 after etching the P-region trench;
FIG. 3 is a schematic diagram illustrating the structure of forming deep P region by ion implantation in step S300;
FIG. 4 is a schematic diagram of the structure after etching the N-region trench in step S400;
fig. 5 is a schematic structural diagram after depositing ohmic contact metal in step S500;
fig. 6 is a schematic structural diagram of the schottky junction contact metal deposited in step S600;
FIG. 7 is a schematic diagram of the structure after deposition of front electrode metal in step S700;
in the figure, 1 is a silicon carbide substrate, 2a is a carbonization drift layer, 2b is a silicon carbide epitaxial layer, 3 is an etched P-region trench, 4 is a P-type region, 5 is an N-region trench, 6 is an ohmic contact metal, 7 is a schottky junction contact metal, and 8 is a front electrode metal.
Detailed Description
The present invention will be described in detail with reference to specific practical examples. Examples of which are shown in the accompanying drawings and the description thereof are for the purpose of illustrating the invention only and are not to be construed as limiting the invention.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. In the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
A silicon carbide diode device comprises a silicon carbide substrate 1, a silicon carbide epitaxial layer 2 and a front electrode metal 8 which are arranged in sequence from bottom to top;
the top surface of the silicon carbide epitaxial layer 2 is provided with a plurality of downward extending P region grooves 3, and a P type region 4 is arranged in each P region groove 3;
n region grooves 5 are arranged among the P-type regions 4;
ohmic contact metal 6 is arranged in the P-type region 4;
the ohmic contact metal 6 and the silicon carbide epitaxial layer 2 are provided with a Schottky junction contact metal 7;
a front electrode metal 8 is arranged above the Schottky junction contact metal 7;
further defined, the conductivity type of the silicon carbide substrate 1 and the silicon carbide epitaxial layer 2 are both N-type.
Further defined, the silicon carbide epitaxial layer 2 includes a silicon carbide drift layer 2a and a silicon carbide epitaxial layer 2b disposed in this order from below.
The doping impurities of the silicon carbide drift layer 2a and the silicon carbide epitaxial layer 2b are the same, are N ions, and the doping concentrations can be the same or different, so that the doping of the silicon carbide drift layer 2aThe concentration is 1E16/cm 3 The doping concentration of the silicon carbide epitaxial layer 2b is more than or equal to 1E16/cm 3 . The silicon carbide drift layer 2a has the function of forming an electric field shielding function with the P-type region, so that the voltage-resistant capability of the device is ensured, the concentration is lower, and the silicon carbide epitaxial layer 2b hardly bears the electric field shielding function in the scheme, so that the doping concentration can be larger, the on-resistance of the device is reduced, and the current-passing capability is improved.
Further defined, the pitches of the P-type regions 4 are the same.
Further defined, the pitch of the P-type regions 4 is 2.5-3um. In this range, the reverse breakdown voltage performance of the device can be sufficiently ensured, for example, a 650V silicon carbide diode, whose reverse breakdown voltage can be as low as 750V.
A method of fabricating a silicon carbide diode device, comprising the steps of:
s100, growing a silicon carbide epitaxial layer 2 on a silicon carbide substrate 1; referring to fig. 1;
s200, forming a patterned mask oxide layer on the silicon carbide epitaxial layer 2 through dielectric film deposition, photoetching and etching, and forming a plurality of P region grooves 3 through an etching process; referring to fig. 2;
s300, forming a patterned mask oxide layer in the P region groove 3 through dielectric film deposition, photoetching and etching processes, and then forming a P type region 4 through ion implantation and high-temperature activation annealing; referring to fig. 3;
s400, forming an N-region groove 5 by utilizing an etching process after forming a patterned mask oxide layer between adjacent P-region grooves 3 through dielectric film deposition, photoetching and etching; referring to fig. 4;
further preferably, the depth of the N region groove 5 is between 3/5 and 4/5 of the depth of the P region groove 3, wherein the depth of 4/5 is the optimal condition.
Because the deep P region influences the through flow of the Schottky junction contact at the side wall of the N region groove 5, when the depth of the N region groove 5 is less than 3/5 of the depth of the P region groove 3, the through flow is realized at the bottom of the N region groove, and when the depth is greater than 3/5, the through flow is realized at the side wall of the N region groove, and the through flow capacity is stronger as the depth of the N region groove 5 is greater. However, in order to ensure stable reverse performance of the device, the depth of the N-region trench 5 is set to be at most 4/5 of the depth of the P-region trench 3, so as to avoid device failure caused by increase of reverse leakage current.
S500, depositing metal Ni on the P-type region 4 in the P-region groove 3, and forming ohmic contact metal 6 through rapid thermal annealing; referring to fig. 5;
s600, forming a Schottky junction contact metal 7 by depositing metal Ti above the ohmic contact metal 6 and the silicon carbide epitaxial layer 2 and performing rapid thermal annealing; referring to fig. 6;
s700, depositing front electrode metal 8 on the Schottky junction contact metal 7 to be led out as an electrode; reference is made to fig. 7.
Further defined, the depth of the N-region trench 5 in the step S400 is 3/5-3/4 of the depth of the P-region trench 3.
When the depth of the N region groove is smaller than 3/5 of the depth of the P region groove, the deep P region blocks the through flow of the side wall of the N region groove, and the improvement of the through flow capacity of the device is seriously affected; when the depth of the N-region groove is 3/5 of that of the P-region groove, the side wall of the N-region groove starts to flow, the flow capacity of the device is improved by 42% compared with that of a super-junction silicon carbide JBS device contacted by a planar Schottky junction, and when the depth of the N-region groove reaches 4/5, the flow capacity is improved by 64%.
Further limited, in the step S300, the ion implantation is Al ion, the implantation temperature is 400-600 ℃, and the high-temperature activation annealing temperature is 1600-1900 ℃ after the implantation is completed.
Compared with the planar silicon carbide JBS, the super junction silicon carbide JBS device has the advantages that the reverse voltage endurance capability is greatly improved, but the forward current passing capability of the device is influenced by the super junction structure, and the conduction loss of the device is improved. The groove type Schottky junction contact is formed through etching, the Schottky junction contact area is increased, the forward current capacity of the super junction silicon carbide JBS device is improved, and the conduction loss is reduced. Through verification, the forward through-flow capacity of the structure of the invention is improved by 42-64%. In addition, ohmic contact is formed in the deep P region, so that surge current impact bearing capacity of the device is improved.
Compared with a super junction silicon carbide diode with a planar N region, the through-flow capacity of the device is remarkably improved by forming the N region groove through etching. As the table shows, when the ratio of the etching depth of the N-region trench to the junction depth of the P-region is 2:5, the through-flow capacity is improved by 35%, and when the depth ratio is 3:5, by 66%, when the depth ratio is 4:5, 112% improvement. It follows that the device throughput can be increased by at least half when the ratio is in the range of 3/5 to 4/5, and by a factor of 1 when the ratio is 4/5, which is the optimal choice.
For the purposes of this disclosure, the following points are also described:
(1) The drawings of the embodiments disclosed in the present application relate only to the structures related to the embodiments disclosed in the present application, and other structures can refer to common designs;
(2) The embodiments disclosed herein and features of the embodiments may be combined with each other to arrive at new embodiments without conflict;
the above is only a specific embodiment disclosed in the present application, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (8)

1. A silicon carbide diode device, which is characterized by comprising a silicon carbide substrate (1), a silicon carbide epitaxial layer (2) and a front electrode metal (8) which are sequentially arranged from bottom to top;
the top surface of the silicon carbide epitaxial layer (2) is provided with a plurality of P region grooves (3) extending downwards, and a P type region (4) is arranged in each P region groove (3);
n region grooves (5) are formed among the P-type regions (4);
ohmic contact metal (6) is arranged in the P-type region (4);
the ohmic contact metal (6) and the silicon carbide epitaxial layer (2) are provided with Schottky junction contact metal (7);
and a front electrode metal (8) is arranged above the Schottky junction contact metal (7).
2. A silicon carbide diode device according to claim 1, characterized in that the conductivity type of the silicon carbide substrate (1) and the silicon carbide epitaxial layer (2) are both N-type.
3. A silicon carbide diode device according to claim 1 or 2, characterized in that the silicon carbide epitaxial layer (2) comprises a silicon carbide drift layer (2 a) and a silicon carbide epitaxial layer (2 b) arranged in sequence from below.
4. A silicon carbide diode device according to claim 1, characterized in that the pitch of several of the P-type regions (4) is the same.
5. A silicon carbide diode device according to claim 4, characterized in that the pitch of the P-type regions (4) is 2.5-3um.
6. A method of fabricating a silicon carbide diode device, comprising the steps of:
s100, growing a silicon carbide epitaxial layer (2) on a silicon carbide substrate (1);
s200, forming a plurality of P region grooves (3) on the silicon carbide epitaxial layer (2) through an etching process;
s300, forming a P-type region (4) in the P-region groove (3) through ion implantation and high-temperature activation annealing;
s400, forming N region grooves (5) between adjacent P region grooves (3) by using an etching process;
s500, depositing metal Ni on a P-type region (4) in a P-region groove (3), and forming ohmic contact metal (6) through rapid thermal annealing;
s600, forming a Schottky junction contact metal (7) above the ohmic contact metal (6) and the silicon carbide epitaxial layer (2) through depositing metal Ti and performing rapid thermal annealing;
and S700, depositing a front electrode metal (8) on the Schottky junction contact metal (7) to be led out as an electrode.
7. A method of fabricating a silicon carbide diode device according to claim 6 wherein the depth of the N-region trench (5) in step S400 is between 3/5 and 3/4 of the depth of the P-region trench (3).
8. The method of manufacturing a silicon carbide diode device according to claim 6, wherein the ion implantation in step S300 is performed as Al ions.
CN202311405654.8A 2023-10-27 2023-10-27 Silicon carbide diode device and preparation method thereof Pending CN117316986A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311405654.8A CN117316986A (en) 2023-10-27 2023-10-27 Silicon carbide diode device and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311405654.8A CN117316986A (en) 2023-10-27 2023-10-27 Silicon carbide diode device and preparation method thereof

Publications (1)

Publication Number Publication Date
CN117316986A true CN117316986A (en) 2023-12-29

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