CN117294283A - Programmable double-side delay device based on ferroelectric capacitor - Google Patents

Programmable double-side delay device based on ferroelectric capacitor Download PDF

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Publication number
CN117294283A
CN117294283A CN202311567451.9A CN202311567451A CN117294283A CN 117294283 A CN117294283 A CN 117294283A CN 202311567451 A CN202311567451 A CN 202311567451A CN 117294283 A CN117294283 A CN 117294283A
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electrically connected
circuit
pulse
delay
edge delay
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CN202311567451.9A
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CN117294283B (en
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张盛
马月
李欣瑜
李昌荣
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Crystal Iron Semiconductor Technology Guangdong Co ltd
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Crystal Iron Semiconductor Technology Guangdong Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15006—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two programmable outputs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses a programmable double-side delay device based on a ferroelectric capacitor, which adopts an RC delay circuit formed by the ferroelectric capacitor, a resistor and a field effect transistor to generate a delay signal, compared with the traditional inverter delay circuit, the programmable double-side delay device has higher precision naturally, and an inverter is not required to be connected in series when the delay signal is generated, so that the problems of error increase and larger occupied chip area caused by the cascade inverter in the traditional technology can be avoided; meanwhile, the capacitance value of the ferroelectric capacitor can be steplessly changed by controlling the voltage, so that a programmable stepless time delay effect can be realized, and the time delay can be flexibly adjusted on the basis of not changing the hardware structure; in addition, the invention can obtain the output pulse with the same rising edge and falling edge time delay, based on the output pulse, the problem of different rising edge and falling edge time delay in the traditional technology is solved, and the time delay precision is further improved.

Description

Programmable double-side delay device based on ferroelectric capacitor
Technical Field
The invention belongs to the technical field of semiconductor integrated circuit design, and particularly relates to a programmable double-side delay device based on a ferroelectric capacitor.
Background
The cascade delay circuit is used as CLK and RST of the programmable time sequence generating circuit, and is composed of basic delay units, wherein the basic delay units are shown in figure 1, the core of the basic delay units is a delay structure composed of a PMOS tube P1 and a capacitor C1, and the subsequent inverters and buffers are used for pulse shaping; then, by using inverters (INV 1-INV4 in fig. 1) to perform series operation on the basic delay units, a high-level pulse with a narrower width can be stretched to generate a series of signals with gradually increased falling edge delay; finally, the signals are reasonably distributed to the CLK and RST terminals of the register, so that any signal actually needed can be generated.
However, the cascade delay circuit described above has the following disadvantages: (1) The delay effect is realized by connecting a plurality of inverters in series, the delay precision is greatly influenced by the process of the inverters, and the error is aggravated after cascading, so that the delay precision is reduced, and the delay of the rising edge and the falling edge is inconsistent; (2) A plurality of inverters are connected in series, so that a larger area of the chip is occupied; (3) inconvenient delay time adjustment; increasing the delay time requires increasing the number of inverters connected in series, thereby further reducing the precision, improving the occupied area of the chip, changing the circuit structure and having complex operation; based on this, how to provide a delay circuit with high precision, small chip occupation area and stepless adjustable delay time has become a problem to be solved.
Disclosure of Invention
The invention aims to provide a programmable double-side delay device based on a ferroelectric capacitor, which is used for solving the problems of low delay precision, inconsistent delay of a rising edge and a falling edge, large occupied chip area and inconvenience in delay time adjustment in the prior art that a plurality of inverters are connected in series to generate a delay signal.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
in a first aspect, a programmable double-sided delay device based on ferroelectric capacitors is provided, comprising:
the double-side delay unit comprises a rising edge delay circuit and a falling edge delay circuit, and the rising edge delay circuit and the falling edge delay circuit comprise a first field effect transistor, a second field effect transistor, a ferroelectric capacitor and a resistor;
the grid electrode of the first field effect tube is used as an input end and is used for receiving an input signal, wherein the source electrode of the first field effect tube is electrically connected with one end of the resistor, the other end of the resistor is respectively and electrically connected with the source electrode of the second field effect tube and one end of the ferroelectric capacitor, and the grid electrode of the second field effect tube is electrically connected with the grid electrode of the first field effect tube;
the drain electrode of the first field effect transistor and the drain electrode of the second field effect transistor are electrically connected with a first power supply, wherein the other end of the ferroelectric capacitor is electrically connected with a second power supply, and the common connection end of the ferroelectric capacitor, the resistor and the second field effect transistor is used as an output end and is electrically connected with the pulse integration unit;
the pulse integration unit is used for carrying out pulse shaping on the rising edge pulse signal output by the rising edge delay circuit and the falling edge pulse signal output by the falling edge delay circuit, and carrying out pulse integration on the rising edge pulse signal after pulse shaping and the falling edge pulse signal after pulse shaping so as to obtain the output pulse signal with the same rising edge delay and the falling edge delay.
Based on the disclosure, the delay device provided by the invention comprises a rising edge delay circuit, a falling edge delay circuit and a pulse integration unit, wherein the two delay circuits are RC delay circuits formed by adopting ferroelectric capacitors, resistors and field effect transistors, compared with the traditional inverter delay circuit, the RC delay circuit has higher precision naturally, and an inverter is not required to be connected in series when delay signals are generated, so that the problems of error increase and larger occupied chip area caused by the cascade inverter in the prior art can be avoided; meanwhile, the capacitance value of the ferroelectric capacitor can be steplessly changed by controlling the voltage, so that a programmable stepless time delay effect can be realized, and the time delay can be flexibly adjusted on the basis of not changing the hardware structure, thereby meeting various application requirements; in addition, the pulse integration unit can perform pulse shaping and integration on delay signals generated by the two delay circuits, so that output pulses with the same rising edge delay and falling edge delay are obtained, and based on the output pulses, the problem that the rising edge delay and the falling edge delay in the traditional technology are different is solved, and the delay precision is further improved; therefore, the delay circuit provided by the invention has the advantages of high delay precision, small occupied chip area, realization of stepless adjustment of delay time and suitability for large-scale application and popularization in the field of delay circuits.
In one possible design, the pulse integration unit includes a first pulse shaping circuit, a second pulse shaping circuit, a first combinational logic circuit, a second combinational logic circuit, and a flip-flop;
the output end of the rising edge delay circuit is electrically connected with the input end of the first pulse shaping circuit, wherein the output end of the first pulse shaping circuit is electrically connected with the input end of the first combinational logic circuit, and the output end of the first combinational logic circuit is electrically connected with the first input end of the trigger;
the output end of the falling edge delay circuit is electrically connected with the input end of the second pulse shaping circuit, wherein the output end of the second pulse shaping circuit is electrically connected with the input end of the second combinational logic circuit, the output end of the second combinational logic circuit is electrically connected with the second input end of the trigger, and the output end of the trigger outputs the output pulse signal.
In one possible design, the first combinational logic circuit includes a first and gate, where a first input terminal of the first and gate is electrically connected to an output terminal of the first pulse shaping circuit, a second input terminal of the first and gate is electrically connected to a gate of a second field effect transistor in the rising edge delay circuit, and an output terminal of the first and gate is electrically connected to a first input terminal of the flip-flop.
In one possible design, the second combinational logic circuit includes a first not gate and a second and gate, where a first input terminal of the second and gate is electrically connected to an output terminal of the second pulse shaping circuit, and a second input terminal of the first and gate is electrically connected to a gate of a second field effect transistor in the falling edge delay circuit, for receiving the input signal;
the output end of the second AND gate is electrically connected with the input end of the first NOT gate, and the output end of the first NOT gate is electrically connected with the second input end of the trigger.
In one possible design, the first pulse shaping circuit and the second pulse shaping circuit each employ a schmitt trigger.
In one possible design, the flip-flop employs an asynchronous clear 0 to 1D flip-flop.
In one possible design, the method further comprises: and the input end of the first buffer is used for receiving the input signal, and the output end of the first buffer is electrically connected with the input ends of the rising edge delay circuit and the falling edge delay circuit respectively.
In one possible design, the input of the falling edge delay circuit is electrically connected to a second not gate, wherein the input signal is transmitted to the falling edge delay circuit through the second not gate.
In one possible design, the output end of the pulse integration unit is also electrically connected with a second buffer, and the second buffer is used for driving the output pulse signal.
In one possible design, RC time constants of the rising edge delay circuit and the falling edge delay circuit are greater than a preset value, so as to increase circuit response time of the rising edge delay circuit and the falling edge delay circuit, so that pulse widths of the output rising edge pulse signal and the output falling edge pulse signal are greater than the input signal.
The beneficial effects are that:
(1) The precision and stability are good: the circuit can provide better precision and stability to a certain extent, and the reason is that: compared with an inverter delay circuit, the RC delay circuit has higher natural delay precision; meanwhile, the precision of the inverter chain delay circuit mainly depends on the performance of the inverter and is greatly influenced by process variation and environment (temperature and the like), and the invention does not need to use inverter cascading to generate delay signals, so that the problem of error increase caused by cascading inverters in the traditional technology can be avoided, and the delay precision can be further improved.
(2) The delay time can be adjusted steplessly; according to the invention, the ferroelectric capacitor is introduced into the delay circuit, and the programmable stepless delay effect can be realized through the capacitance programmable characteristic of the ferroelectric capacitor (namely, the ferroelectric capacitor can steplessly change the capacitance value by controlling the voltage); thus, the delay time can be flexibly adjusted, thereby meeting various application requirements.
(3) The occupied chip area is small; the circuit provided by the invention can realize longer delay in a smaller area, and the inverter chain needs more inverters to realize the same delay, so that the RC delay circuit occupies smaller chip area compared with the inverter delay circuit.
(4) The time delay of the upper edge and the lower edge is controllable; the invention is provided with the rising edge delay circuit and the falling edge delay circuit, can control the delay of the rising edge and the falling edge, and can adapt to various application requirements.
(5) The rising edge delay is the same as the falling edge delay; the invention is provided with a pulse integration unit which can integrate the pulse of the delay signals generated by the two delay circuits through an internal combinational logic circuit and a trigger, thereby obtaining the output pulse with the same delay of the rising edge and the falling edge; thus, the problem that the rising edge delay and the falling edge delay in the traditional technology are different is solved, and the delay precision is further improved.
Drawings
Fig. 1 is a schematic circuit diagram of a conventional basic delay unit;
FIG. 2 is a circuit block diagram of a programmable double-sided delay device based on ferroelectric capacitors according to an embodiment of the present invention;
fig. 3 is a detailed circuit diagram of a programmable dual-side delay device based on ferroelectric capacitors according to an embodiment of the present invention.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the present invention will be briefly described below with reference to the accompanying drawings and the description of the embodiments or the prior art, and it is obvious that the following description of the structure of the drawings is only some embodiments of the present invention, and other drawings can be obtained according to these drawings without inventive effort to a person skilled in the art. It should be noted that the description of these examples is for aiding in understanding the present invention, but is not intended to limit the present invention.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments of the present invention.
It should be understood that for the term "and/or" that may appear herein, it is merely one association relationship that describes an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a alone, B alone, and both a and B; for the term "/and" that may appear herein, which is descriptive of another associative object relationship, it means that there may be two relationships, e.g., a/and B, it may be expressed that: a alone, a alone and B alone; in addition, for the character "/" that may appear herein, it is generally indicated that the context associated object is an "or" relationship.
Examples:
referring to fig. 2 and 3, the programmable double-sided delay device based on ferroelectric capacitor according to the present embodiment may include, but is not limited to: the double-sided delay unit is used for generating delay signals, namely rising edge pulse signals and falling edge pulse signals; the pulse integrating unit is used for carrying out pulse shaping on the delay signal and carrying out delay adjustment (the delay of the rising edge and the delay of the falling edge are adjusted to be consistent), and finally integrating the delay signal into an output pulse signal with consistent delay of the rising edge and the falling edge.
In a specific application, the bilateral delay unit includes a rising edge delay circuit and a falling edge delay circuit, where the rising edge delay circuit and the falling edge delay circuit have the same circuit structure, and may include, but not limited to: the device comprises a first field effect tube, a second field effect tube, a ferroelectric capacitor and a resistor, wherein the devices in a rising edge delay circuit are sequentially named as a first field effect tube P2, a second field effect tube P3, a ferroelectric capacitor C2 and a resistor R2, and the devices in a falling edge delay circuit are sequentially named as a first field effect tube P4, a second field effect tube P5, a ferroelectric capacitor C3 and a resistor R3; further, the specific connection structure of each electronic device is as follows:
referring to fig. 3, the gate of the first fet is used as an input terminal (the gate of the first fet P2 is used as an input terminal of a rising edge delay circuit, the gate of the first fet P4 is used as an input terminal of a falling edge delay circuit, meanwhile, the gates of the two first fets are also used as input terminal switches of respective delay circuits and can be used for controlling input of input signals) for receiving input signals, wherein the source of the first fet is electrically connected with one end of the resistor (the source of the first fet P2 is electrically connected with one end of the resistor R2, the source of the first fet P4 is electrically connected with one end of the resistor R3), the other end of the resistor is electrically connected with the source of the second fet and one end of the ferroelectric capacitor (the other end of the resistor R2 is electrically connected with the source of the second fet P3 and one end of the ferroelectric capacitor C2), and the other end of the resistor R3 is electrically connected with the source of the second fet P5 and one end of the ferroelectric capacitor C3, and the other end of the second fet is electrically connected with the first fet P2, the first fet P4 is electrically connected with the gate of the first fet P2.
Meanwhile, the drain electrode of the first fet and the drain electrode of the second fet are electrically connected to a first power supply (in the rising edge delay circuit, the drain electrode of the second fet P2 and the drain electrode of the second fet P3 are electrically connected to a VDD power supply, and in the falling edge delay circuit, the drain electrode of the second fet P4 and the drain electrode of the second fet P3 are electrically connected to a VDD power supply), wherein the other end of the ferroelectric capacitor is electrically connected to a second power supply (i.e., ferroelectric capacitors C2 and C3 are electrically connected to a VSS power supply), and the common connection ends of the ferroelectric capacitor, the resistor and the second fet serve as output ends, and are electrically connected to the pulse integration unit.
Thus, the working principle of the delay circuit is as follows: when the edge of the input signal comes, the ferroelectric capacitor starts to charge or discharge, so that the output signal is changed; the delay effect can be realized by controlling the charge and discharge processes of the capacitor; meanwhile, the capacitance value of the ferroelectric capacitor can be adjusted by changing the direction and the intensity of an external electric field of the ferroelectric capacitor, so that the delay circuit can realize stepless adjustable delay, thereby meeting various application requirements; further, for example, the RC time constants of the rising edge delay circuit and the falling edge delay circuit are greater than a preset value (the RC time constant is usually the product of a resistor and a capacitor, and the preset value may be specifically set according to practical use, in this embodiment, the larger RC time constant may be set), so that the circuit response time of the rising edge delay circuit and the falling edge delay circuit can be increased, so that the pulse width of the output rising edge pulse signal and the output falling edge pulse signal is greater than the input signal; thus, the pulse amplitude can be gradually changed, and the rising edge and the falling edge of the output signal become more gentle.
After generating the rising edge pulse signal and the falling edge pulse signal based on the double-sided delay unit, the pulse integration unit can be utilized to perform signal processing of the delay signal, wherein the processing process is as follows: the pulse integration unit is used for carrying out pulse shaping on the rising edge pulse signal output by the rising edge delay circuit and the falling edge pulse signal output by the falling edge delay circuit, and carrying out pulse integration on the rising edge pulse signal after pulse shaping and the falling edge pulse signal after pulse shaping so as to obtain the output pulse signal with the same rising edge delay and the falling edge delay.
Therefore, through the foregoing explanation, the RC delay circuit formed by the ferroelectric capacitor, the resistor and the field effect transistor is adopted to generate the delay signal, so that compared with the traditional inverter delay circuit, the precision is higher, and a plurality of inverters are not required to be cascaded when the delay signal is generated, so that the problems of error increase and occupation of a larger area of a chip in the traditional technology are avoided; meanwhile, the voltage of the ferroelectric capacitor is regulated, so that the capacitor value can be regulated, a programmable stepless time delay effect can be realized, and the time delay can be flexibly regulated on the basis of not changing a hardware structure; in addition, through the pulse integration unit, the adjustment of rising edge delay and falling edge delay can be realized to obtain the same output pulse signal of rising edge delay and falling edge delay, based on this, solved the inconsistent problem of traditional technique delay, further improved the delay precision.
Referring to fig. 2 and 3, a specific circuit structure of the pulse integrating unit is provided as follows.
In a specific embodiment, the pulse integrating unit may include, but is not limited to: the pulse shaping circuit comprises a first pulse shaping circuit, a second pulse shaping circuit, a first combination logic circuit, a second combination logic circuit and a trigger, wherein the specific connection relation of the circuits is as follows:
referring to fig. 2, the output end of the rising edge delay circuit is electrically connected to the input end of the first pulse shaping circuit, where the output end of the first pulse shaping circuit is electrically connected to the input end of the first combinational logic circuit, and the output end of the first combinational logic circuit is electrically connected to the first input end of the flip-flop; similarly, the output end of the falling edge delay circuit is electrically connected with the input end of the second pulse shaping circuit, the output end of the second pulse shaping circuit is electrically connected with the input end of the second combinational logic circuit, the output end of the second combinational logic circuit is electrically connected with the second input end of the trigger, and the output end of the trigger outputs the output pulse signal.
Through the explanation of the pulse integration unit, after each delay circuit outputs a delay signal, pulse shaping is carried out through the respective pulse shaping circuit to obtain a pulse signal with steep and clear edges, then the delay adjustment of the shaped rising edge pulse signal and the shaped falling edge pulse signal is carried out through the trigger and the respective logic circuit, so that the delay of the rising edge pulse signal and the delay of the falling edge pulse signal are consistent, and finally the trigger outputs an output pulse signal with consistent rising edge delay and falling edge delay.
Optionally, the following discloses specific structures of each circuit in the pulse integrating unit:
in a specific application, for example, the first pulse shaping circuit and the second pulse shaping circuit each use schmitt triggers, as shown in fig. 3, that is, SMT1 and SMT2 in fig. 3, and the triggers use asynchronous clear 0 to set 1D triggers (that is, D Flip-flop in fig. 3).
The working principle of the first pulse shaping circuit and the second pulse shaping circuit is as follows:
the embodiment uses a schmitt trigger to carry out pulse shaping, and can convert the output waveform of the delay circuit into a pulse waveform with steep edges; the pulse signal processed by the RC delay circuit is input to the input end of the Schmitt trigger, the upper threshold (Uth) and the lower threshold (Lth) of the Schmitt trigger are designated, when the amplitude of the input signal exceeds the upper threshold, the Schmitt trigger outputs a high level (VDD), and when the amplitude of the input signal is lower than the lower threshold, the Schmitt trigger outputs a low level (0), so that the pulse signal with steep edges and cleanness can be obtained as the output of the Schmitt trigger, and the function of the pulse shaping circuit is completed.
Meanwhile, referring to fig. 3, an example of the first combinational logic circuit may include, but is not limited to, a first and gate U1, wherein a first input terminal of the first and gate U1 is electrically connected to an output terminal of the first pulse shaping circuit (i.e., electrically connected to an output terminal of the schmitt trigger SMT 1), a second input terminal of the first and gate U1 is electrically connected to a gate of the second fet P3 in the rising edge delay circuit, and an output terminal of the first and gate U1 is electrically connected to a first input terminal of the trigger.
Similarly, referring also to fig. 3, an example second combinational logic circuit may include, but is not limited to: the first input end of the second and gate U2 is electrically connected to the output end of the second pulse shaping circuit (i.e. electrically connected to the output end of the schmitt trigger SMT 2), and the second input end of the first and gate U2 is electrically connected to the gate of the second fet P5 in the falling edge delay circuit, so as to receive the input signal; meanwhile, the output end of the second AND gate U2 is electrically connected with the input end of the first NOT gate U2, and the output end of the first NOT gate U2 is electrically connected with the second input end of the trigger.
The detailed structure of each circuit in the pulse integrating unit is thus explained by the foregoing: in this embodiment, after pulse shaping of the schmitt triggers, pulse signals output by the two delay circuits are integrated by the combination logic circuit and the asynchronous 0-D trigger, so that output pulses with the same rising edge delay and falling edge delay can be obtained, and thus, the pulse accuracy is further improved.
In one possible design, the following provides a more abundant circuit structure of the double-sided delay device.
Referring to fig. 2 and 3, the double-sided delay device may also include, but is not limited to: a first buffer BUF1, a second buffer BUF2, and a second not gate U4; wherein, the arrangement structure of each device is as follows:
in a specific application, the first buffer BUF1 is disposed before the two delay circuits, that is, the input end of the first buffer BUF1 is used for receiving the input signal to drive the input signal, and the output end of the first buffer BUF1 is electrically connected to the input ends of the rising edge delay circuit and the falling edge delay circuit (that is, the gate of the first fet P2 and the gate of the third fet P4) respectively, and is used for transmitting the input signal to the two delay circuits, so as to generate a rising edge pulse signal and a falling edge pulse signal.
Meanwhile, the second NOT gate U4 is arranged between the first buffer and the falling edge delay circuit, namely, the input end of the falling edge delay circuit is electrically connected with the second NOT gate U4 (namely, the first buffer BUF1 is electrically connected with the grid electrode of the third field effect transistor P4 through the second NOT gate U4); therefore, the input signal is transmitted to the falling edge delay circuit through the second NOT gate U4, so that the falling edge pulse signal is generated by the falling edge delay circuit.
In addition, in this embodiment, the second buffer BUF2 is disposed after the asynchronous 0D flip-flop, specifically, the output end of the pulse integrating unit is further electrically connected with the second buffer, that is, the second buffer BUF2 at the output end of the asynchronous 0D flip-flop; in this way, an electrical connection can be used for driving the output pulse signal with the second buffer BUF2, thereby facilitating the invocation of the processor.
Therefore, compared with the traditional reverse delay circuit, the invention has the advantages of high delay precision, small occupied chip area, and capability of realizing stepless adjustment of delay time, and is very suitable for large-scale application and popularization in the field of delay circuits.
Finally, it should be noted that: the foregoing description is only of the preferred embodiments of the invention and is not intended to limit the scope of the invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A ferroelectric capacitor-based programmable double-sided delay device, comprising:
the double-side delay unit comprises a rising edge delay circuit and a falling edge delay circuit, and the rising edge delay circuit and the falling edge delay circuit comprise a first field effect transistor, a second field effect transistor, a ferroelectric capacitor and a resistor;
the grid electrode of the first field effect tube is used as an input end and is used for receiving an input signal, wherein the source electrode of the first field effect tube is electrically connected with one end of the resistor, the other end of the resistor is respectively and electrically connected with the source electrode of the second field effect tube and one end of the ferroelectric capacitor, and the grid electrode of the second field effect tube is electrically connected with the grid electrode of the first field effect tube;
the drain electrode of the first field effect transistor and the drain electrode of the second field effect transistor are electrically connected with a first power supply, wherein the other end of the ferroelectric capacitor is electrically connected with a second power supply, and the common connection end of the ferroelectric capacitor, the resistor and the second field effect transistor is used as an output end and is electrically connected with the pulse integration unit;
the pulse integration unit is used for carrying out pulse shaping on the rising edge pulse signal output by the rising edge delay circuit and the falling edge pulse signal output by the falling edge delay circuit, and carrying out pulse integration on the rising edge pulse signal after pulse shaping and the falling edge pulse signal after pulse shaping so as to obtain the output pulse signal with the same rising edge delay and the falling edge delay.
2. The ferroelectric capacitor based programmable double edge delay device of claim 1 wherein the pulse integrating unit comprises a first pulse shaping circuit, a second pulse shaping circuit, a first combinational logic circuit, a second combinational logic circuit, and a flip-flop;
the output end of the rising edge delay circuit is electrically connected with the input end of the first pulse shaping circuit, wherein the output end of the first pulse shaping circuit is electrically connected with the input end of the first combinational logic circuit, and the output end of the first combinational logic circuit is electrically connected with the first input end of the trigger;
the output end of the falling edge delay circuit is electrically connected with the input end of the second pulse shaping circuit, wherein the output end of the second pulse shaping circuit is electrically connected with the input end of the second combinational logic circuit, the output end of the second combinational logic circuit is electrically connected with the second input end of the trigger, and the output end of the trigger outputs the output pulse signal.
3. The ferroelectric capacitor based programmable double edge delay device of claim 2 wherein the first combinational logic circuit comprises a first and gate, wherein a first input of the first and gate is electrically connected to an output of the first pulse shaping circuit, a second input of the first and gate is electrically connected to a gate of a second fet in the rising edge delay circuit, and an output of the first and gate is electrically connected to a first input of the flip-flop.
4. The ferroelectric capacitor based programmable double edge delay device of claim 2, wherein the second combinational logic circuit comprises a first not gate and a second and gate, wherein a first input terminal of the second and gate is electrically connected to an output terminal of the second pulse shaping circuit, and a second input terminal of the first and gate is electrically connected to a gate of a second fet in the falling edge delay circuit for receiving the input signal;
the output end of the second AND gate is electrically connected with the input end of the first NOT gate, and the output end of the first NOT gate is electrically connected with the second input end of the trigger.
5. A ferroelectric capacitor based programmable double sided delay device as in claim 2, wherein the first pulse shaping circuit and the second pulse shaping circuit each employ schmitt trigger.
6. The ferroelectric capacitor based programmable double edge delay device of claim 2 wherein said flip-flop is an asynchronous 0-set 1D flip-flop.
7. The ferroelectric capacitor-based programmable double-sided delay device of claim 1, further comprising: and the input end of the first buffer is used for receiving the input signal, and the output end of the first buffer is electrically connected with the input ends of the rising edge delay circuit and the falling edge delay circuit respectively.
8. The ferroelectric capacitor-based programmable double edge delay device of claim 1, wherein the input of the falling edge delay circuit is electrically connected to a second not gate, wherein the input signal is transmitted to the falling edge delay circuit via the second not gate.
9. The programmable double-sided delay device based on ferroelectric capacitors as in claim 1, wherein the output of the pulse integrating unit is further electrically connected to a second buffer for driving the output pulse signal with the second buffer.
10. The ferroelectric capacitor based programmable double edge delay device of claim 1 wherein the RC time constant of the rising edge delay circuit and the falling edge delay circuit is greater than a predetermined value for increasing the circuit response time of the rising edge delay circuit and the falling edge delay circuit such that the pulse width of the output rising edge pulse signal and falling edge pulse signal is greater than the input signal.
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