CN116938194A - Comparator circuit and relaxation oscillator - Google Patents

Comparator circuit and relaxation oscillator Download PDF

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Publication number
CN116938194A
CN116938194A CN202310665547.2A CN202310665547A CN116938194A CN 116938194 A CN116938194 A CN 116938194A CN 202310665547 A CN202310665547 A CN 202310665547A CN 116938194 A CN116938194 A CN 116938194A
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China
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circuit
voltage
transistor
signal
inverter
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Inventor
张双
刘兆哲
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SG Micro Beijing Co Ltd
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SG Micro Beijing Co Ltd
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Publication of CN116938194A publication Critical patent/CN116938194A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0231—Astable circuits
    • H03K3/02315—Stabilisation of output, e.g. using crystal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

The application relates to a comparator circuit and a relaxation oscillator. The comparator circuit includes a latch circuit, a first voltage-to-current conversion circuit, and a second voltage-to-current conversion circuit. The latch circuit comprises a first inverter and a second inverter which are connected end to end, and the first voltage-to-current conversion circuit outputs a first control current signal with the same change state as the first input signal in the process of increasing the accessed first input voltage signal; the second voltage-to-current conversion circuit outputs a second control current signal with the same change state as the second input signal in the process of increasing the accessed second input voltage signal. The first control current signal and the second control current signal are used for controlling the voltage states of the output ends of the two inverters to be simultaneously inverted so as to enable the voltage states of the first end and the second section of the latch circuit to be inverted. The turnover state of the output voltages of the two output ends of the comparator circuit is not directly influenced by the power supply voltage any more, so that the voltage sensitivity of the circuit is improved, and the output stability of the circuit is high.

Description

Comparator circuit and relaxation oscillator
Technical Field
The present application relates to the field of integrated circuits, and more particularly to a comparator circuit and a relaxation oscillator.
Background
A relaxation oscillator circuit is widely used as a common clock generation circuit in various integrated circuits. The frequency of the high-speed relaxation oscillator can reach tens megahertz or higher, the whole clock period is only tens nanoseconds (ns) or tens nanoseconds, the requirement of the high-speed relaxation oscillator circuit is hardly met by using an amplifier as a comparator, and a comparison circuit with a Latch structure is usually used for replacing the amplifier.
However, the flip time of the comparison circuit of the conventional Latch structure is affected by the power supply voltage, the larger the power supply voltage is, the larger the flip frequency of the output signal is, so that the PSR (power sensitivity ratio, voltage sensitivity) of the overall circuit is large, and the stability of the output signal is poor.
Therefore, a comparator circuit with low voltage sensitivity is needed to improve the output stability of the circuit.
Disclosure of Invention
Based on this, it is necessary to provide a comparator circuit and a relaxation oscillator which are small in voltage sensitivity and stable in output.
A comparator circuit comprising:
the latch circuit comprises a first inverter and a second inverter, wherein the input end of the first inverter is connected with the output end of the second inverter, and the output end of the first inverter is connected with the input end of the second inverter; the input end of the first inverter is a first end of the latch circuit, and the input end of the second inverter is a second end of the latch circuit;
the first voltage-to-current conversion circuit is connected with the first end of the latch circuit and is used for outputting a first control current signal with the same change state as the first input voltage signal to the first end of the latch circuit in the process of increasing the accessed first input voltage signal;
the second voltage-to-current conversion circuit is connected with the second end of the latch circuit and is used for outputting a second control current signal with the same change state as the second input voltage signal to the second end of the latch circuit in the process of increasing the accessed second input voltage signal; the first input voltage signal and the second input voltage signal are alternately increased in a preset voltage range, and the change states are opposite;
the first control current signal and the second control current signal are used for controlling the voltage states of the output ends of the first inverter and the second inverter to be simultaneously inverted so as to enable the voltage states of the first end and the second end of the latch circuit to be inverted.
In some embodiments, the voltage states of the first and second terminals of the latch circuit are flipped when the first control current signal increases to a preset maximum current value or the second control current signal increases to a preset maximum current value.
In some embodiments, the first inverter includes a first transistor and a second transistor; the grid electrode of the first transistor is connected with the grid electrode of the second transistor, the drain electrode of the first transistor is connected with the drain electrode of the second transistor, the source electrode of the first transistor is connected with a power supply, and the source electrode of the second transistor is grounded;
the common end of the connection of the grid electrode of the first transistor and the grid electrode of the second transistor is the input end of the first inverter, and the common end of the connection of the drain electrode of the first transistor and the drain electrode of the second transistor is the output end of the first inverter;
the second inverter includes a third transistor and a fourth transistor; the grid electrode of the third transistor is connected with the grid electrode of the fourth transistor, the drain electrode of the third transistor is connected with the drain electrode of the fourth transistor, the source electrode of the third transistor is connected with a power supply, and the source electrode of the fourth transistor is grounded;
the common terminal of the gate of the third transistor and the gate of the fourth transistor is an input terminal of the second inverter, and the common terminal of the drain of the third transistor and the drain of the fourth transistor is an output terminal of the second inverter.
In some embodiments, the first voltage to current conversion circuit comprises a first amplifier circuit and the second voltage to current conversion circuit comprises a second amplifier circuit;
the first amplifier circuit is used for converting the accessed first input voltage signal into the corresponding first control current signal and outputting the first control current signal to the first end of the latch circuit;
the second amplifier circuit is configured to convert the second input voltage signal into the corresponding second control current signal, and output the second control current signal to the second end of the latch circuit.
In some embodiments, the first amplifier circuit includes a first amplifying transistor; the grid of the first amplifying transistor is an input end of the first amplifier circuit and is used for being connected with the first input voltage signal; the drain electrode of the first amplifying transistor is an output end of the first amplifier circuit and is used for being connected with a first end of the latch circuit; the source electrode of the first amplifying transistor is grounded;
the second amplifier circuit includes a second amplifying transistor; the grid of the second amplifying transistor is an input end of the second amplifier circuit and is used for being connected with the second input voltage signal; the drain electrode of the second amplifying transistor is an output end of the second amplifier circuit and is used for being connected with a second end of the latch circuit; the source electrode of the second amplifying transistor is grounded.
In some embodiments, the first amplifying transistor and the second amplifying transistor are both NMOS transistors.
In some embodiments, the comparator circuit further comprises a first voltage limiting circuit and a second voltage limiting circuit; the first voltage limiting circuit is connected with the first end of the latch circuit, and the second voltage limiting circuit is connected with the second end of the latch circuit;
the first voltage limiting circuit is used for limiting the lowest voltage of the first end of the latch circuit to be higher than the ground voltage so that the first control current signal output to the latch circuit is correspondingly reduced in the process that the first input voltage signal is reduced by the first voltage-to-current conversion circuit;
the second voltage limiting circuit is configured to limit a lowest voltage at a second end of the latch circuit to be higher than a ground voltage, so that the second control current signal output to the latch circuit by the second voltage converting circuit is correspondingly reduced in a process of reducing the second input voltage signal.
In some embodiments, the first voltage limiting circuit comprises a first voltage limiting transistor, a gate and a drain of the first voltage limiting transistor are both connected with a first end of the latch circuit, and a source of the first voltage limiting transistor is connected with a power supply;
the second voltage limiting circuit comprises a second voltage limiting transistor, the grid electrode and the drain electrode of the second voltage limiting transistor are both connected with the second end of the latch circuit, and the source electrode of the second voltage limiting transistor is connected with a power supply.
In some embodiments, the first voltage limiting transistor and the second voltage limiting transistor are PMOS transistors.
A relaxation oscillator comprising: a switching circuit, a capacitor-resistor array, a digital logic circuit, and a comparator circuit as described above;
the switch circuit is used for controlling the capacitor-resistor array to output a first voltage signal and a second voltage signal to the comparator circuit according to the clock signal output by the digital logic circuit;
the voltages at the first end and the second end of the comparator circuit are turned over according to the first voltage signal and the second voltage signal, and a level signal obtained by turning over is output to the digital logic circuit;
the digital logic circuit is connected with the first end and the second end of the comparator circuit, and performs digital logic analysis according to the level signal output by the comparator circuit to obtain a corresponding clock signal.
The comparator circuit and the relaxation oscillator output a first control current signal with the same state as the change state of the first input voltage signal by the first voltage-current follower circuit in the process of increasing the first input voltage signal and decreasing the second input voltage signal; the second voltage-current follower circuit outputs a second control current signal having the same state as the second input voltage signal in the process of increasing the second input voltage signal and decreasing the first input voltage signal. The latch circuit comprises a first inverter and a second inverter which are connected end to end, wherein the input end of the first inverter is used as the first end of the latch circuit and receives a first control current signal; the input end of the second inverter is used as a second end of the latch circuit and receives a second control current signal. Thus, under the drive of the first control current signal and the second control current signal, the voltage states of the output ends of the first inverter and the second inverter are simultaneously reversed, so that the output voltage states of the two ends of the latch circuit are reversed. Because the first control current signal and the second control current signal are not directly influenced by the power supply voltage, the voltage states of the first end and the second end of the latch circuit are not directly influenced by the power supply voltage any more, so that the voltage sensitivity of the circuit is greatly improved, and the output stability of the circuit is improved.
Drawings
FIG. 1 is a block diagram of a comparator circuit in some embodiments;
FIG. 2 is a schematic diagram of a comparator circuit in some embodiments;
FIG. 3 is a schematic diagram of a comparator circuit in some embodiments;
FIG. 4 is a timing diagram of the comparator circuit of the embodiment shown in FIG. 3;
FIG. 5 is a block diagram of a comparator circuit in alternative embodiments;
FIG. 6 is a schematic diagram of a comparator circuit in alternative embodiments;
FIG. 7 is a timing diagram of the comparator circuit of the embodiment shown in FIG. 6;
FIG. 8 is a block diagram of a relaxation oscillator in some embodiments;
FIG. 9 is a schematic diagram of a circuit configuration of a relaxation oscillator in some embodiments;
FIG. 10 is a timing diagram of the relaxation oscillator in the embodiment of FIG. 9.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that the terms first, second, etc. as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the application. Both the first resistor and the second resistor are resistors, but they are not the same resistor.
It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.
It is understood that "at least one" means one or more and "a plurality" means two or more. "at least part of an element" means part or all of the element.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.
In some embodiments, as shown in fig. 1, there is provided a comparator circuit comprising: the first voltage-to-current conversion circuit 200 is connected to the first terminal ON of the latch circuit 100, and the second voltage-to-current conversion circuit 300 is connected to the second terminal OP of the latch circuit 100.
The Latch circuit 100 is a Latch circuit, which is a memory cell circuit sensitive to a pulse level, and an output signal thereof can be inverted according to a change of an input signal. Specifically, the latch circuit 100 may include a first inverter 110 and a second inverter 120, an input terminal of the first inverter 110 is connected to an output terminal of the second inverter 120, and an output terminal of the first inverter 110 is connected to an input terminal of the second inverter 120; the input terminal of the first inverter 110 is a first terminal ON of the latch circuit 100, and the input terminal of the second inverter 120 is a second terminal OP of the latch circuit.
The first voltage-to-current conversion circuit 200 is used for receiving a first input voltage signal V at an input terminal X During the increasing process, the first input voltage signal V is output X The first control current signal with the same change state is applied to the first terminal ON of the latch circuit 100. The second voltage-to-current conversion circuit 300 is used for receiving a second input voltage signal V at an input terminal Y During the increasing process, output and second input voltage signal V Y The second control current signal with the same state is changed to the second terminal OP of the latch circuit 100.
First input voltage signal V X And a second input voltage signal V Y Alternately increasing within a preset voltage range and changing in opposite states, i.e. the first input voltage signal V X When the voltage increases within the preset voltage range, the second input voltage signal V Y Decreasing within a preset voltage range; thereafter, a first input voltage signal V X Reduced at the same time as the second input voltage signal V Y Increasing, and repeatedly alternating in this way. The preset voltage range is determined according to specific situations in actual implementation, and the embodiment is not limited to this.
The first control current signal and the second control current signal are used to control the voltage states of the output terminals of the first inverter 110 and the second inverter 120 of the latch circuit 100 to be simultaneously inverted, so that the voltage states of the first terminal ON and the second terminal OP of the latch circuit 100 are inverted. In some embodiments, the voltage states of the first terminal ON and the second terminal OP of the latch circuit 100 are flipped when the first control current signal increases to the preset maximum current value, or the second control current signal increases to the preset maximum current value. The preset maximum current value is specifically set according to an actual circuit, and the size of the preset maximum current value is not limited.
It will be appreciated that the inverter may flip the phase of the input signal, with the output signal and the input signal being opposite in phase. Specifically, at the first input voltage signal V X In the increasing process, the first voltage-current follower circuit 200 outputs a corresponding increased first control current signal to the first terminal ON of the latch circuit 100 (i.e. the input terminal of the first inverter 110), thereby increasing the current path of the input terminal of the first inverter 110, so that the voltage of the input terminal of the first inverter 110 gradually decreases until the first input voltage signal V X When the maximum value is reached, the first control current signal correspondingly increases to a preset maximum current value, so that the output voltage and the input voltage of the first inverter 110 are phase-inverted, the output voltage and the input voltage of the second inverter 120 are phase-inverted, the voltage of the first terminal ON is reduced to GND, and the output voltage of the second terminal OP is inverted to the maximum voltage value.
Next, a second input voltage signal V Y Increase, first input voltage signal V X During this process, the second voltage-current follower circuit 300 outputs a corresponding increased second control current signal to the second terminal OP of the latch circuit 100 (i.e., the input terminal of the second inverter 120) until the second input voltage signal V Y When the maximum value is reached, the second control current signal reaches the preset maximum current value, so that the output voltage and the input voltage of the second inverter 120 are phase-inverted, the output voltage and the input voltage of the first inverter 110 are phase-inverted, the voltage of the first terminal ON is inverted to the maximum voltage value, and the voltage of the second terminal OP is GND. Therefore, the voltage state inversion of the first end ON and the second end OP is controlled by the first control current signal or the second control current signal ON one side, and the voltage sensitivity of the circuit is reduced.
In actual implementation, the first input voltage signal V X And a second inputVoltage signal V Y The state of the first voltage-flow follower circuit 200 and the second voltage-flow follower circuit 300 alternately follow the increased first input voltage signal V X And a second input voltage signal V Y The output voltage states of both ends of the latch circuit 100 are controlled to be inverted by outputting the first control current signal and the second control current signal which are correspondingly increased.
Based on the comparator circuit provided in the present embodiment and described above, the first input voltage signal V X Increase, second input voltage signal V Y During the reduction process, the first voltage-current follower circuit 200 outputs a voltage signal V corresponding to the first input voltage X A first control current signal having the same change state; at the second input voltage signal V Y Increase, first input voltage signal V X During the reduction process, the second voltage-current follower circuit 300 outputs a voltage signal V with the second input voltage Y And a second control current signal with the same change state. The latch circuit 100 includes a first inverter 110 and a second inverter 120 connected end to end, wherein an input terminal of the first inverter 110 is turned ON as a first terminal of the latch circuit 100, and receives a first control current signal; the input terminal of the second inverter 120 is used as the second terminal OP of the latch circuit 100 to receive the second control current signal. Thus, the voltage states of the output terminals of the first inverter 110 and the second inverter 120 are simultaneously inverted under the driving of the first control current signal and the second control current signal, so that the output voltage states of the two terminals of the latch circuit 100 are inverted. Since neither the first control current signal nor the second control current signal is directly affected by the power supply voltage VDD, the voltage states of the first terminal ON and the second terminal OP of the latch circuit 100 are no longer directly affected by the power supply voltage VDD, thereby greatly improving the voltage sensitivity of the circuit and improving the output stability of the circuit.
In some embodiments, as shown in fig. 2, the first inverter 110 includes a first transistor Mp0 and a second transistor Mn0; the gate of the first transistor Mp0 is connected to the gate of the second transistor Mn0, the drain of the first transistor Mp0 is connected to the drain of the second transistor Mn0, the source of the first transistor Mp0 is connected to the power supply VDD, and the source of the second transistor Mn0 is grounded. The common terminal of the gate of the first transistor Mp0 and the gate of the second transistor Mn0 is an input terminal of the first inverter 110, and the common terminal of the drain of the first transistor Mp0 and the drain of the second transistor Mn0 is an output terminal of the first inverter 110.
It should be noted that, in some embodiments, the second inverter 120 may have the same structure as the first inverter 110, and in embodiments of the present application, the second inverter 120 may include a third transistor Mp1 and a fourth transistor Mn1; the gate of the third transistor Mp1 is connected to the gate of the fourth transistor Mn1, the drain of the third transistor Mp1 is connected to the drain of the fourth transistor Mn1, the source of the third transistor Mp1 is connected to the power supply VDD, and the source of the fourth transistor Mn1 is grounded. The common terminal of the gate of the third transistor Mp1 and the gate of the fourth transistor Mn1 is an input terminal of the second inverter 120, and the common terminal of the drain of the third transistor Mp1 and the drain of the fourth transistor Mn1 is an output terminal of the second inverter 120.
The first transistor Mp0, the second transistor Mn0, the third transistor Mp1, and the fourth transistor Mn1 may be MOS transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-Oxide semiconductor field effect transistors) or other transistors. In each embodiment of the present application, the first transistor Mp0, the second transistor Mn0, the third transistor Mp1, and the fourth transistor Mn1 are all exemplified as MOS transistors. Further, the first transistor Mp0 and the third transistor Mp1 may be PMOS transistors, and the second transistor Mn0 and the fourth transistor Mn1 may be NMOS transistors.
In addition, in practical implementation, the circuit structures of the first inverter 110 and the second inverter 120 may be adaptively adjusted according to the specific situation, and only the corresponding functions described above need to be implemented. For convenience of explanation, each embodiment of the present application will be described by taking the structure shown in fig. 2 as an example of the first inverter 110 and the second inverter 120.
In some embodiments, the first voltage to current conversion circuit 200 comprises a first amplifier circuit; the first amplifier circuit is used for switching in a first input voltage signal V X Conversion to the corresponding firstThe control current signal and outputs a first control current signal to the first terminal ON of the latch circuit 100.
The second voltage-to-current conversion circuit 300 has the same structure as the first voltage-to-current conversion circuit 200, and the second voltage-to-current conversion circuit 300 includes a second amplifier circuit; the second amplifier circuit is used for switching in the second input voltage signal V Y Converts the second control current signal into a corresponding second control current signal, and outputs the second control current signal to the second terminal OP of the latch circuit 100.
The first amplifier circuit and the second amplifier circuit are used for converting a voltage signal into a current signal, the circuit structure of the first amplifier circuit and the second amplifier circuit is not limited, and a person skilled in the art can refer to common techniques in the art to set the first amplifier circuit and the second amplifier circuit, and only the corresponding functions, such as a common gate amplifier, a common drain amplifier, a common source amplifier and the like, need to be realized.
In some specific embodiments, referring to FIG. 3, the first amplifier circuit includes a first amplifying transistor Mn4, the gate of the first amplifying transistor Mn4 is an input terminal of the first amplifier circuit for receiving a first input voltage signal V X . The drain electrode of the first amplifying transistor Mn4 is an output end of the first amplifier circuit, and is used for connecting with the first end ON of the latch circuit 100; the source of the first amplifying transistor Mn4 is grounded.
The second amplifier circuit comprises a second amplifying transistor Mn3, wherein the grid electrode of the second amplifying transistor Mn3 is an input end of the second amplifier circuit and is used for being connected with a second input voltage signal V Y . The drain of the second amplifying transistor Mn3 is an output terminal of the second amplifier circuit, and is used for connecting to the second terminal OP of the latch circuit 100; the source of the second amplifying transistor Mn3 is grounded.
In this embodiment, the first amplifying transistor Mn4 and the second amplifying transistor Mn3 are MOS transistors, and further, the first amplifying transistor Mn4 and the second amplifying transistor Mn3 may be PMOS transistors or NMOS transistors. Illustratively, the first and second amplifying transistors Mn4 and Mn3 each employ NMOS transistors for converting the first input voltage signal Vx into the first control current signal In4 and converting the second input voltage signal V, respectively Y Conversion to a second control current signalIn3。
Referring to fig. 4, when the comparator circuit is in the enabled state, the initial voltage of the first terminal ON is the power voltage VDD, and the initial voltage of the second terminal OP is the lowest voltage GND. At the first input voltage signal V X Increase, second input voltage signal V Y In the decreasing process, the first control current signal In4 which is increased along with the first input voltage signal Vx is obtained through the first amplifying transistor Mn4, the voltage of the first end ON gradually decreases until the first control current signal In4 is increased to the maximum current value, so that the states of the first transistor MP0 and the second transistor Mn0 In the first inverter 110 are reversed, the states of the third transistor MP1 and the fourth transistor Mn1 In the second inverter 120 are reversed, and the voltage of the first end ON is decreased to the ground voltage V GND The voltage of the second terminal OP is pulled up to the maximum voltage value. Thus breaking the original Latch state and realizing the overturn of the output voltages of the two output ends OP and ON.
In this process, since the voltage of the second terminal OP is GND, the drain-source voltage V of the second amplifying transistor Mn3 DS 0, although the second input voltage signal V is switched on Y The drain current is still 0, i.e. the second control current signal In3 is zero.
At the second input voltage signal V Y Increase, first input voltage signal V X In the course of the reduction, a signal V following the second input voltage is obtained via the second amplifying transistor Mn3 Y The increased second control current signal In3 and the first control current signal In4 are zero.
In this process, as the second control current signal In3 increases, the voltage of the second terminal OP gradually decreases until the second control current signal In3 reaches the maximum current value, so that the states of the third transistor Mp1 and the fourth transistor Mn1 In the second inverter 120 are inverted, the states of the first transistor Mp0 and the second transistor Mn0 In the first inverter 110 are inverted, the voltage of the first terminal ON is inverted to the maximum voltage value, and the voltage of the second terminal OP is reduced to GND.
Whereby the first input voltage signal V X And a second input voltage signal V Y Is changed alternately to cause control of one sideThe change of the current signals In4 and In3 controls the output voltages of the two output terminals OP and ON to be inverted. Therefore, PSR of the comparator circuit is obviously improved, and output stability is higher.
Further, based on the above embodiments, as shown in fig. 5, the comparator circuit further includes a first voltage limiting circuit 400 and a second voltage limiting circuit 500; the first voltage limiting circuit 400 is connected to the first terminal ON of the latch circuit 100, and the second voltage limiting circuit 500 is connected to the second terminal OP of the latch circuit 100.
The first voltage limiting circuit 400 is used for limiting the lowest voltage of the first end ON of the latch circuit 100 to be higher than the ground voltage V GND So that the first voltage-to-current converting circuit 200 converts the first input voltage signal V X During the decreasing, the first control current signal output to the latch circuit 100 correspondingly decreases.
The second voltage limiting circuit 500 is used for limiting the lowest voltage of the second terminal OP of the latch circuit 100 to be higher than the ground voltage V GND So that the second voltage-to-current converting circuit 300 converts the second input voltage signal V Y During the decreasing, the second control current signal output to the latch circuit 100 correspondingly decreases.
It is understood that voltage limiting is to limit the voltage value within a certain range. In this embodiment, the first voltage limiting circuit 400 is used to limit the output voltage of the first terminal ON of the latch circuit 100 to be not lower than GND, and the second voltage limiting circuit 500 is used to limit the output voltage of the second terminal OP of the latch circuit 100 to be not lower than GND, so that the first input voltage V X And a second input voltage signal V Y In the process of alternating, the first control current signal and the second control current signal are also changed alternately, so that the output voltages of the two output ends OP and ON are controlled to be inverted through the current change of the first control current signal and the second control current signal. Therefore, by setting two groups of voltage limiting circuits, the flip of the latch circuit 100 is controlled by comparing the current values of two paths of control current signals, when the power supply voltage VDD changes, the flip time of the comparator is not directly affected by the power supply voltage any more, and the PSR of the circuit is greatly improved.
In practical implementation, the first voltage limiting circuit 400 and the second voltage limiting circuit 500 have the same structure, and the specific structures of the two groups of voltage limiting circuits are not limited, and only the corresponding functions are needed to be realized.
In some embodiments, as shown in fig. 6, the first voltage limiting circuit 400 includes a first voltage limiting transistor Mp4, where a gate and a drain of the first voltage limiting transistor Mp4 are both connected to the first terminal ON of the latch circuit 100, and a source of the first voltage limiting transistor Mp4 is connected to the power supply VDD.
The second voltage limiting circuit 500 includes a second voltage limiting transistor Mp3, where a gate and a drain of the second voltage limiting transistor Mp3 are both connected to the second terminal OP of the latch circuit 100, and a source of the second voltage limiting transistor Mp3 is connected to the power supply VDD.
The first voltage limiting transistor Mp4 and the second voltage limiting transistor Mp3 may be MOS transistors or other transistors, and in this embodiment, the first voltage limiting transistor Mp4 and the second voltage limiting transistor Mp3 are MOS transistors. Further, the first voltage limiting transistor Mp4 and the second voltage limiting transistor Mp3 may be PMOS transistors.
The principle of the comparator circuit will be described in detail below with reference to fig. 7, taking the specific circuit shown in fig. 6 as an example.
When the comparator circuit is in the enable state, since the first voltage limiting transistor Mp4 and the second voltage limiting transistor Mp3 are arranged, the minimum voltage of the first terminal ON and the second terminal OP is not GND but a dc operating point larger than GND, and thus the first amplifying transistor Mn4 converts the first input voltage signal V X The obtained first control current signal In4 can follow the first input voltage signal V X A change; the second amplifying transistor Mn3 converts the second input voltage signal V Y The second control current signal In3 follows the second input voltage signal V Y And (3) a change.
First input voltage signal V X A second input voltage signal V Y The intersection point with equal voltage is the intersection point of the first control current signal In4 and the second control current signal In3 with equal current, and is the first input voltage signal V X A second input voltage signal V Y From V X ＜V Y Change to V X ＞V Y At the time, the first control current signal In4 and the second control current signalNumber In3 corresponds to and also from In3>In4 changes to In3 < In4, and finally the state of Latch is broken through the change of the current magnitude, so that the output voltages of the first end ON and the second end OP are inverted.
The turnover state of the output voltage of the comparator circuit is not directly influenced by the power supply voltage any more, and when the power supply voltage changes, the turnover time of the comparator circuit is not directly influenced by the power supply voltage any more, so that the PSR of the circuit is greatly improved, and the output stability of the circuit is improved.
In some embodiments, as shown in fig. 8, there is provided a relaxation oscillator comprising: a switching circuit 810, a capacitance-resistance array 820, a comparator circuit 830, and a digital logic circuit 840.
The comparator circuit 830 may be configured with reference to the above embodiments, and the specific structure thereof will not be described herein, wherein the input terminals of the first voltage-to-current converting circuit and the second voltage-to-current converting circuit are two input terminals of the comparator circuit 830, and the first terminal and the second terminal of the latch circuit are two output terminals of the comparator circuit 830.
An input terminal of the switch circuit 810 is connected to an output terminal of the digital logic circuit 840 and an input terminal of the capacitor-resistor array 820, two output terminals of the capacitor-resistor array 820 are connected to two input terminals of the comparator circuit 830, and an output terminal of the comparator circuit 830 is connected to an input terminal of the digital logic circuit 840.
The switch circuit 810 is configured to control the capacitor-resistor array 820 to output a first voltage signal and a second voltage signal to the comparator circuit 830 according to a clock signal output from the digital logic circuit 840.
The first voltage signal and the second voltage signal are alternately increased in a preset voltage range, and the change states are opposite, and after the comparator circuit 830 receives the first voltage signal and the second voltage signal, two internal current signals respectively follow the corresponding changes of the first voltage signal and the second voltage signal, so as to control the output voltages of the two output ends to overturn. The digital logic circuit 840 performs digital logic analysis according to the output voltage signal of the comparator circuit 830, and obtains a corresponding clock signal.
A relaxation oscillator is a complex oscillator that periodically releases energy stored in a capacitor or inductor, causing the output signal waveform to change instantaneously, for example, to produce a non-sinusoidal output signal such as a square wave or triangle wave. The relaxation oscillator in the present embodiment may specifically be a high-speed relaxation oscillator or another type of relaxation oscillator.
The circuit structures of the switch circuit 810, the capacitor-resistor array 820, and the digital logic circuit 840 are not limited, and those skilled in the art can make the arrangement with reference to the conventional technology in the art, and only need to implement the corresponding functions described above.
In some embodiments, as shown in fig. 9, the switching circuit 810 includes two switch sets, each including one switch K1 and one switch K2. In one switch group, one end of the switch K1 is connected with a power supply, and the other end of the switch K1 is grounded through the switch K2. In another switch group, one end of the switch K2 is connected to a power supply, and the other end is grounded through the switch K1. Each switch K1 is controlled by one set of clock signals T1 of the receiving digital logic circuit 840 and each switch K2 is controlled by another set of clock signals T2 of the receiving digital logic circuit 840. The common terminal of the two switch groups, where the switch K1 and the switch K2 are connected, is used as two output terminals of the switch circuit 810 for connecting the capacitor-resistor array 820.
The capacitor-resistor array 820 includes a capacitor C1, a capacitor C2, a resistor R1, and a resistor R2. The first terminal of the resistor R1 is connected to one output terminal of the switch circuit 810, the second terminal of the resistor R1 is connected to the first terminal of the capacitor C1, and the second terminal of the capacitor C1 is connected to the other output terminal of the switch circuit 810. The first end of the capacitor C2 is connected with the first end of the resistor R1, the second end of the capacitor C2 is connected with the first end of the resistor R2, and the second end of the resistor R2 is connected with the second end of the capacitor C1.
Wherein the connection terminal of the resistor R1 and the capacitor C1 is used as an output terminal of the capacitor-resistor array 820 for outputting the first voltage signal V X The method comprises the steps of carrying out a first treatment on the surface of the The connection terminal of the capacitor C2 and the resistor R2 is used as the other output terminal of the capacitor-resistor array 820 to output the second voltage signal V Y 。
Specifically, the working logic of the relaxation oscillator is as follows:
1. in the case of disabling, switch K1 and switch K2 in switching circuit 810 are both open and the entire circuit is in a zero power state.
2. After enabling, initially, switch K1 is closed, switch K2 is opened, a first voltage signal V X Is pulled to a lower value (V X <GND), capacitor C1 is charged by resistor R1, first voltage signal V X Rising to a second voltage signal V Y Is pulled to a higher value (V Y >VDD). Capacitor C2 is then discharged through resistor R2, the second voltage signal V Y Descending. It can be seen that, initially, V X <V Y After which the first voltage signal V X Rising, the second voltage signal V Y Down to V X ＝V Y 、V X >V Y After a certain delay, the output voltage of the comparator circuit 830 is turned over, so that the states of the clock signals T1 and T2 output by the digital logic circuit 840 are turned over, and at the same time, the switch K2 is closed and the switch K1 is opened.
3. When the switch K2 is closed and the switch K1 is opened, the second voltage signal V Y Is pulled to a lower value (V Y <GND), then capacitor C2 is charged through resistor R2, second voltage signal V Y Rising, the first voltage signal V X Is pulled to a higher value (V X >VDD). Capacitor C1 is then discharged through resistor R1, first voltage signal V X Descending. It can be seen that V is initially X >V Y After which the first voltage signal V X Falling, the second voltage signal V Y Rising until V X ＝V Y 、V X <V Y At this time, the output of the comparator circuit 830 is inverted again, so that the states of the clock signals T1, T2 output from the digital logic circuit 840 are inverted.
4. Steps 2 and 3 are repeated, and the output voltage of the comparator circuit 830 is continuously inverted, so that a stable output clock is obtained, as shown in fig. 10.
In this embodiment, the flip time of the comparator circuit 830 is not directly affected by the power supply voltage, and the output stability is high, so that the PSR of the relaxation oscillator using the comparator circuit 830 is also improved, and the output stability is improved.
In the description of the present specification, reference to the term "some embodiments," "other embodiments," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the present application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.

Claims (10)

1. A comparator circuit, comprising:
the latch circuit comprises a first inverter and a second inverter, wherein the input end of the first inverter is connected with the output end of the second inverter, and the output end of the first inverter is connected with the input end of the second inverter; the input end of the first inverter is a first end of the latch circuit, and the input end of the second inverter is a second end of the latch circuit;
the first voltage-to-current conversion circuit is connected with the first end of the latch circuit and is used for outputting a first control current signal with the same change state as the first input voltage signal to the first end of the latch circuit in the process of increasing the accessed first input voltage signal;
the second voltage-to-current conversion circuit is connected with the second end of the latch circuit and is used for outputting a second control current signal with the same change state as the second input voltage signal to the second end of the latch circuit in the process of increasing the accessed second input voltage signal; the first input voltage signal and the second input voltage signal are alternately increased in a preset voltage range, and the change states are opposite;
the first control current signal and the second control current signal are used for controlling the voltage states of the output ends of the first inverter and the second inverter to be simultaneously inverted so as to enable the voltage states of the first end and the second end of the latch circuit to be inverted.
2. The comparator circuit of claim 1, wherein the voltage states of the first and second terminals of the latch circuit are flipped when the first control current signal increases to a preset maximum current value or the second control current signal increases to a preset maximum current value.
3. The comparator circuit of claim 1, wherein the first inverter comprises a first transistor and a second transistor; the grid electrode of the first transistor is connected with the grid electrode of the second transistor, the drain electrode of the first transistor is connected with the drain electrode of the second transistor, the source electrode of the first transistor is connected with a power supply, and the source electrode of the second transistor is grounded;
the common end of the connection of the grid electrode of the first transistor and the grid electrode of the second transistor is the input end of the first inverter, and the common end of the connection of the drain electrode of the first transistor and the drain electrode of the second transistor is the output end of the first inverter;
the second inverter includes a third transistor and a fourth transistor; the grid electrode of the third transistor is connected with the grid electrode of the fourth transistor, the drain electrode of the third transistor is connected with the drain electrode of the fourth transistor, the source electrode of the third transistor is connected with a power supply, and the source electrode of the fourth transistor is grounded;
the common terminal of the gate of the third transistor and the gate of the fourth transistor is an input terminal of the second inverter, and the common terminal of the drain of the third transistor and the drain of the fourth transistor is an output terminal of the second inverter.
4. The comparator circuit of claim 1, wherein the first voltage to current conversion circuit comprises a first amplifier circuit and the second voltage to current conversion circuit comprises a second amplifier circuit;
the first amplifier circuit is used for converting the accessed first input voltage signal into the corresponding first control current signal and outputting the first control current signal to the first end of the latch circuit;
the second amplifier circuit is configured to convert the second input voltage signal into the corresponding second control current signal, and output the second control current signal to the second end of the latch circuit.
5. The comparator circuit of claim 4, wherein the first amplifier circuit comprises a first amplifying transistor; the grid of the first amplifying transistor is an input end of the first amplifier circuit and is used for being connected with the first input voltage signal; the drain electrode of the first amplifying transistor is an output end of the first amplifier circuit and is used for being connected with a first end of the latch circuit; the source electrode of the first amplifying transistor is grounded;
the second amplifier circuit includes a second amplifying transistor; the grid of the second amplifying transistor is an input end of the second amplifier circuit and is used for being connected with the second input voltage signal; the drain electrode of the second amplifying transistor is an output end of the second amplifier circuit and is used for being connected with a second end of the latch circuit; the source electrode of the second amplifying transistor is grounded.
6. The comparator circuit of claim 5, wherein the first and second amplifying transistors are NMOS transistors.
7. The comparator circuit according to any one of claims 1-6, wherein the comparator circuit further comprises a first voltage limiting circuit and a second voltage limiting circuit; the first voltage limiting circuit is connected with the first end of the latch circuit, and the second voltage limiting circuit is connected with the second end of the latch circuit;
the first voltage limiting circuit is used for limiting the lowest voltage of the first end of the latch circuit to be higher than the ground voltage so that the first control current signal output to the latch circuit is correspondingly reduced in the process that the first input voltage signal is reduced by the first voltage-to-current conversion circuit;
the second voltage limiting circuit is configured to limit a lowest voltage at a second end of the latch circuit to be higher than a ground voltage, so that the second control current signal output to the latch circuit by the second voltage converting circuit is correspondingly reduced in a process of reducing the second input voltage signal.
8. The comparator circuit of claim 7, wherein the first voltage limiting circuit comprises a first voltage limiting transistor having a gate and a drain both connected to the first end of the latch circuit, a source connected to a power supply;
the second voltage limiting circuit comprises a second voltage limiting transistor, the grid electrode and the drain electrode of the second voltage limiting transistor are both connected with the second end of the latch circuit, and the source electrode of the second voltage limiting transistor is connected with a power supply.
9. The comparator circuit of claim 8, wherein the first voltage limiting transistor and the second voltage limiting transistor are PMOS transistors.
10. A relaxation oscillator, comprising: switching circuit, capacitive-resistive array, digital logic circuit, and comparator circuit according to any of claims 1-9;
the switch circuit is used for controlling the capacitor-resistor array to output a first voltage signal and a second voltage signal to the comparator circuit according to the clock signal output by the digital logic circuit;
the voltages at the first end and the second end of the comparator circuit are turned over according to the first voltage signal and the second voltage signal, and a level signal obtained by turning over is output to the digital logic circuit;
the digital logic circuit is connected with the first end and the second end of the comparator circuit, and performs digital logic analysis according to the level signal output by the comparator circuit to obtain a corresponding clock signal.
CN202310665547.2A 2023-06-07 2023-06-07 Comparator circuit and relaxation oscillator Pending CN116938194A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310665547.2A CN116938194A (en) 2023-06-07 2023-06-07 Comparator circuit and relaxation oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310665547.2A CN116938194A (en) 2023-06-07 2023-06-07 Comparator circuit and relaxation oscillator

Publications (1)

Publication Number Publication Date
CN116938194A true CN116938194A (en) 2023-10-24

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Family Applications (1)

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CN202310665547.2A Pending CN116938194A (en) 2023-06-07 2023-06-07 Comparator circuit and relaxation oscillator

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