CN116449111A - Narrow pulse detection and counting circuit - Google Patents
Narrow pulse detection and counting circuit Download PDFInfo
- Publication number
- CN116449111A CN116449111A CN202310219254.1A CN202310219254A CN116449111A CN 116449111 A CN116449111 A CN 116449111A CN 202310219254 A CN202310219254 A CN 202310219254A CN 116449111 A CN116449111 A CN 116449111A
- Authority
- CN
- China
- Prior art keywords
- pwm
- input
- narrow pulse
- output
- filt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 title claims abstract description 85
- 238000001914 filtration Methods 0.000 claims abstract description 9
- 239000003990 capacitor Substances 0.000 claims description 33
- 230000000630 rising effect Effects 0.000 claims description 13
- 102100038026 DNA fragmentation factor subunit alpha Human genes 0.000 claims description 11
- 101000950906 Homo sapiens DNA fragmentation factor subunit alpha Proteins 0.000 claims description 11
- 102100038023 DNA fragmentation factor subunit beta Human genes 0.000 claims description 7
- 101100277639 Homo sapiens DFFB gene Proteins 0.000 claims description 7
- 230000007306 turnover Effects 0.000 claims description 2
- 238000005070 sampling Methods 0.000 abstract description 17
- 238000000034 method Methods 0.000 abstract description 6
- 230000003111 delayed effect Effects 0.000 abstract description 2
- 238000003708 edge detection Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/023—Measuring pulse width
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
- G01R29/027—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values
- G01R29/0273—Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values the pulse characteristic being duration, i.e. width (indicating that frequency of pulses is above or below a certain limit)
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
- H03K3/0233—Bistable circuits
- H03K3/02337—Bistables with hysteresis, e.g. Schmitt trigger
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention relates to a narrow pulse detection and counting circuit, and belongs to the field of integrated circuits. The invention combines the method of analog circuit design and the method of digital circuit design, firstly uses the analog circuit to filter the narrow pulse signal, and then uses the signal before filtering the narrow pulse to make double-edge sampling to the signal after filtering the narrow pulse. The essence is that the input signal is delayed by the double edge sampling. And then performing an exclusive OR operation according to the sampling result. The double edges sample the same signal, which indicates that a narrow pulse is detected and a high level is output; otherwise, the double-edge detection result is different signals, which indicates that the detected pulse is not a narrow pulse and outputs a low level. The method does not need a high-frequency sampling clock, the detection delay also only needs the time of one narrow pulse, the detection output can be cascaded to realize the detection of a plurality of continuous narrow pulses, and the circuit is simple to realize and has extremely strong expandability. The self-defined continuous narrow pulse detection and counting can be realized by free cascading.
Description
Technical Field
The invention belongs to the field of integrated circuits, and relates to a narrow pulse detection and counting circuit.
Background
In an analog integrated circuit, the high and low levels of logic signals may represent different states and the pulse width may be used to represent different information. In an on-off keying (OOK) modulation system, different pulse widths are used to represent different information, so as to implement coded transmission of different signals.
In the capacitive isolation type digital isolation chip, a signal transmission system adopting OOK modulation and demodulation is required to be able to identify signals with different pulse widths, so as to decode different information. It is desirable to be able to detect and count the start and end times of narrow pulses, as well as the number of consecutive narrow pulses, with low delay. The transmitted information is decoded by counting the number of narrow pulses.
Conventional pulse width detection and counting circuits require a high frequency sampling clock that is at least twice as large as the signal being sampled to identify and detect the signal of the smallest pulse width transmitted. This not only increases the complexity of the circuit design, but also places certain demands on frequency. It is common practice to count the period of the sampling clock within one level state time of the sampled signal, and consider the detected pulse width as a wide pulse if the period is greater than a designed threshold; whereas a counted period smaller than the threshold value considers that a narrow pulse is detected, a detection result register circuit is also required if a continuous narrow pulse is to be detected. This approach is implemented using logic in a purely digital circuit, requiring a threshold counter, and a high frequency clock, the circuit being complex to implement.
Disclosure of Invention
Accordingly, the present invention is directed to a narrow pulse detection and counting circuit.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a narrow pulse detection and counting circuit, the circuit comprising:
an input signal pwm_input comprising narrow pulse and wide pulse information;
EN is a narrow pulse detection circuit enabling signal, the detection circuit is enabled to work when EN is in a high level, the circuit is not operated when EN is in a low level, and the counter output is cleared;
PWM_Filt_OUT is the output signal of the filter circuit;
a unit narrow pulse detection circuit, a broken line box represents a detection unit, and a narrow pulse state is checked and counted;
the narrow pulse detection output 1 and the narrow pulse detection output 2 represent the state in which the narrow pulse is detected; when a narrow pulse is detected, a high level is output, and otherwise, a low level is output;
schmitt triggers ST1 and ST2, which function to reduce the power consumption of the intermediate state generated by the filtering of the capacitor C and the resistor R;
when the initial state of the input PWM_input is low level, MN2 is started, the R end of the RS trigger is high level, the output state is determined by the S end, meanwhile MN1 is closed, INV6 charges a capacitor C1 through a resistor R1, and when the voltage of the capacitor C1 is higher than the threshold voltage of the Schmitt trigger, the S point voltage is turned down, and the PWM_filt_OUT output is turned down; the low level of the output pwm_filt_out is the delay of the low level of the input pwm_input, and the delay time is the time when the resistor R1 and the capacitor C1 are charged to the switching threshold of the schmitt trigger ST 1;
when the input PWM_input turns high, the MN1 is started, the S end is high, the output state of the RS trigger is determined by the R end, meanwhile, the MN2 is closed, the INV5 charges the capacitor C2 through the resistor R2, when the voltage of the capacitor C2 is higher than the threshold voltage of the Schmitt trigger, the R point voltage turns low PWM_filt_OUT output turns high; the high level of the output pwm_filt_out is the delay of the high level of the input pwm_input, and the delay time is the time when the resistor R2 and the capacitor C2 are charged to the switching threshold of the schmitt trigger ST 2;
when the pulse low level time of the input PWM_input is longer than the delay time generated by the resistor R1 and the capacitor C1, and the pulse high level time of the input PWM_input is longer than the delay time generated by the resistor R2 and the capacitor C2, the output PWM_filt_OUT is the delay signal of the input PWM_input, if the delay time of the high voltage and the delay time of the low level are identical, the pulse width of the PWM_filt_OUT and the pulse width of the PWM_input are identical, and the delay time is different, and the edges of the PWM_filt_OUT and the PWM_input are staggered; the rising edge of pwm_input will correspond to the low level of pwm_filt_out and the falling edge of pwm_input will correspond to the high level of pwm_filt_out; with pwm_input as a clock signal, the rising edge samples pwm_filt_out through D flip-flop DFF1, the output is low level; after passing through the inverter INV8, the falling edge of the pwm_input will sample pwm_filt_out through the D flip-flop DFF2, and output as high level; the state of the DFF1 output low is not changed, so the exclusive nor gate XNOR1 input is a different value, the output is low, indicating that no narrow pulse is detected;
when the pulse low level time of the input PWM_input is smaller than the delay time generated by the resistor R1 and the capacitor C1, and the pulse high level time of the input PWM_input is smaller than the delay time generated by the resistor R2 and the capacitor C2, the output PWM_filt_OUT is a signal after the input PWM_input filters OUT the narrow pulse, the narrow pulse time is insufficient to enable the Schmitt trigger ST1 and ST2 to turn over, and the state of the RS trigger keeps the original value and cannot be changed; during the input of the narrow pulse, the output pwm_filt_out will remain unchanged;
when the narrow pulse detection output 1 turns high, the enable is effective at the EN end of the narrow pulse detection circuit of the next stage, the second narrow pulse of the PWM_input is detected by the second detection unit, and the narrow pulse detection output 2 turns high; two successive narrow pulses are sequentially detected and counted;
when a wider pulse is transmitted after the end of the narrow pulse of pwm_input, the first unit narrow pulse detection circuit will output a low level while clearing the unit narrow pulse detection circuits of the subsequent cascade.
Optionally, when the pwm_filt_out keeps low level, the rising edge of pwm_input will correspond to the low level of pwm_filt_out, and the falling edge of pwm_input also corresponds to the low level of pwm_filt_out; with pwm_input as a clock signal, the rising edge samples pwm_filt_out through D flip-flop DFF1, the output is low level; after passing through the inverter INV8, the falling edge of pwm_input will sample pwm_filt_out through D flip-flop DFF2, and the output is also low; the input of the exclusive nor gate XNOR1 is the same value, the output is high level, which means that a narrow pulse is detected, the narrow pulse detection output 1 is high level, and the detection delay is the time of a narrow pulse width; and outputting a detection result as soon as the narrow pulse is finished.
The invention has the beneficial effects that: the invention combines the method of analog circuit design and the method of digital circuit design, firstly uses the analog circuit to filter the narrow pulse signal, and then uses the signal before filtering the narrow pulse to make double-edge sampling to the signal after filtering the narrow pulse. The essence is that the input signal is delayed by the double edge sampling. And then performing an exclusive OR operation according to the sampling result. The double edges sample the same signal, which indicates that a narrow pulse is detected and a high level is output; otherwise, the double-edge detection result is different signals, which indicates that the detected pulse is not a narrow pulse and outputs a low level. The method does not need a high-frequency sampling clock, the detection delay also only needs the time of one narrow pulse, the detection output can be cascaded to realize the detection of a plurality of continuous narrow pulses, and the circuit is simple to realize and has extremely strong expandability. The self-defined continuous narrow pulse detection and counting can be realized by free cascading.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and other advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the specification.
Drawings
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in the following preferred detail with reference to the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a narrow pulse detection and counting circuit according to the present invention;
FIG. 2 is a basic sequential logic diagram of the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the illustrations provided in the following embodiments merely illustrate the basic idea of the present invention by way of illustration, and the following embodiments and features in the embodiments may be combined with each other without conflict.
Wherein the drawings are for illustrative purposes only and are shown in schematic, non-physical, and not intended to limit the invention; for the purpose of better illustrating embodiments of the invention, certain elements of the drawings may be omitted, enlarged or reduced and do not represent the size of the actual product; it will be appreciated by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numbers in the drawings of embodiments of the invention correspond to the same or similar components; in the description of the present invention, it should be understood that, if there are terms such as "upper", "lower", "left", "right", "front", "rear", etc., that indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, it is only for convenience of describing the present invention and simplifying the description, but not for indicating or suggesting that the referred device or element must have a specific azimuth, be constructed and operated in a specific azimuth, so that the terms describing the positional relationship in the drawings are merely for exemplary illustration and should not be construed as limiting the present invention, and that the specific meaning of the above terms may be understood by those of ordinary skill in the art according to the specific circumstances.
The input signal PWM_input is subjected to high-low level filtering to filter the narrow pulse information carried by the input signal PWM_input, the filtering circuit is realized by R1 and C1 and R2 and C2, and then the PWM_filt_OUT signal is output through the RS trigger circuit. The key narrow pulse detection and counting circuit is shown in a dashed line box in fig. 1, and the implementation principle is that an input PWM_input signal is used as a double-edge sampling clock, the sampling circuit is realized by a D trigger DFF1 and a DFF2, wherein the DFF1 is used as a rising edge sampling circuit, the DFF2 is used as a falling edge sampling circuit, and the PWM_filt_OUT signal output by the filter circuit is sampled. And then the sampling output realizes the output of the detection state through the exclusive or gate, and the high level is output when the narrow pulse is detected, otherwise the low level is output. Meanwhile, the signal of the narrow pulse detection output 1 can be output as a state signal for detecting one narrow pulse, and also can be output as an enable signal EN of a second narrow pulse detection unit. The cascade expansion is realized, namely the output of the unit narrow pulse detection circuit of the previous stage can be used as the enabling of the unit narrow pulse detection circuit of the next stage, so that the detection of one narrow pulse is realized, and then the detection of the next narrow pulse is continued, thereby realizing continuous detection and counting. The narrow pulse detection circuit can be infinitely extended to realize infinite continuous narrow pulse detection and counting. Meanwhile, only the first narrow pulse detection unit does not detect the continuous state of the narrow pulse, the chain reaction is triggered, all the cascaded detection units are cleared, and the aim of synchronously clearing the counter is fulfilled. In addition, the exclusive-or gate requires different output signals to be low level, so that when no narrow pulse is detected in the initial state, the initial states of two edge sampling D flip-flops are different, that is, one D flip-flop outputs high level initially, and one D flip-flop outputs low level initially, for example, the next time, so that the initial state output is correct.
Specific narrow pulse detection and counting circuits are shown in fig. 1, and include: MN1, MN2, INV 1-9, R1, R2, C1, C2, ST1, ST2, NAND1, NAND2, DFF 1-DFF 4, XNOR1, XNOR2.
As shown in fig. 1, pwm_input in the circuit is an input signal, and includes narrow pulse and wide pulse information, specifically shown in fig. 2. EN in fig. 1 is a narrow pulse detection circuit enable signal, the detection circuit is enabled to operate when EN is high level, the circuit is not operated when EN is low level, and the counter output is cleared. Pwm_filt_out in fig. 1 is a filter circuit output signal, and specifically shown in fig. 2. The circuit within the dashed box in fig. 1 represents a unit narrow pulse detection circuit, and one dashed box represents one detection unit, and one narrow pulse state can be checked and counted. The present example shows only two detection units, and the number of cascaded units can be customized according to the requirement. The narrow pulse detection output 1 and the narrow pulse detection output 2 represent the state in which the narrow pulse is detected. When a narrow pulse is detected, a high level is output, and conversely, a low level is output. ST1 and ST2 in fig. 1 are schmitt triggers that function to reduce the power consumption of the intermediate states generated by the filtering of the capacitor C and the resistor R.
When the initial state of the input PWM_input is low level, MN2 is started, the R end of the RS trigger is high level, the output state is determined by the S end, meanwhile MN1 is closed, INV6 charges a capacitor C1 through a resistor R1, when the voltage of the capacitor C1 is higher than the threshold voltage of the Schmitt trigger, the S point voltage is turned down, and the PWM_filt_OUT output is turned down. The low level of the output pwm_filt_out is then the delay of the low level of the input pwm_input, and the delay time is the time for the resistor R1 and the capacitor C1 to charge to the switching threshold of the schmitt trigger ST 1.
When the input PWM_input turns high, MN1 is turned on, S end is high level, the output state of the RS trigger is determined by R end, meanwhile MN2 is turned off, INV5 charges capacitor C2 through resistor R2, when the voltage of capacitor C2 is higher than the threshold voltage of the Schmitt trigger, the voltage of R point turns low PWM_filt_OUT output turns high. The high level of the output pwm_filt_out is then the delay of the high level of the input pwm_input, and the delay time is the time for the resistor R2 and the capacitor C2 to charge to the switching threshold of the schmitt trigger ST 2.
When the pulse low level time of the input PWM_input is longer than the delay time generated by the resistor R1 and the capacitor C1, and the pulse high level time of the input PWM_input is longer than the delay time generated by the resistor R2 and the capacitor C2, the output PWM_filt_OUT is the delay signal of the input PWM_input, if the delay time of the high voltage and the delay time of the low level are identical, the pulse width of the PWM_filt_OUT and the pulse width of the PWM_input are identical, and the delay time is different, and the edges are staggered. The rising edge of pwm_input will correspond to the low level of pwm_filt_out and the falling edge of pwm_input will correspond to the high level of pwm_filt_out. Then, with pwm_input as a clock signal, the rising edge samples pwm_filt_out through D flip-flop DFF1, and the output is low. After passing through the inverter INV8, the falling edge of pwm_input will be output as high level by sampling pwm_filt_out through D flip-flop DFF 2. And the state of the DFF1 output low is not changed, so the exclusive nor gate XNOR1 input is a different value, and the output is low. That means that no narrow pulse is detected.
When the pulse low level time of the input pwm_input is smaller than the delay time generated by the resistor R1 and the capacitor C1, and the pulse high level time of the input pwm_input is smaller than the delay time generated by the resistor R2 and the capacitor C2, the output pwm_filt_out is the signal after the input pwm_input filters OUT the narrow pulse, because the narrow pulse time is insufficient to cause the schmitt trigger ST1 and ST2 to flip, the state of the RS trigger will remain the original value and will not change. The output pwm_filt_out will then remain unchanged during the input of the narrow pulse. Taking the example that pwm_filt_out remains low, (because the same holds high), the rising edge of pwm_input will correspond to the low level of pwm_filt_out, as will the falling edge of pwm_input. Then, with pwm_input as a clock signal, the rising edge samples pwm_filt_out through D flip-flop DFF1, and the output is low. After passing through the inverter INV8, the falling edge of pwm_input will sample pwm_filt_out through D flip-flop DFF2, and the output is also low. The exclusive nor gate XNOR1 input is then the same value and the output is high. That is, the detection of a narrow pulse, the detection output 1 of the narrow pulse being high, the detection delay being the time of a narrow pulse width. Therefore, the detection delay is extremely low, and the detection result can be output immediately after the narrow pulse is ended.
When the narrow pulse detection output 1 turns high, the enable is effective at the EN end of the narrow pulse detection circuit of the next stage, the second narrow pulse of the PWM_input is detected by the second detection unit, and the narrow pulse detection output 2 turns high. Two successive narrow pulses can be detected and counted in sequence.
When a wider pulse is transmitted after the end of the narrow pulse of pwm_input, the first unit narrow pulse detection circuit will output a low level while clearing the unit narrow pulse detection circuits of the subsequent cascade.
The analysis of the narrow pulse detection and counting circuit can show that the narrow pulse detection circuit provided by the invention has the advantages of simple implementation principle, extremely short detection delay and strong expandability, and can realize the functions of continuous narrow pulse detection and counting and automatic synchronous zero clearing.
Finally, it is noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the present invention, which is intended to be covered by the claims of the present invention.
Claims (2)
1. A narrow pulse detection and counting circuit, characterized by: the circuit comprises:
an input signal pwm_input comprising narrow pulse and wide pulse information;
EN is a narrow pulse detection circuit enabling signal, the detection circuit is enabled to work when EN is in a high level, the circuit is not operated when EN is in a low level, and the counter output is cleared;
PWM_Filt_OUT is the output signal of the filter circuit;
a unit narrow pulse detection circuit, a broken line box represents a detection unit, and a narrow pulse state is checked and counted;
the narrow pulse detection output 1 and the narrow pulse detection output 2 represent the state in which the narrow pulse is detected; when a narrow pulse is detected, a high level is output, and otherwise, a low level is output;
schmitt triggers ST1 and ST2, which function to reduce the power consumption of the intermediate state generated by the filtering of the capacitor C and the resistor R;
when the initial state of the input PWM_input is low level, MN2 is started, the R end of the RS trigger is high level, the output state is determined by the S end, meanwhile MN1 is closed, INV6 charges a capacitor C1 through a resistor R1, and when the voltage of the capacitor C1 is higher than the threshold voltage of the Schmitt trigger, the S point voltage is turned down, and the PWM_filt_OUT output is turned down; the low level of the output pwm_filt_out is the delay of the low level of the input pwm_input, and the delay time is the time when the resistor R1 and the capacitor C1 are charged to the switching threshold of the schmitt trigger ST 1;
when the input PWM_input turns high, the MN1 is started, the S end is high, the output state of the RS trigger is determined by the R end, meanwhile, the MN2 is closed, the INV5 charges the capacitor C2 through the resistor R2, when the voltage of the capacitor C2 is higher than the threshold voltage of the Schmitt trigger, the R point voltage turns low PWM_filt_OUT output turns high; the high level of the output pwm_filt_out is the delay of the high level of the input pwm_input, and the delay time is the time when the resistor R2 and the capacitor C2 are charged to the switching threshold of the schmitt trigger ST 2;
when the pulse low level time of the input PWM_input is longer than the delay time generated by the resistor R1 and the capacitor C1, and the pulse high level time of the input PWM_input is longer than the delay time generated by the resistor R2 and the capacitor C2, the output PWM_filt_OUT is the delay signal of the input PWM_input, if the delay time of the high voltage and the delay time of the low level are identical, the pulse width of the PWM_filt_OUT and the pulse width of the PWM_input are identical, and the delay time is different, and the edges of the PWM_filt_OUT and the PWM_input are staggered; the rising edge of pwm_input will correspond to the low level of pwm_filt_out and the falling edge of pwm_input will correspond to the high level of pwm_filt_out; with pwm_input as a clock signal, the rising edge samples pwm_filt_out through D flip-flop DFF1, the output is low level; after passing through the inverter INV8, the falling edge of the pwm_input will sample pwm_filt_out through the D flip-flop DFF2, and output as high level; the state of the DFF1 output low is not changed, so the exclusive nor gate XNOR1 input is a different value, the output is low, indicating that no narrow pulse is detected;
when the pulse low level time of the input PWM_input is smaller than the delay time generated by the resistor R1 and the capacitor C1, and the pulse high level time of the input PWM_input is smaller than the delay time generated by the resistor R2 and the capacitor C2, the output PWM_filt_OUT is a signal after the input PWM_input filters OUT the narrow pulse, the narrow pulse time is insufficient to enable the Schmitt trigger ST1 and ST2 to turn over, and the state of the RS trigger keeps the original value and cannot be changed; during the input of the narrow pulse, the output pwm_filt_out will remain unchanged;
when the narrow pulse detection output 1 turns high, the enable is effective at the EN end of the narrow pulse detection circuit of the next stage, the second narrow pulse of the PWM_input is detected by the second detection unit, and the narrow pulse detection output 2 turns high; two successive narrow pulses are sequentially detected and counted;
when a wider pulse is transmitted after the end of the narrow pulse of pwm_input, the first unit narrow pulse detection circuit will output a low level while clearing the unit narrow pulse detection circuits of the subsequent cascade.
2. The narrow pulse detection and counting circuit of claim 1, wherein: when the PWM_Filt_OUT keeps low level, the rising edge of the PWM_input corresponds to the low level of the PWM_Filt_OUT, and the falling edge of the PWM_input also corresponds to the low level of the PWM_Filt_OUT; with pwm_input as a clock signal, the rising edge samples pwm_filt_out through D flip-flop DFF1, the output is low level; after passing through the inverter INV8, the falling edge of pwm_input will sample pwm_filt_out through D flip-flop DFF2, and the output is also low; the input of the exclusive nor gate XNOR1 is the same value, the output is high level, which means that a narrow pulse is detected, the narrow pulse detection output 1 is high level, and the detection delay is the time of a narrow pulse width; and outputting a detection result as soon as the narrow pulse is finished.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310219254.1A CN116449111A (en) | 2023-03-08 | 2023-03-08 | Narrow pulse detection and counting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310219254.1A CN116449111A (en) | 2023-03-08 | 2023-03-08 | Narrow pulse detection and counting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116449111A true CN116449111A (en) | 2023-07-18 |
Family
ID=87119147
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310219254.1A Pending CN116449111A (en) | 2023-03-08 | 2023-03-08 | Narrow pulse detection and counting circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116449111A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117294283A (en) * | 2023-11-23 | 2023-12-26 | 晶铁半导体技术(广东)有限公司 | Programmable double-side delay device based on ferroelectric capacitor |
-
2023
- 2023-03-08 CN CN202310219254.1A patent/CN116449111A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117294283A (en) * | 2023-11-23 | 2023-12-26 | 晶铁半导体技术(广东)有限公司 | Programmable double-side delay device based on ferroelectric capacitor |
| CN117294283B (en) * | 2023-11-23 | 2024-03-01 | 晶铁半导体技术(广东)有限公司 | Programmable double-side delay device based on ferroelectric capacitor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102931944B (en) | Digital burr filter | |
| CN109039307B (en) | Double-edge anti-shake circuit structure | |
| CN116449111A (en) | Narrow pulse detection and counting circuit | |
| JP2009545262A (en) | Pulse counter with clock edge recovery | |
| KR100232017B1 (en) | Up/down conversion counter | |
| CN212622809U (en) | Detection circuit | |
| CN107112985A (en) | A kind of system and method for detecting dropout | |
| US6414540B2 (en) | Input filter stage for a data stream, and method for filtering a data stream | |
| CN103208980A (en) | Window voltage comparison device | |
| CN117554703A (en) | Short pulse detection device and signal transmission system | |
| US6981204B2 (en) | Programmable glitch filter for an asynchronous data communication interface | |
| CN109635355B (en) | GPIO-oriented frequency-adjustable filter circuit | |
| US7420398B1 (en) | Pulse extension circuits for extending pulse signals | |
| US7071738B1 (en) | Glitchless clock selection circuit using phase detection switching | |
| CN106953630B (en) | High-speed pulse signal counting device and method for mercury ion microwave frequency standard | |
| CN113904655B (en) | Filter circuit and medical 3D endoscope | |
| JP2023509036A (en) | Detection circuit and detection method | |
| CN211826248U (en) | Pulse detection circuit and equipment for detecting pulse signals | |
| US4924484A (en) | High speed digital counter | |
| CN114513167B (en) | Communication module and battery management system | |
| US6931075B2 (en) | Event detection with a digital processor | |
| CN112824910A (en) | Pulse detection circuit and pulse detection method | |
| KR0152346B1 (en) | Clock switching circuit | |
| CN209787137U (en) | Logic control circuit and radio frequency communication device | |
| CN108923769B (en) | Digital filter circuit and filtering method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |