CN115603714A

CN115603714A - Pulse delay circuit

Info

Publication number: CN115603714A
Application number: CN202211194108.XA
Authority: CN
Inventors: 轩昂
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2022-09-28
Filing date: 2022-09-28
Publication date: 2023-01-13

Abstract

Embodiments of the present disclosure provide a pulse delay circuit. The pulse delay circuit includes: the signal recovery circuit comprises a signal receiving circuit, a rising edge acquisition circuit, a falling edge acquisition circuit and a signal restoring circuit, wherein the signal receiving circuit is configured to receive an input signal; the rising edge acquisition circuit is configured to acquire the rising edge of the input signal and generate a rising edge trigger signal after a preset delay; the falling edge acquisition circuit is configured to acquire the falling edge of the input signal and generate a falling edge trigger signal after a preset delay; the signal restoring circuit is configured to restore the input signal through the first trigger according to the rising edge trigger signal generated by the rising edge acquisition circuit and the falling edge trigger signal generated by the falling edge acquisition circuit to obtain an output signal, wherein the output signal is a signal obtained after the input signal is subjected to a preset time delay. The problems that the short pulse delay is filtered by the conventional delay mode, or the flexibility is low, the number of stages is too many, and the area of a chip is wasted are solved.

Description

Pulse delay circuit

Technical Field

The disclosed embodiments relate to the field of integrated circuit technology, and in particular, to a pulse delay circuit.

Background

In circuit design, an input signal is required to be delayed for a certain time and then transmitted to a logic unit for processing, but the input signal is sometimes a pulse with a short period, and if a common RC delay circuit is adopted to delay the input signal, the problem of short pulse filtering may occur. Referring to fig. 1, a conventional RC delay circuit 100 includes a resistor 101, a capacitor 102, and a schmitt trigger 103, and the RC delay circuit 100 is used to delay an INPUT signal INPUT, and waveforms of corresponding signals during the delay are shown in fig. 2, which correspond to the INPUT signal INPUT, a voltage at a point a, and an OUTPUT signal OUTPUT from top to bottom in sequence. If the design method of the inverter chain is used for delaying the input signal, although the input signal cannot be filtered, the problems of low flexibility, too many stages, chip area waste and the like are caused. Because, once the single-stage delay of the inverter chain is fixed, the resolution and the maximum delay time are already determined, for example, when the single-stage delay of the inverter is 0.5ns, 1000 stages are needed to realize the delay of 500ns, and the number of stages is too many; although the number of stages can be reduced by increasing the delay of a single stage, for example, increasing the delay of a single stage to 2us, so that a 500us delay is achieved with only 200 stages, the resolution is 2us, i.e., pulses smaller than 2us will not be resolved.

Disclosure of Invention

Embodiments described herein provide a pulse delay circuit, in order to solve the problem that the existing delay may filter out the short pulse delay, or the flexibility is not high, the number of stages is too many, and the chip area is wasted.

According to a first aspect of the present disclosure, a pulse delay circuit is provided. The pulse delay circuit includes: the device comprises a signal receiving circuit, a rising edge acquisition circuit, a falling edge acquisition circuit and a signal restoring circuit, wherein the signal receiving circuit is configured to receive an input signal, and the input signal is a pulse signal needing time delay; the rising edge acquisition circuit is configured to acquire a rising edge of the input signal and generate a rising edge trigger signal after a preset delay; the falling edge acquisition circuit is configured to acquire a falling edge of the input signal and generate a falling edge trigger signal after a preset delay; the signal restoring circuit is configured to restore the input signal through a first trigger according to a rising edge trigger signal generated by the rising edge acquisition circuit and a falling edge trigger signal generated by the falling edge acquisition circuit to obtain an output signal, wherein the output signal is a signal of the input signal after the preset time delay.

Optionally, the signal receiving circuit includes a first and gate, where a first input end of the first and gate receives the input signal, a second input end of the first and gate receives a completion indication signal, the completion indication signal is a signal indicating whether a system in which the pulse delay circuit is located can normally operate, and output ends of the first and gate are respectively connected to the rising edge collecting circuit and the falling edge collecting circuit.

Optionally, the rising edge collecting circuit includes: the clock end of the second trigger is connected with the output end of the first AND gate, the input end of the second trigger is connected with a power supply end, the set end of the second trigger is connected with the power supply end, the reset end of the second trigger is connected with the output end of the second AND gate, and the output end of the second trigger is connected with the input end of the first delay circuit; the output end of the first delay circuit is connected with the input end of the first not gate, and the output end of the first not gate is used as the output end of the rising edge acquisition circuit to output a rising edge trigger signal; the input end of the second not gate receives a power-on logic indication signal, the output end of the second not gate is connected with the second input end of the second and gate, the first input end of the second and gate is connected with the output end of the first not gate, and the power-on logic indication signal is a signal indicating whether a system where the pulse delay circuit is located is powered on stably.

Optionally, the falling edge collecting circuit includes: the clock end of the third trigger is connected with the output end of the third NOT gate, the input end of the third NOT gate is connected with the output end of the first AND gate, the input end of the third trigger is connected with a power supply end, the set end of the third trigger is connected with the power supply end, the reset end of the third trigger is connected with the output end of the third AND gate, and the output end of the third trigger is connected with the input end of the second delay circuit; the output end of the second delay circuit is connected with the input end of the fourth not gate, and the output end of the fourth not gate is used as the output end of the falling edge acquisition circuit to output a falling edge trigger signal; an input end of the fifth not gate receives the power-on logic indication signal, an output end of the fifth not gate is connected with a second input end of the third and gate, and a first input end of the third and gate is connected with an output end of the fourth not gate.

Optionally, the signal restoring circuit includes: the first trigger and the fourth and gate, wherein a clock end of the first trigger is connected to a ground end, an input end of the first trigger is connected to the power end, a set end of the first trigger is connected to an output end of the rising edge acquisition circuit, a reset end of the first trigger is connected to an output end of the fourth and gate, and an output end of the first trigger outputs the output signal; and a first input end of the fourth AND gate is connected with the output end of the falling edge acquisition circuit, and a second input end of the fourth AND gate is connected with the power-on logic indication signal.

Optionally, the first delay circuit and the second delay circuit have the same structure, and the first delay circuit includes: the circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor and a Schmitt trigger, wherein a control electrode of the first transistor and a control electrode of the second transistor are used as input ends of the first delay circuit, a first end of the first transistor is connected with a power supply end, a second end of the first transistor is respectively connected with a first end of the second transistor, one end of the capacitor and an input end of the Schmitt trigger, and a second end of the second transistor is connected with a first end of the third transistor; a second end of the third transistor is connected with a ground terminal, and a control electrode of the third transistor is connected with a control electrode of the fourth transistor; the first end of the fourth transistor receives a preset bias current, the first end of the fourth transistor is also connected with the control electrode of the fourth transistor, and the second end of the fourth transistor is connected with a grounding end; the other end of the capacitor is connected with a grounding end, and the output end of the Schmitt trigger is used as the output end of the first delay circuit.

Optionally, the first transistor is a P-type transistor, and the second transistor, the third transistor, and the fourth transistor are N-type transistors.

Optionally, the period of the input signal is longer than the time period from when the output signal of the second flip-flop changes from low to high to when the output signal of the second delay circuit changes from high to low.

Optionally, the second flip-flop and the third flip-flop are rising edge triggered flip-flops.

Optionally, the set end and the reset end of the second flip-flop are not zero at the same time, and the set end and the reset end of the third flip-flop are not zero at the same time.

According to the pulse delay circuit, the rising edge of the input signal is collected through the rising edge collecting circuit, the falling edge of the input signal is collected through the falling edge collecting circuit, the input signal is finally reserved after the preset delay through the signal restoring circuit, the input signal can be completely reserved after the delay regardless of the length of the input signal pulse, and compared with the existing common RC delay circuit, the problem that the input signal with short pulse is filtered cannot occur. In addition, compared with a time delay mode of an inverter chain, the rising edge and the falling edge of the input signal only need to be collected and are irrelevant to the width of the pulse, so that the circuit stage number cannot be increased along with the increase of the pulse width, and the problems of low flexibility, too many stage numbers and chip area waste do not exist.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, it being understood that the drawings described below relate only to some embodiments of the present disclosure, and not to limit the present disclosure, wherein:

FIG. 1 is an exemplary circuit diagram of a conventional RC delay circuit pulse delay circuit;

FIG. 2 is a waveform diagram of the corresponding correlation signals of the circuit diagram of FIG. 1;

FIG. 3 is a schematic block diagram of a pulse delay circuit according to an embodiment of the present disclosure;

FIG. 4 is an exemplary circuit diagram of a pulse delay circuit according to an embodiment of the present disclosure;

FIG. 5 is an exemplary circuit diagram of a first delay circuit in the embodiment shown in FIG. 4;

fig. 6 is a waveform diagram of relevant signals corresponding to the pulse delay circuit in the embodiment shown in fig. 4 and 5.

The elements in the drawings are schematic and not drawn to scale.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below in detail and completely with reference to the accompanying drawings. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are also within the scope of protection of the disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate components.

In all embodiments of the present disclosure, since the source and the drain of a Metal Oxide Semiconductor (MOS) transistor are symmetric and the on-currents between the source and the drain of an N-type transistor and a P-type transistor are opposite in direction, in embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as a control electrode, and the remaining two terminals of the MOS transistor are referred to as a first electrode and a second electrode, respectively. The transistors employed in the embodiments of the present disclosure are mainly switching transistors. For convenience of general description, a base of a Bipolar Junction Transistor (BJT) is referred to as a control electrode, an emitter of the BJT is referred to as a first electrode, and a collector of the BJT is referred to as a second electrode. In addition, terms such as "first" and "second" are only used to distinguish one element (or part of an element) from another element (or another part of an element).

Fig. 3 shows a schematic block diagram of a pulse delay circuit 200 according to an embodiment of the present disclosure. As shown in fig. 3, the pulse delay circuit 200 may include: the signal receiving circuit 210, the rising edge collecting circuit 220, the falling edge collecting circuit 230, and the signal restoring circuit 240.

The signal receiving circuit 210 is configured to receive an INPUT signal INPUT, where the INPUT signal INPUT is a pulse signal requiring a delay, and the INPUT signal INPUT may be a short pulse signal or a long pulse signal. The signal receiving circuit 210 is connected to the rising edge collecting circuit 220 and the falling edge collecting circuit 230, respectively, and the signal receiving circuit 210 provides the INPUT signal INPUT to the rising edge collecting circuit 220 and the falling edge collecting circuit 230, respectively, so that the INPUT signal INPUT can be collected by the signal receiving circuit, and preparation is made for reserving the INPUT signal INPUT in the following process.

The rising edge collecting circuit 220 is configured to collect a rising edge of the INPUT signal INPUT and generate a rising edge trigger signal RST1 after a preset delay. In the embodiment of the present disclosure, the rising edge collecting circuit 220 is connected to the signal receiving circuit 210 and the signal restoring circuit 240 respectively. The rising edge collecting circuit 220 is connected to the signal receiving circuit 210 to obtain the INPUT signal INPUT, and then collects the rising edge of the INPUT signal INPUT, during the collecting process, since the delayed signal of the INPUT signal INPUT is finally output, a delay process is required during the collecting process, and the delay process does not adopt a common RC delay circuit as shown in fig. 1. The INPUT signal INPUT passes through the rising edge acquisition circuit 220 to obtain a rising edge trigger signal RST1, where the rising edge trigger signal RST1 is to trigger a first flip-flop D1 in the signal restoring circuit 240 to restore the rising edge of the INPUT signal INPUT.

The falling edge collection circuit 230 is configured to collect the falling edge of the INPUT signal INPUT and generate the falling edge trigger signal RST2 after a preset delay time. In the embodiment of the present disclosure, the falling edge collecting circuit 230 is connected to the signal receiving circuit 210 and the signal restoring circuit 240, respectively. The falling edge collecting circuit 230 is connected to the signal receiving circuit 210 to obtain the INPUT signal INPUT, and then collects the falling edge of the INPUT signal INPUT, during the collecting process, since the delayed signal of the INPUT signal INPUT is finally output, a delay process is required during the collecting process, and the delay process does not adopt the conventional RC delay circuit shown in fig. 1. The INPUT signal INPUT passes through the falling edge acquisition circuit 230 to obtain a falling edge trigger signal RST2, where the falling edge trigger signal RST2 is to trigger a first flip-flop D1 in the signal restoring circuit 240 to restore the falling edge of the INPUT signal INPUT.

The signal restoring circuit 240 is configured to restore the INPUT signal INPUT through the first flip-flop D1 according to the rising edge trigger signal RST1 generated by the rising edge collecting circuit 220 and the falling edge trigger signal RST2 generated by the falling edge collecting circuit 230, so as to obtain an OUTPUT signal OUTPUT, where the OUTPUT signal OUTPUT is a signal of the INPUT signal INPUT after a preset time delay. In the embodiment of the present disclosure, the signal restoring circuit 240 is connected to the rising edge acquiring circuit 220 and the falling edge acquiring circuit 230, respectively, and triggers the first flip-flop D1 through RST1 and RST2, so as to restore the INPUT signal INPUT, and since the rising edge acquiring circuit 220 and the falling edge acquiring circuit 230 have been subjected to delay processing, the OUTPUT signal OUTPUT obtained finally is the INPUT signal INPUT after being subjected to a preset delay.

According to the pulse delay circuit of the embodiment of the present disclosure, the rising edge of the INPUT signal INPUT is collected by the rising edge collecting circuit 220, the falling edge of the INPUT signal INPUT is collected by the falling edge collecting circuit 230, and the INPUT signal INPUT is finally retained after a preset delay by the signal restoring circuit 240, and the INPUT signal INPUT can be completely retained after the delay regardless of the length of the INPUT signal INPUT pulse. In addition, compared with a time delay mode of an inverter chain, the rising edge and the falling edge of the input signal only need to be collected and are irrelevant to the width of the pulse, so that the circuit stage number cannot be increased along with the increase of the pulse width, and the problems of low flexibility, too many stage numbers and chip area waste do not exist.

Fig. 4 illustrates an exemplary circuit diagram of a pulse delay circuit 200 according to an embodiment of the present disclosure. As shown in fig. 4, the signal receiving circuit 210 includes a first and gate 211, wherein a first INPUT terminal of the first and gate 211 receives an INPUT signal INPUT, a second INPUT terminal of the first and gate 211 receives a completion indication signal START, the completion indication signal START is a signal indicating whether a system in which the pulse delay circuit 200 is located can operate normally, and output terminals of the first and gate 211 are respectively connected to the rising edge collecting circuit 220 and the falling edge collecting circuit 230. In addition, when the completion indication signal START is high, it indicates that data can be normally accepted and the system can operate normally.

The rising edge acquisition circuit 220 includes: the circuit comprises a second trigger D2, a second and gate 221, a first delay circuit 222, a first not gate 223 and a second not gate 224, wherein a clock terminal CK of the second trigger D2 is connected with an output terminal of the first and gate 211, an input terminal D of the second trigger D2 is connected with a power supply terminal VDD, a set terminal NS of the second trigger D2 is connected with the power supply terminal VDD, a reset terminal NR of the second trigger D2 is connected with an output terminal of the second and gate 221, and an output terminal Q of the second trigger D2 is connected with an input terminal of the first delay circuit 222; the output end of the first delay circuit 222 is connected to the input end of the first not gate 223, and the output end of the first not gate 223 is used as the output end of the rising edge collecting circuit 220 to output a rising edge triggering signal RST1; the input end of the second not gate 224 receives the power-on logic indication signal POR, the output end of the second not gate 224 is connected to the second input end of the second and gate 221, the first input end of the second and gate 221 is connected to the output end of the first not gate 223, and the power-on logic indication signal POR is a signal indicating whether a system in which the pulse delay circuit 200 is located is powered on stably. After the system is powered on stably, the power-on logic indicates that the signal POR is kept low. The delay of the first delay circuit 222 is set to the preset delay (i.e., the delay required by the input signal) as described above.

The falling edge acquisition circuit 230 includes: a third trigger D3, a third and gate 231, a second delay circuit 232, a third not gate 233, a fourth not gate 234, and a fifth not gate 235, wherein a clock terminal CK of the third trigger D3 is connected to an output terminal of the third not gate 233, an input terminal of the third not gate 233 is connected to an output terminal of the first and gate 211, an input terminal D of the third trigger D3 is connected to a power supply terminal VDD, a set terminal NS of the third trigger D3 is connected to the power supply terminal VDD, a reset terminal NR of the third trigger D3 is connected to an output terminal of the third and gate 231, and an output terminal Q of the third trigger D3 is connected to an input terminal of the second delay circuit 232; the output end of the second delay circuit 232 is connected to the input end of the fourth not gate 234, and the output end of the fourth not gate 234 serves as the output end of the falling edge acquisition circuit 230 to output a falling edge trigger signal RST2; an input terminal of the fifth not gate 235 receives the power-on logic indication signal POR, an output terminal of the fifth not gate 235 is connected to a second input terminal of the third and gate 231, and a first input terminal of the third and gate 231 is connected to an output terminal of the fourth not gate 234. The delay of the second delay circuit 232 is set to the preset delay (i.e., the delay required by the input signal) as described above.

The signal restoring circuit 240 includes: the circuit comprises a first trigger D1 and a fourth AND gate 241, wherein a clock terminal CK of the first trigger D1 is connected with a ground terminal GND, an input terminal D of the first trigger D1 is connected with a power terminal VDD, a set terminal NS of the first trigger D1 is connected with an OUTPUT terminal of the rising edge acquisition circuit 220, a reset terminal NR of the first trigger D1 is connected with an OUTPUT terminal of the fourth AND gate 241, and an OUTPUT terminal Q of the first trigger D1 OUTPUTs an OUTPUT signal OUTPUT; a first input terminal of the fourth and gate 241 is connected to the output terminal of the falling edge collecting circuit 230, and a second input terminal of the fourth and gate 241 is connected to the power-on logic indication signal POR.

In the example of fig. 4, the second flip-flop D2 and the third flip-flop D3 are flip-flops triggered by rising edges, the output terminal Q is set high when the set terminal NS is low, the output terminal Q is cleared when the reset terminal NR is low, the set terminal NS and the reset terminal NR of the second flip-flop D2 are not allowed to be zero at the same time, and the set terminal NS and the reset terminal NR of the third flip-flop D3 are also not allowed to be zero at the same time. Those skilled in the art will appreciate that variations to the circuit shown in fig. 4 based on the above inventive concepts are intended to fall within the scope of the present disclosure.

The operation of the pulse delay circuit 200 according to an embodiment of the present disclosure is described below in conjunction with the exemplary diagram of fig. 4.

1. The completion indication signal START is 1, the power-up logic indication signal POR is 0, and the circuit has entered the normal operation mode. The signal Q2 output by the output end Q of the second flip-flop D2 and the signal Q3 output by the output end Q of the third flip-flop D3 are 0 at this time due to the power-on reset.

2. When the INPUT signal INPUT changes from low to high, the clock terminal CK of the second flip-flop D2 detects a rising signal edge, and therefore Q2 changes from low to high. At this time, Q2 starts to generate a delay of a preset delay by the first delay circuit 222, and at the end of the delay, the output signal Q2_ delay of the first delay circuit 222 also changes from low to high. The rising edge trigger signal RST1 is obtained through the first not gate 223, RST1 is low at this time, and the reset terminal NR of the second flip-flop D2 is controlled immediately after RST1 to clear Q2. RST1 then goes high.

3. When Q2 goes low, Q2_ delay goes high, RST1 goes low, the first flip-flop D1 is set high by RST1. The OUTPUT signal OUTPUT is changed from low to high and is maintained until the clear signal arrives.

4. When the INPUT signal INPUT changes from high to low, the clock terminal CK of the third flip-flop D3 detects a rising signal edge, and thus Q3 changes from low to high. At this time, Q3 starts to generate a delay of a preset delay by the second delay circuit 232, and at the end of the delay, the output signal Q3_ delay of the second delay circuit 232 also changes from low to high. After passing through the fourth not-gate 234, the falling edge trigger signal RST2 is obtained, RST2 is low, and then RST2 controls the reset terminal NR of the third flip-flop D3 to zero Q3, and RST2 goes high.

5. When Q3 goes low, Q3_ delay goes high, and RST2 goes low, the first flip-flop D1 is cleared by RST2, and the OUTPUT signal OUTPUT goes high to low.

It should be further noted that, in fig. 4, both the first delay circuit 222 and the second delay circuit 232 are delayed in rising and not delayed in falling. The first delay circuit 222 and the second delay circuit 232 have the same structure, and a specific circuit structure will be described by taking the first delay circuit 222 as an example. As shown in fig. 5, the first delay circuit 222 includes: a first transistor PM1, a second transistor NM1, a third transistor NM2, a fourth transistor NM3, a capacitor C, and a schmitt trigger 2221, wherein a control electrode of the first transistor PM1 and a control electrode of the second transistor NM1 are used as an input terminal In of the first delay circuit 222, a first end of the first transistor PM1 is connected to a power supply terminal VDD, a second end of the first transistor PM1 is respectively connected to a first end of the second transistor NM1, one end of the capacitor C, and an input terminal of the schmitt trigger 2221, and a second end of the second transistor NM1 is connected to a first end of the third transistor NM 2; a second end of the third transistor NM2 is connected to a ground terminal, and a control electrode of the third transistor NM2 is connected to a control electrode of the fourth transistor NM 3; a first end of the fourth transistor NM3 receives a preset bias current Ibias, the first end of the fourth transistor NM3 is further connected to a control electrode of the fourth transistor NM3, and a second end of the fourth transistor NM3 is connected to a ground terminal; the other end of the capacitor C is connected to the ground, and the output end of the schmitt trigger 2221 serves as the output end OUT of the first delay circuit 222. In fig. 5, the first transistor PM1 is a P-type transistor, and the second transistor NM1, the third transistor NM2, and the fourth transistor NM3 are N-type transistors.

The following describes the operation of the first delay circuit 222 and the second delay circuit 232 with reference to the exemplary diagram of fig. 5, when the input terminal IN is changed from low to high, the second transistor NM1 is turned on, the first transistor PM1 is turned off, the charge on the capacitor C leaks to the ground through the NM1 and the third transistor NM2, but since the current of NM2 is limited by the preset bias current Ibias, the voltage at the point a is decreased slowly, and correspondingly, the potential of the output terminal OUT is increased slowly. When the input terminal IN goes from high to low, NM1 is turned off, PM1 is turned on, and the power supply terminal VDD charges the capacitor C through PM 1. Without the limitation of the current source, the voltage at the point A rises rapidly, and correspondingly, the OUT potential rises rapidly.

To further illustrate the effect of the pulse delay circuit according to the embodiment of the disclosure, as shown in fig. 6, a waveform diagram of the correlation signal obtained by delaying one short pulse by 700ns by applying the circuit example of fig. 4 and 5 is shown, and in fig. 6, waveforms corresponding to the INPUT signal INPUT, the signal Q2 OUTPUT from the OUTPUT terminal Q of the second flip-flop D2, the OUTPUT signal Q2_ delay (inversion of RST 1) of the first delay circuit 222, the signal Q3 OUTPUT from the OUTPUT terminal Q of the third flip-flop D3, the OUTPUT signal Q3_ delay (inversion of RST 2) of the second delay circuit 232, and the OUTPUT signal OUTPUT are sequentially shown from top to bottom, and as can be seen from fig. 6, when the INPUT signal INPUT changes from low to high, the Q2 starts to change from low to high, when the Q2 signal starts to generate one delay of 700ns by the first delay circuit 222, and when the Q2_ delay signal changes from low to zero after the delay ends, the delay signal changes from low to high to zero. The OUTPUT signal also follows the signal from low to high when Q2_ delay changes from low to high; when the INPUT changes from high to low, Q3 starts to go from low to high in response to the INPUT signal, at which time the Q3 signal starts to generate a delay of 700ns by the second delay circuit 232, and at the end of the delay, the Q3_ delay signal goes from low to high and goes to zero after undergoing a short pulse. The OUTPUT signal follows the signal from high to low as Q3_ delay changes from low to high. It can be seen that OUTPUT is shown as a signal that retains the delay of INPUT of 700ns, enabling the delay of short pulses.

In addition, description is made of 10ns (the period in which Q2_ delay or Q3_ delay is maintained high) in fig. 6 with reference to fig. 4: taking Q2_ delay as an example, after Q2_ delay goes from low to high, RST1 goes low, the output of the second and gate 221 goes low, the second flip-flop D2 is reset (cleared), Q2 goes low, the second flip-flop D2 is a rising edge flip-flop, the falling edge is fast, and after Q2 goes low, Q2_ delay goes from high to low again. 10ns is the time of the cycle described above, which can also be understood as the Reset time. In an actual circuit, the time during which Q2_ delay or Q3_ delay is maintained high is not necessarily 10ns, and is determined by the time of the above cycle in the actual circuit, but both are relatively short.

It should be noted that, because the next pulse of the INPUT signal INPUT cannot be identified during the time delay of Q2 or Q3, and therefore the second pulse can be identified after the time delay is finished, the period of the INPUT signal INPUT in the embodiment of the present disclosure is longer than the time of the delay signal, which corresponds to fig. 6, that is, the period of the INPUT signal INPUT is longer than the time period from when Q2 changes from low to high to when Q3_ delay changes from high to low, that is, "period of INPUT" > "preset time delay + pulse width of INPUT + time period of Q3_ delay is maintained high".

In summary, the pulse delay circuit 200 according to the embodiment of the disclosure can retain the short pulse signal, prevent the problem of filtering, and does not increase the circuit stages with the increase of the pulse width, so that the problems of low flexibility, too many stages, and chip area waste do not exist.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when reference is made to the singular, it is generally intended to include the plural of the corresponding term. Similarly, the words "comprise" and "include" are to be construed as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be construed as inclusive unless such interpretation is explicitly prohibited herein. Where the term "example" is used herein, particularly when it comes after a set of terms, it is merely exemplary and illustrative and should not be considered exclusive or extensive.

Further aspects and ranges of adaptability will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples herein are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

Several embodiments of the present disclosure have been described in detail above, but it is apparent that various modifications and variations can be made to the embodiments of the present disclosure by those skilled in the art without departing from the spirit and scope of the present disclosure. The scope of the disclosure is defined by the appended claims.

Claims

1. A pulse delay circuit, comprising: a signal receiving circuit, a rising edge acquisition circuit, a falling edge acquisition circuit and a signal restoring circuit,

the signal receiving circuit is configured to receive an input signal, wherein the input signal is a pulse signal needing time delay;

the rising edge acquisition circuit is configured to acquire a rising edge of the input signal and generate a rising edge trigger signal after a preset delay;

the falling edge acquisition circuit is configured to acquire a falling edge of the input signal and generate a falling edge trigger signal after a preset delay;

the signal restoring circuit is configured to restore the input signal through a first trigger according to a rising edge trigger signal generated by the rising edge acquisition circuit and a falling edge trigger signal generated by the falling edge acquisition circuit to obtain an output signal, wherein the output signal is a signal of the input signal after the preset time delay.

2. The pulse delay circuit of claim 1, wherein the signal receiving circuit comprises a first AND gate,

the first input end of the first and gate receives the input signal, the second input end of the first and gate receives a completion indication signal, the completion indication signal is a signal indicating whether a system where the pulse delay circuit is located can work normally, and the output end of the first and gate is connected with the rising edge acquisition circuit and the falling edge acquisition circuit respectively.

3. The pulse delay circuit of claim 2 wherein the rising edge acquisition circuit comprises: a second trigger, a second AND gate, a first delay circuit, a first NOT gate, a second NOT gate,

the clock end of the second trigger is connected with the output end of the first AND gate, the input end of the second trigger is connected with a power supply end, the set end of the second trigger is connected with the power supply end, the reset end of the second trigger is connected with the output end of the second AND gate, and the output end of the second trigger is connected with the input end of the first delay circuit;

the output end of the first delay circuit is connected with the input end of the first not gate, and the output end of the first not gate is used as the output end of the rising edge acquisition circuit to output a rising edge trigger signal;

the input end of the second not gate receives a power-on logic indication signal, the output end of the second not gate is connected with the second input end of the second and gate, the first input end of the second and gate is connected with the output end of the first not gate, and the power-on logic indication signal is a signal indicating whether a system where the pulse delay circuit is located is powered on stably.

4. The pulse delay circuit of claim 3 wherein the falling edge acquisition circuit comprises: a third trigger, a third AND gate, a second delay circuit, a third NOT gate, a fourth NOT gate and a fifth NOT gate,

the clock end of the third trigger is connected with the output end of the third not gate, the input end of the third not gate is connected with the output end of the first and gate, the input end of the third trigger is connected with a power supply end, the set end of the third trigger is connected with the power supply end, the reset end of the third trigger is connected with the output end of the third and gate, and the output end of the third trigger is connected with the input end of the second delay circuit;

the output end of the second delay circuit is connected with the input end of the fourth not gate, and the output end of the fourth not gate is used as the output end of the falling edge acquisition circuit to output a falling edge trigger signal;

the input end of the fifth not gate receives the power-on logic indication signal, the output end of the fifth not gate is connected with the second input end of the third and gate, and the first input end of the third and gate is connected with the output end of the fourth not gate.

5. The pulse delay circuit of claim 4, wherein the signal recovery circuit comprises: the first trigger, the fourth AND gate,

the clock end of the first trigger is connected with a ground end, the input end of the first trigger is connected with the power end, the set end of the first trigger is connected with the output end of the rising edge acquisition circuit, the reset end of the first trigger is connected with the output end of the fourth and gate, and the output end of the first trigger outputs the output signal;

and a first input end of the fourth AND gate is connected with the output end of the falling edge acquisition circuit, and a second input end of the fourth AND gate is connected with the power-on logic indication signal.

6. The pulse delay circuit of claim 5 wherein the first delay circuit and the second delay circuit are identical in construction, the first delay circuit comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor, a Schmitt trigger,

a control electrode of the first transistor and a control electrode of the second transistor are used as input ends of the first delay circuit, a first end of the first transistor is connected with a power supply end, a second end of the first transistor is respectively connected with a first end of the second transistor, one end of the capacitor and an input end of the schmitt trigger, and a second end of the second transistor is connected with a first end of the third transistor;

a second end of the third transistor is connected with a ground terminal, and a control electrode of the third transistor is connected with a control electrode of the fourth transistor;

the first end of the fourth transistor receives a preset bias current, the first end of the fourth transistor is also connected with the control electrode of the fourth transistor, and the second end of the fourth transistor is connected with the ground terminal;

the other end of the capacitor is connected with a grounding end, and the output end of the Schmitt trigger is used as the output end of the first delay circuit.

7. The pulse delay circuit according to claim 6, wherein the first transistor is a P-type transistor, and the second, third, and fourth transistors are N-type transistors.

8. The pulse delay circuit according to any one of claims 4 to 7, wherein the period of the input signal is longer than the time period from when the output signal of the second flip-flop changes from low to high to when the output signal of the second delay circuit changes from high to low.

9. The pulse delay circuit of any one of claims 4 to 7, wherein the second flip-flop and the third flip-flop are rising edge triggered flip-flops.

10. The pulse delay circuit according to any one of claims 4 to 7, wherein the set terminal and the reset terminal of the second flip-flop are not zero at the same time, and the set terminal and the reset terminal of the third flip-flop are not zero at the same time.