JPH1127121A - Power on reset circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely generate a reset pulse to an internal circuit even when the rise of power supply at the time of power supply throwing is very steep and also extremely slow in a semiconductor integrated circuit. SOLUTION: A 1st voltage detection circuit 104 detects the one that has the higher threshold voltage between a Pch transistor and an Nch transistor at the time of power supply throwing, next, a 2nd voltage detection circuit 105 detects the sum of respective threshold voltages, and the deviation of 1st and 2nd detection time is applied as a reset pulse by synthesizing respective detection signals. Thus, a reset pulse can be surely formed to any kind of rise of power supply without providing a heavy circuit such as an oscillation circuit because plural different voltage values are detected in the rise of power supply voltage and the deviation of the detection time is directly applied or is adjusted to be applied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a power-on reset circuit.

[0002]

2. Description of the Related Art Conventionally, a power-on reset circuit for resetting an internal circuit when power is turned on in a semiconductor integrated circuit has been widely used. Especially microcontrollers,
If a reset is not applied to the internal circuit such as a real-time clock or a control IC when the power is turned on, there is a case where a malfunction occurs after that, leading to a serious accident, and the power-on reset circuit is considered to be a very important circuit part. However, the method of turning on the power varies greatly depending on the device, and it has been difficult to configure a circuit that reliably generates a reset pulse even when the power is turned on. Here, the circuit configuration most commonly used in the past will be described.

FIG. 7A shows an example of a conventional power-on reset circuit. This power-on reset circuit includes an inverter (70) in which a resistor (704) and a capacitor (705) are connected in series and inverts the output at the connection point.
6). The power supply voltage 707 applied to both ends of the resistor and the capacitor changes rapidly (when the power is turned on) to charge the capacitor 705, and the node 701 gradually rises due to the time constant of the resistor 704 and the capacitor 705. The reset pulse is generated by shaping the waveform by the inverter 706. FIG. 7B shows the rising of the power supply and the potential change of the node 701, the output node 702 of the inverter 706, and the waveform 7 of the rising of the power supply.
03 is shown. 4 is a timing chart in which the horizontal axis represents time and the vertical axis represents potential. The reference numerals use the same waveforms as those of the node in FIG. A waveform 701 is a basic charging waveform of the CR circuit, and is represented by equation (1).

[0004]

(Equation 1)

If the logic Vth of the waveform shaping inverter is V1, the waveform of 702 becomes V1.
Since it is inverted when it reaches 1, the width of the reset pulse is the time tT from power-on to inversion. In equation (1), when V1 is substituted for V and solved, it is represented by equation 2. From this equation, the width of the reset pulse can be designed by C and R.

[0006]

(Equation 2)

Here, considering the required width of the reset pulse, it is generally preferable that the CPU has a period of 5 or 6 clock cycles of its basic clock.
In addition, it is considered that at least several ns to several us are required for the control circuit, even in consideration of recent low voltage operation.
Here, in order to obtain a pulse width of 1 us, V1 is set to half of the power supply voltage, and the value of the capacitor that can be integrated into IC is set to 10p.
If the value of F is appropriate, the resistance is about 150 Kohm, which is a value that can be easily produced in IC design. From this viewpoint, the conventional power-on reset circuit is often used in ICs.

When the power supply rises very rapidly, the conventional power-on reset circuit operates according to the design as discussed above. On the other hand, if you start up very slowly, you will have problems. Moreover, the problem is fatal in that the power-on reset circuit does not work at all. This will be described with reference to FIG. FIG. 8 shows a change in the potential of each node when the power supply rises slowly in the conventional power-on reset circuit. Here, reference numeral 803 denotes a change in power supply voltage, and reference numeral 801 denotes a change in FIG.
(A) shows a change in the potential of the node 701, and 802 denotes a reset pulse. When the power supply voltage changes very slowly as shown by 803, 801 shows a similar waveform with a delay of about 1 us. At this time, the rising slope of the power supply voltage is defined as V0 / ts. Here, V0 is a stable power supply voltage value, and ts is a time until it is stabilized. 7
When the potential of 01 becomes Vth of the Nch transistor of the inverter 706, the power supply voltage is obtained by adding Vth to the voltage value corresponding to the delay of the waveform 801. That is, (Vth +
(V0 / ts) × 1 us), and the change is (V0 / t)
s) × 1 us and, for example, V0 = 3v and ts = 50 us, the power supply voltage is about 0.06 with respect to the potential of the node 701.
about v higher. When the potential of the node 701 exceeds Vth of the Nch transistor, the output of the inverter 706 becomes lo
w, the waveform becomes as shown by the waveform 802. At this time, if Vth = 0.55v, the value of the power supply voltage becomes 0.6
1 v, and the reset pulse disappears while the internal circuit operates or does not operate. As described above, the smaller the inclination of the rise of the power supply voltage, the more the reset pulse cannot reset the internal circuit. Therefore, the conventional power-on reset circuit cannot guarantee reliable operation when the power supply voltage rises very slowly. Therefore, as a countermeasure, an oscillation stop detection circuit described below is often used together or substituted.

The basic concept of the oscillation stop detection circuit is as follows. When the power supply reaches the oscillatable region in an IC with a built-in oscillation circuit (usually the oscillatable voltage is higher than the operable voltage of other logic units), the capacitor connected by the analog switch controlled by the oscillation clock is changed. By successively charging, the potential of the output node is changed to distinguish between oscillation and oscillation stop. Specifically, the oscillation stop detection circuit will be described with reference to FIG. In FIG. 9, reference numerals 901 and 902 denote Nch transistors 903 and 90
7 is an inverter, and 904 and 905 are capacitors connected to the Vss side. 906 is a high pull-up resistance of 90
8 is Vss, and 909, 910, 911, and 912 are nodes. If the power supply does not reach the voltage at which oscillation is possible, the node 912 is fixed at high or low, and the switch 901 or 902 (Nch transistor) is used.
Are left off and the node at 910 is a high resistance 9
It is pulled up to 06 and becomes high. Next, when oscillation starts, the clock enters node 912 and the
The switches 1 and 902 are alternately turned on. First, when 901 is turned on, the capacitor of 904 is connected to V
The ss side is charged and the potential of 909 drops to the Vss side, and then when the 901 is turned off and the 902 is turned on, the capacitor of 905 is charged by the potential of 909 and the node of 910 drops to the Vss side. Next, 9
01 is turned on, 902 is turned off, and 901 is turned off again.
The potential of 09 and the potential of 910 decrease, and finally the potential of 910 becomes Vss. Here, since 906 has a sufficiently high resistance, it does not affect the charging in this cycle. Or clock cycle, so as not to affect
The values of the capacitors 904 and 905 and the value of the resistor 906 are designed. In this way, node 910 is hi before oscillation.
gh goes low when it becomes an oscillation state. Using this, a reset pulse can be generated. This oscillation stop detection circuit can be designed so that the dependence on the rise of the power supply is considerably eliminated, and can be used as an effective power-on reset circuit. However, this circuit is based on the premise that an oscillation circuit is built in the IC, and the built-in oscillation circuit is considered to be a chip size when an oscillation clock is not necessary, especially in the case of a power control IC. This is a major disadvantage in terms of power consumption and power consumption.

That is, when the power supply voltage rises very slowly, reliable operation cannot be guaranteed.

The need for an oscillation circuit and the like leads to an increase in cost due to an increase in chip size and a remarkable increase in current consumption.

[0012] The above disadvantages are found in the conventional power-on reset circuit and oscillation stop detection circuit.

[0013]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has as its object to detect a plurality of different voltage values at the rise of a power supply voltage in a semiconductor integrated circuit and detect the same. A method that applies the reset pulse directly or by adjusting the detection time lag, and forms a reset pulse reliably at any power supply rise without providing a heavy circuit such as an oscillation circuit. An on-reset circuit is provided.

[0014]

According to the first aspect of the present invention,
In a voltage detection circuit that detects a plurality of different voltages and a power-on reset circuit that generates a control signal based on a plurality of outputs of the voltage detection circuit, a detection value of a second voltage detection circuit is smaller than a detection value of a first voltage detection circuit. Is larger, and generates a control signal corresponding to a time difference between a time when the first voltage detection circuit detects a predetermined detection value and a time when the second voltage detection circuit detects a predetermined detection value. It is characterized by.

Therefore, according to the power-on reset circuit of the first aspect, when the power supply voltage rises with a certain slope from the time when the power is turned on, since the detection voltage of the first voltage detection circuit is smaller, it is detected earlier. The second voltage detection circuit detects a predetermined voltage with a time delay corresponding to the rising slope. By combining the two detection signals, a control signal corresponding to the time delay can be generated.

According to a second aspect of the present invention, in the first aspect, the first voltage detection circuit detects the higher one of the threshold voltage of the Pch transistor and the threshold voltage of the Nch transistor, and the second voltage detection circuit detects the threshold voltage of the Pch transistor. Threshold voltage and Nc
It is characterized in that the sum of the threshold values of the h transistors is detected.

Therefore, the Pch transistor, Nch
By detecting the higher one of the threshold voltages of both transistors and detecting the sum of both threshold voltages, the detection voltage can be set without any special process consideration. In addition, it is possible to surely reset the operation until the internal circuit starts to operate reliably.

According to a third aspect of the present invention, in the first aspect, the power supply voltage is shaped, and voltage detection is performed on the shaped output.

Therefore, when the power supply voltage rises sharply, the power supply voltage is shaped so that the width of the reset pulse becomes appropriate, and its output is detected, whereby a reliable reset pulse can be provided.

According to a fourth aspect of the present invention, in the first aspect, the first voltage detection circuit directly detects a power supply voltage, and the second voltage detection circuit detects an output obtained by shaping the power supply voltage.

Therefore, the width of the reset pulse can be made larger than in the case of the third aspect of the invention by making the first detection time earlier and the second detection time later.

According to a fifth aspect of the present invention, in the first aspect, the output of the second voltage detection circuit operates within a power supply voltage range.

Therefore, since the voltage detection circuit operates in the voltage range of the shaped waveform, it is necessary to supply a reset pulse that swings in the power supply voltage range to other circuit units. Interface to voltage range.

[0024]

Embodiments of the present invention will be described below.

(Embodiment 1) FIG. 1 shows a basic conceptual diagram of a power-on reset circuit according to a preferred embodiment 1 of the present invention. First, the basic concept of the present invention will be described with reference to FIG. In FIG. 1, 102 is Vdd, 1
03 is Vss, 104 and 105 are first and second voltage detection circuits, and 107 and 108 are output nodes thereof, respectively. A reset output circuit 106 generates a reset signal from the output of the voltage detection circuit.
It is one. In this embodiment, the detection voltage Vd1 of the first voltage detection circuit is set to the larger voltage value of Vthp of the Pch transistor or Vthn of the Nch transistor, and the detection voltage Vd2 of the second voltage detection circuit is (Vthp + Vth
n). The time when the power supply voltage reaches Vd1 is t
1, assuming that the time to reach Vd2 is t2, the pulse width tpw
Is tpw = t2-t1. For example, at a power supply voltage of 3 V considered in the description of the conventional power-on reset circuit, 50 u
s rise time, Vd1 is 0.55
Assuming that v and Vd2 are 1.1v, Vd1
T1 = 9.1 us until Vd2 is detected, and Vd2
It takes 18.2 us to detect. As a result, tpw
Is about 9 us, which is sufficient for a reset pulse. Also, when the reset pulse width is considered to be 1 us, the rise of the power supply can cope with the rise up to 3v in 5 us, and it is understood that this basic idea is sufficiently effective.

FIG. 2 is a specific circuit diagram of the first embodiment according to the present invention, and a voltage detection circuit, a reset output circuit, and the like will be described. The nodes and blocks described in FIG. 1 will be described using the same reference numerals. Here, blocks 104, 105, and 106 surrounded by dotted lines indicate first and second voltage detection circuits and reset output circuits, respectively. Also, 211
212, 213, 214, 215 are high resistance, 216.2
17, 218 and 219 are Pch transistors, 220
221, 222, 223 and 224 indicate Nch transistors, respectively. 107 ・ 108 ・ 225 ・
226 and 227 are nodes. As described above, the first voltage detection circuit 104 uses Vthp of the Pch transistor.
Alternatively, the voltage value Vd1 of the larger Vthn of the Nch transistor is detected. Here, the power supply voltage is Vd1
If it is lower than the above, the potential of each internal node is basically not determined. When the power supply voltage becomes higher than Vthn, the node 225 overcomes the high resistance 211 which is pulled up because the Nch transistor 220 is on and is low.
And the gate potential of the Pch transistor 216 is low.
Becomes Here, when the absolute value of Vthp is smaller than the absolute value of Vthn, the transistor is turned on, and the potential of the node 107 becomes high.
And Vd1 is detected. Also, if the absolute value of Vthp is V
If the absolute value of thn is larger than the absolute value of
Since 16 is off, 107 remains low. When the power supply voltage becomes larger than the absolute value of Vthp, 216 is turned on and 107 becomes high. In this way, when the power supply voltage becomes the larger of the absolute values of Vthp and Vthn, the first voltage detection circuit outputs high as the detection result. Next, the second voltage detection circuit 1
05 will be described. Pch transistor 217 and N
The circuit constituted by the channel transistor 221 is a circuit that is turned on when the voltage applied to both ends of the channel transistor 221 becomes equal to or more than (Vthp + Vthn). Therefore, when the power supply voltage is lower than Vd2, the potential of the node 226 is pulled up to the high resistance 213 to be high, and the Pch transistor 218
Is off, so node 227 is pulled down and low
And the Nch transistor 222 is turned off. Therefore, the output 108 of the second voltage detection circuit 105 is high. When the power supply voltage becomes higher than Vd2, node 22
6 becomes low, and the transistors subsequently turn on, and the output 108 of the voltage detection circuit becomes low, and outputs the detection of Vd2. In summary, if the power supply voltage is Vdd, 1) Vdd <Vd1 The internal potential is undefined 2) Vd1 <Vdd <Vd2 107 is high 108 is high 3) Vd2 <Vdd 107 is high 108 is low, and three states are considered. The output 101 of the reset output circuit is 2) low and 3) high. This state is shown in FIG. The reference numerals are the same as in FIG. In the case of this embodiment, a more gradual rise allows a more reliable reset signal to be formed, but a steeper rise results in a smaller pulse width. When the rising waveform becomes 1 us for 3v, the pulse width of the reset pulse becomes about 200 ns. Another embodiment will be described in order to avoid such a fear.

(Embodiment 2) FIG. 3 shows a basic conceptual diagram of a power-on reset circuit according to Embodiment 2 of the present invention. Reference numerals 104, 105, and 106 denote a first voltage detection circuit, a second voltage detection circuit, and a reset output circuit, respectively, which are basically the same as those in the first embodiment. Here, reference numeral 310 denotes a time constant circuit, and the difference between this conceptual diagram and the first embodiment is 310. In the first embodiment, the first and second voltage detection circuits are connected between the power supplies to directly detect the value of the power supply voltage. In the second embodiment, however, the first and second voltage detection circuits are connected between the power supplies (between 102 and 103). The first and second voltage detection circuits detect the shaped and adjusted output voltage output from the time constant circuit. That is, even if the rise of the power supply is very steep, the waveform is shaped into a sufficiently gentle waveform by the time constant circuit, and by detecting the voltage from this waveform, an operation equivalent to the case where the rise is gentle even if the rise is sharp is performed. It is what we did. FIG.
2 shows a specific circuit diagram (a) and a timing chart (b) of the second embodiment according to the present invention. The configuration and operation will now be described. Blocks 310 and 104 surrounded by dotted lines
Reference numerals 105 and 106 denote a time constant circuit, first and second voltage detection circuits, and a reset output circuit, respectively. The time constant circuit 310 includes a high resistance 410 and a capacitor 411, and their respective values are t2-t when the reset pulse width is 1 us.
Since it is expressed by 1, it becomes Expression (3) from Expression (2).

[0028]

(Equation 3)

From this, Vd1 = 0.55v, Vd2 =
Assuming 1.1 v and a capacitance of 10 pF, the pull-up resistance is about 370 kohm. Although two voltage detection circuits are connected to the load line 424, the high resistance included in the voltage detection circuit is set to several tens of ohms and has little effect on the time constant circuit. FIG. 4 (b)
And the output waveform of the time constant circuit indicated by 424 with respect to the power supply voltage having a steep rising indicated by 102. The first voltage detection circuit 104 has substantially the same configuration as that of the first embodiment and performs the same operation, but the second voltage detection circuit has a relationship between a resistor 414 and a portion formed by a Pch transistor 418 and an Nch transistor 419. Of the first embodiment. Further, since the series connection of the next resistor 415 and the Nch transistor 420 is connected between the power supply voltages 102 and 103, a waveform obtained by full swing between the power supplies is input to the reset output. Therefore, the reset output also has a waveform indicated by 101, and outputs a reset pulse having a pulse width of at least 1 us. With the configuration as in the second embodiment, a power-on reset circuit that reliably operates even when the power supply rises steeply or very slowly can be provided. .

(Embodiment 3) FIG. 5 shows a basic conceptual diagram of Embodiment 3 of the present invention. 104 and 105 are first and second voltage detection circuits, and 106 and 310 are reset output circuits and time constant circuits. In the third embodiment, the first voltage detection circuit is connected between the power supplies, and when the power supply voltage reaches the first detection voltage, a detection signal is output, and this signal activates the time constant circuit connected between the power supplies. Let it. The time constant circuit starts outputting a gentle waveform from this point. The second voltage detection circuit is connected to the output of the time constant circuit, and emits a detection signal when the voltage reaches the second detection voltage. FIG. 6 (a)
3 shows a specific circuit diagram of the third embodiment, and (b) shows a timing chart. Blocks 104 and 10 surrounded by dotted lines
Reference numerals 5, 106, and 310 denote a first voltage detection circuit, a second voltage detection circuit, a reset output circuit, and a time constant circuit, respectively. 107 ・ 627 ・ 628 ・ 629 ・ 108 ・ 101
Denotes a connection node. In particular, 101 outputs a reset signal in the same manner as in the other examples. When the power supply voltage is detected by the first voltage detection circuit, the output becomes LOW,
The Pch transistor 619 is turned on and the resistor 613 is connected to the capacitor 6
26, and its output waveform is 628 in FIG.
Becomes t1 is the detection time of the first voltage detection circuit, and the waveform of 628 from t1 starts to rise with respect to Vdd. When the voltage of the waveform 628 reaches the detection value of the second voltage detection circuit, the potential of 629 becomes high, and the potential of the node 108 becomes LOW. Resistor 615 and Nch transistor 6
Since the series connection circuit 22 is connected between the power supplies,
The signal makes a full swing between the power supplies. Therefore, the reset signal also becomes full swing and has a waveform indicated by 101. Here, considering the difference from the second embodiment, the first detection time in the second embodiment is shown in FIG.
When the width of the reset pulse in the second embodiment is t2-t1 ', the width of the reset pulse in the third embodiment is t2-t1, so that the capacitance and resistance of the time constant circuit are the same. , About twice the pulse width can be secured.

By applying the present invention as described in the three embodiments, even if the power supply rises steeply or very slowly with respect to the initial setting when the power supply of the IC is turned on, it is ensured. A reset signal can be generated to reliably initialize the system. Also provides a very suitable power-on reset circuit that does not require a large area in terms of circuit size and does not particularly require a circuit that has large disadvantages in terms of area and current consumption such as an oscillation circuit. can do.

[0032]

According to the present invention, a plurality of different voltage values are detected at the rise of the power supply voltage, and the deviation of the detection time is applied to the reset pulse directly or by adjusting it. It is possible to provide a power-on reset circuit that reliably forms a reset pulse at any rising power without providing a circuit.

[Brief description of the drawings]

FIG. 1 is a basic conceptual diagram of Embodiment 1 according to the present invention.

FIG. 2 is a circuit example and a timing chart according to the first embodiment of the present invention.

FIG. 3 is a basic conceptual diagram of Embodiment 2 according to the present invention.

FIG. 4 is a circuit example and a timing chart according to a second embodiment of the present invention.

FIG. 5 is a basic conceptual diagram of a third embodiment according to the present invention.

FIG. 6 is a circuit example and a timing chart according to a third embodiment of the present invention.

FIG. 7 is a circuit example and a timing chart of a conventional power-on reset circuit.

FIG. 8 is a timing chart in the case where the rise of the power supply is slow in the conventional example.

FIG. 9 is an example of an oscillation stop detection circuit.

[Explanation of symbols]

 Reference Signs List 101, reset pulse output 102, 103 Vdd, Vss 104, 105 first and second voltage detection circuits 106 reset output circuit 107 output node of first voltage detection circuit 108 output node of second voltage detection circuit 310 time constant circuit

Claims (5)

[Claims] A voltage detection circuit for detecting a plurality of different voltages; and a power-on reset circuit for generating a control signal based on a plurality of outputs of the voltage detection circuit. The detection value of the detection circuit is larger, and the control corresponding to the time difference between the time when the first voltage detection circuit detects the predetermined detection value and the time when the second voltage detection circuit detects the predetermined detection value. A power-on reset circuit for generating a signal. 2. The first voltage detection circuit according to claim 1, wherein
detecting the higher of the threshold voltage of the h transistor or the absolute value of the threshold voltage of the Nch transistor, and the second voltage detection circuit detecting the sum of the threshold voltage of the Pch transistor and the absolute value of the threshold value of the Nch transistor. Claim 1
A power-on reset circuit as described. 3. The power-on reset circuit according to claim 1, wherein the power supply voltage according to claim 1 is shaped, and voltage detection is performed on the shaped output. 4. The power supply voltage according to claim 1, wherein the first voltage detection circuit directly detects a power supply voltage, and the second voltage detection circuit detects an output obtained by shaping the power supply voltage. Power-on reset circuit. 5. The output of the second voltage detecting circuit according to claim 1, wherein the output operates within a power supply voltage range.
A power-on reset circuit as described.