CN117293020A - Transistor and preparation method thereof - Google Patents

Transistor and preparation method thereof Download PDF

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Publication number
CN117293020A
CN117293020A CN202311153066.XA CN202311153066A CN117293020A CN 117293020 A CN117293020 A CN 117293020A CN 202311153066 A CN202311153066 A CN 202311153066A CN 117293020 A CN117293020 A CN 117293020A
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China
Prior art keywords
layer
gate
source
gate metal
drain
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吴志浩
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HC Semitek Zhejiang Co Ltd
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HC Semitek Zhejiang Co Ltd
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Priority to CN202311153066.XA priority Critical patent/CN117293020A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The present disclosure provides a transistor and a method for manufacturing the same, which belong to the field of semiconductor devices. The method comprises the following steps: manufacturing a grid dielectric layer on the surface of the semiconductor layer; manufacturing a gate metal layer on the surface of the gate dielectric layer; manufacturing a patterned first sacrificial oxide layer on the surface of the gate metal layer, wherein the patterned first sacrificial oxide layer covers a gate region of the gate metal layer; wet etching is carried out on the gate metal layer, the area, which is not covered by the sacrificial oxide layer, in the gate metal layer is removed, and the gate area is reserved to form a gate; manufacturing a gate metal protection layer covering the gate; patterning the gate metal protection layer and the gate dielectric layer to form a source groove and a drain groove which penetrate through the gate metal protection layer and the gate dielectric layer and are connected with the semiconductor layer; and manufacturing a source electrode and a drain electrode in the source electrode groove and the drain electrode groove respectively.

Description

Transistor and preparation method thereof
Technical Field
The present disclosure relates to the field of semiconductor devices, and more particularly, to a transistor and a method of fabricating the same.
Background
The high electron mobility transistor (High Electron Mobility Transistor, HEMT) is a heterojunction field effect transistor that is widely used in various electrical appliances.
The related art provides a method for manufacturing a transistor, which comprises the steps of manufacturing a semiconductor layer, a gate dielectric layer and a gate metal layer on a substrate, performing dry etching on the gate metal layer to form a gate, etching the gate dielectric layer to form a source groove and a drain groove which penetrate through the gate dielectric layer and are connected with the semiconductor layer, and manufacturing a source and a drain in the source groove and the drain groove.
In the transistor preparation method provided by the related art, etching damage is caused to the gate dielectric layer during the gate electrode is manufactured by dry etching, so that the interface state of the gate dielectric layer is influenced, the interface state of the gate dielectric layer presents electropositivity or electronegativity, the electropositive interface state has an attraction effect on two-dimensional electron gas positioned between the channel layer and the barrier layer, the two-dimensional electron gas can move towards the gate dielectric layer, and the electronegativity interface state has a rejection effect on the two-dimensional electron gas. The concentration of two-dimensional electron gas is reduced in either the positive interface state or the negative interface state, and the device has a current collapse effect, so that the drain voltage is increased and the on-resistance of the device is increased.
Disclosure of Invention
The embodiment of the disclosure provides a transistor and a preparation method thereof, which can solve the problems of electric leakage and device resistance increase caused by etching damage of a gate dielectric layer due to dry etching of a gate. The technical scheme is as follows:
in one aspect, a method for fabricating a transistor is provided, the method comprising:
manufacturing a grid dielectric layer on the surface of the semiconductor layer;
manufacturing a gate metal layer on the surface of the gate dielectric layer;
manufacturing a patterned first sacrificial oxide layer on the surface of the gate metal layer, wherein the patterned first sacrificial oxide layer covers a gate region of the gate metal layer;
wet etching is carried out on the gate metal layer, the area, which is not covered by the sacrificial oxide layer, in the gate metal layer is removed, and the gate area is reserved to form a gate;
manufacturing a gate metal protection layer covering the gate;
patterning the gate metal protection layer and the gate dielectric layer to form a source groove and a drain groove which penetrate through the gate metal protection layer and the gate dielectric layer and are connected with the semiconductor layer;
and manufacturing a source electrode and a drain electrode in the source electrode groove and the drain electrode groove respectively.
Optionally, the manufacturing a source and a drain in the source recess and the drain recess, respectively, includes:
manufacturing a source drain metal layer, wherein the source drain metal layer covers the source groove, the drain groove, the surface of the gate metal protection layer and the surface of the first sacrificial oxide layer;
manufacturing a patterned second sacrificial oxide layer on the surface of the source drain metal layer, wherein the patterned second sacrificial oxide layer covers a source region and a drain region of the source drain metal layer;
and carrying out wet etching on the source drain metal layer, removing the uncovered area of the second sacrificial oxide layer in the source drain metal layer, and reserving the source electrode area and the drain electrode area to form the source electrode and the drain electrode.
Optionally, the patterning the gate metal protection layer and the gate dielectric layer to form a source recess and a drain recess penetrating the gate metal protection layer and the gate dielectric layer and connected to the semiconductor layer, includes:
and etching the gate metal protection layer and the gate dielectric layer by high-order dilute hydrofluoric acid DHF or a buffer oxide etchant BOE to form the source electrode groove and the drain electrode groove.
Optionally, the wet etching the gate metal layer includes:
and when the gate metal layer is a TiN layer, etching the gate metal layer by using a mixture of sulfuric acid and hydrogen peroxide or a mixture of ammonia water and hydrogen peroxide.
Optionally, the wet etching the gate metal layer includes:
and when the gate metal layer is an Al layer, etching the gate metal layer by using hydrochloric acid.
Alternatively, the process may be carried out in a single-stage,the first sacrificial oxide layer and the second sacrificial oxide layer are both made of SiO 2 One or more of SiN.
Optionally, the thicknesses of the first sacrificial oxide layer and the second sacrificial oxide layer are 1/3 to 1/2 of the thicknesses of the gate metal layer and the source drain metal layer located outside the source recess and the drain recess.
Optionally, the thickness of the gate dielectric layer is 20-30 nm.
Optionally, the semiconductor layer includes a buffer layer, a channel layer, and a barrier layer sequentially stacked on the surface of the substrate.
In another aspect, there is provided a transistor formed by a method as claimed in any one of the preceding claims.
The technical scheme provided by the embodiment of the disclosure has the beneficial effects that:
in the process of manufacturing the grid electrode, a patterned first sacrificial oxide layer is manufactured on the surface of a grid electrode metal layer, and a grid electrode area is protected by the patterned first sacrificial oxide layer, wherein the grid electrode area refers to an area in the grid electrode metal layer forming the grid electrode. Subsequently, the gate metal layer is patterned by wet etching, and the gate metal layer outside the gate region is etched away, thereby forming a gate. The wet etching is used for replacing dry etching to etch the gate metal layer, so that etching damage to the gate dielectric layer positioned below the gate metal layer when the dry etching is used for etching the gate metal layer can be avoided, the interface state of the gate dielectric layer is prevented from exhibiting positive electricity or negative electricity, the concentration of the two-dimensional electron gas is prevented from being reduced after the interface state of the gate dielectric layer is prevented from exhibiting electricity, and the current collapse effect of the device caused by the reduction of the concentration of the two-dimensional electron gas can be avoided, thereby improving the performance of the device.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a flowchart of a method for manufacturing a transistor according to an embodiment of the present disclosure;
fig. 2 is a flowchart of another method for manufacturing a transistor according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a transistor according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a transistor in a manufacturing process according to an embodiment of the disclosure;
fig. 5 is a schematic structural diagram of a transistor according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a transistor according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a transistor in a manufacturing process according to an embodiment of the disclosure;
fig. 8 is a schematic structural diagram of a transistor according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of a transistor in a manufacturing process according to an embodiment of the disclosure;
fig. 10 is a schematic structural diagram of a transistor in a manufacturing process according to an embodiment of the disclosure;
FIG. 11 is a schematic diagram of a transistor according to an embodiment of the present disclosure;
fig. 12 is a schematic structural diagram of a transistor in the manufacturing process according to an embodiment of the disclosure;
fig. 13 is a schematic structural diagram of a transistor according to an embodiment of the present disclosure.
Reference numerals
11: a buffer layer; 12: a channel layer; 13: a barrier layer; 14: a gate; 15: a drain electrode; 16: and a source electrode.
300: a substrate; 301: an AlN nucleation layer; 302: alGaN/GaN superlattice layer; 303: a GaN channel layer; 304: alGaN barrier layer.
401: a gate dielectric layer; 501: a gate metal layer; 601: a first sacrificial oxide layer; 701: a gate metal protection layer; 801: a drain groove; 802: a source recess; 901: a source/drain metal layer; 902: and a second sacrificial oxide layer.
Detailed Description
For the purposes of clarity, technical solutions and advantages of the present disclosure, the following further details the embodiments of the present disclosure with reference to the accompanying drawings.
Fig. 1 is a flowchart of a method for manufacturing a transistor according to an embodiment of the present disclosure. Referring to fig. 1, the method includes:
101. and manufacturing a gate dielectric layer on the surface of the semiconductor layer.
Illustratively, the gate dielectric layer includes a SiN layer.
Of course, the above-mentioned materials for forming the gate dielectric layer are only examples, and are not intended to limit the disclosure, and the gate dielectric layer may be made of other high dielectric constant (high K) materials in the actual manufacturing process.
102. And manufacturing a gate metal layer on the surface of the gate dielectric layer.
Wherein the gate metal layer is formed of one of TiN and Al.
Of course, the above-described material for forming the gate metal layer is only an example, and is not intended to limit the present disclosure, and the material for forming the gate metal layer in the present disclosure may be other materials, such as Ta, etc.
103. And manufacturing a patterned first sacrificial oxide layer on the surface of the gate metal layer, wherein the patterned first sacrificial oxide layer covers the gate region of the gate metal layer.
Wherein the first sacrificial oxide layer is formed of SiO 2 One or more of SiN.
The first sacrificial oxide layer formed by the material has good corrosion resistance and can protect the grid region from being corroded by liquid medicine.
Of course, the above-mentioned material of the first sacrificial oxide layer is only an example, and is not intended to limit the present disclosure, and the material forming the first sacrificial oxide layer in the present disclosure may also include other materials.
104. And carrying out wet etching on the gate metal layer, removing the uncovered area of the sacrificial oxide layer in the gate metal layer, and reserving the gate area to form a gate.
And etching the gate metal layer by using hydrochloric acid when the gate metal layer is an Al layer.
When the gate metal layer is a TiN layer, the gate metal layer is etched by using a mixture of sulfuric acid and hydrogen peroxide or a mixture of ammonia water and water.
Wherein the ratio of sulfuric acid to hydrogen peroxide or the ratio of ammonia water to hydrogen peroxide is 1:0.5-1:100.
Different etching liquid medicines are used for the grid metal layers of different materials, and the etching liquid medicines can ensure that the selection ratio is higher when wet etching is performed, namely the etching rate of the liquid medicines on the grid metal layers is faster, and the etching rate of the liquid medicines on the first sacrificial oxide layer is slow. Therefore, the protection effect of the first sacrificial oxide layer on the gate region can be better. The gate region is a region in the gate metal layer forming the gate.
Of course, the chemical liquid for wet etching is not limited to the chemical liquid, and the chemical liquid for wet etching in the present disclosure needs to have a higher selectivity ratio to the gate metal layer, that is, the etching rate to the gate metal layer is fast, and the etching rate to the sacrificial oxide layer is slow.
105. And manufacturing a gate metal protection layer covering the gate.
Wherein the gate metal protection layer comprises a SiN layer.
Of course, the material of the gate metal protection layer and the material of the gate dielectric layer may be different, which is not limited by the present disclosure. The gate metal protection layer may also be other materials.
106. And patterning the gate metal protection layer and the gate dielectric layer to form a source electrode groove and a drain electrode groove which penetrate through the gate metal protection layer and the gate dielectric layer and are connected with the semiconductor layer.
And carrying out patterning treatment on the gate dielectric layer and the gate metal protection layer by adopting wet etching.
The wet etching of the gate dielectric layer and the gate metal protective layer can avoid etching damage caused by dry etching, so that the phenomenon that the interface state of the gate dielectric layer and the gate metal protective layer presents electropositivity or electronegativity after the etching damage is generated on the gate dielectric layer and the gate metal protective layer is avoided, and further the influence on two-dimensional electron gas of a device is avoided.
107. And manufacturing a source electrode and a drain electrode in the source electrode groove and the drain electrode groove respectively.
Wherein the source electrode and the drain electrode can be TiN or Al.
Illustratively, the source and drain materials may be the same or different, which is not limiting of the present disclosure.
Of course, the source and drain materials are provided as an example of the disclosure, and the source and drain may be formed of other materials, which is not limited by the disclosure.
In the process of manufacturing the grid electrode, a patterned first sacrificial oxide layer is manufactured on the surface of a grid electrode metal layer, and a grid electrode area is protected by the patterned first sacrificial oxide layer, wherein the grid electrode area refers to an area in the grid electrode metal layer forming the grid electrode. Subsequently, the gate metal layer is patterned by wet etching, and the gate metal layer outside the gate region is etched away, thereby forming a gate. The wet etching is used for replacing dry etching to etch the gate metal layer, so that etching damage to the gate dielectric layer positioned below the gate metal layer when the dry etching is used for etching the gate metal layer can be avoided, the interface state of the gate dielectric layer is prevented from exhibiting positive electricity or negative electricity, the concentration of the two-dimensional electron gas is prevented from being reduced after the interface state of the gate dielectric layer is prevented from exhibiting electricity, and the current collapse effect of the device caused by the reduction of the concentration of the two-dimensional electron gas can be avoided, thereby improving the performance of the device.
Fig. 2 is a flowchart of another method for manufacturing a transistor according to an embodiment of the disclosure. Referring to fig. 2, the method steps include:
201. providing a substrate and manufacturing a semiconductor layer on the substrate.
In one example, step 201 includes:
and step 1, providing a substrate, and growing an AlN nucleation layer on the surface of the substrate.
Wherein the substrate is one of a Si substrate, a SiC substrate, a sapphire substrate and the like.
In one example, step 1 comprises:
in the first step, the substrate is subjected to an oxidation treatment.
The surface of the substrate is subjected to an oxidation treatment using hydrogen gas in the reaction chamber at a temperature of 100 to 1200 c for a period of time of 5 to 10 minutes, for example, 5 minutes.
And (3) performing a de-oxidation treatment on the substrate through hydrogen so as to facilitate the growth of a subsequent film layer.
And secondly, growing an AlN nucleation layer.
And pre-introducing an Al source into the reaction cavity, and pre-paving an Al atomic layer on the surface of the substrate.
Because the lateral mobility of Al atoms is relatively low, pre-paving the Al atomic layer is beneficial to improving the flatness of the subsequent AlN nucleation layer, and further improving the uniformity of the whole semiconductor layer. Is beneficial to improving the overall quality of the semiconductor layer.
Optionally, al source with flow rate of 50-200 sccm is pre-introduced into the reaction cavity for 10-100 s at the temperature of 1000-1100 ℃ so as to pre-spread an Al atomic layer on the substrate.
Under the above temperature conditions, al source with the flow of 50-200 sccm is introduced into the reaction cavity for a certain period of time, so that a layer of stable Al atomic layer with moderate thickness can be laminated on the substrate, and the stable and uniform growth of the subsequent AlN nucleation layer is ensured.
Alternatively, the pressure in the reaction chamber is between 40 and 70mbar when introducing an Al source into the reaction chamber. The low pressure may promote spreading of the Al atomic lateral extension layer on the substrate.
Illustratively, the Al atomic layer has a thickness of 1 to 5nm.
The thickness of the Al atomic layer is within the above range, and a good growth basis for the AlN nucleation layer can be provided.
In the second step, when the Al source is introduced into the reaction chamber, the carrier gas is not supplied with any other gas or the other type of organometallic source than the Al source.
The temperature in the cavity is regulated to 1100-1200 deg.c, alN nucleating layer with thickness of 150-300 nm is grown and the growth pressure is 40-70 mbar. An AlN nucleation layer with better quality can be obtained.
It is worth noting that in the embodiments of the present disclosure, the growth of the LED epitaxial structure is achieved using a VeecoK 465i or C4 or RB MOCVD (Metal Organic Chemical Vapor Deposition ) apparatus. Wherein, high-purity H is adopted 2 (Hydrogen) or high purity N 2 (Nitrogen) or high purity H 2 And high purity N 2 High purity NH using the mixed gas of (2) as carrier gas 3 As nitrogen source, trimethylgallium (TMGa) and triethylgallium (TEGa) as gallium source, trimethylindium (TMIn) as indium source, silane (SiH) 4 ) Trimethylaluminum (TMAL) as an aluminum source, magnesium dicyclopentadiene (CP 2 Mg) as P-type dopant.
And 2, manufacturing a GaN/AlGaN superlattice layer on the AlN nucleation layer.
In one example, step 2 includes:
and growing AlGaN/GaN superlattice layer in the temperature range of 900-1100 ℃ and the pressure range of 40-70 mbar.
For example, the growth of AlGaN/GaN superlattice layers is performed at a temperature of 1000℃and a pressure of 50 mbar.
The number of cycles of the AlGaN/GaN superlattice layer can be 5-10.
For example, the number of periods of the AlGaN/GaN superlattice layer may be 5.
Illustratively, the AlGaN/GaN superlattice layer has a thickness of 1-2 μm.
For example, the AlGaN/GaN superlattice layer has a thickness of 1.5 μm.
And step 3, manufacturing a GaN channel layer on the surface of the AlGaN/GaN superlattice layer.
In one example, step 3 includes:
and growing a GaN channel layer on the surface of the AlGaN/GaN superlattice layer in an environment with the growth temperature of 1050-1150 ℃ and the pressure of 150-250 mbar.
For example, a GaN channel layer is grown on the surface of an AlGaN/GaN superlattice layer in an environment at a growth temperature of 1100 ℃ and a pressure of 200 mbar.
The GaN channel layer is grown in the above-described environment, and a GaN channel layer with good quality can be obtained.
The GaN channel layer has a thickness of 100 to 400nm, for example.
The GaN channel layer within the above thickness range is advantageous in improving the quality of the finally obtained semiconductor layer.
And 4, manufacturing an AlGaN barrier layer on the GaN channel layer.
In one example, step 4 includes:
and growing an AlGaN barrier layer on the surface of the GaN channel layer in an environment with the growth temperature of 1050-1150 ℃ and the growth pressure of 40-70 mbar.
For example, the AlGaN barrier layer is grown on the surface of the GaN channel layer in an environment where the growth temperature is 1100 ℃ and the growth pressure is 55 mbar.
The AlGaN barrier layer grown in the above-described environment is of good quality.
Alternatively, an AlN insertion layer may also be grown on the GaN channel layer surface prior to the growth of the AlGaN barrier layer.
The AlN insert layer is grown on the surface of the GaN channel layer under the conditions of a growth temperature of 1050-1150 ℃ and a pressure of 40-70 mbar.
For example, the AlN insert layer is grown on the surface of the GaN channel layer in an atmosphere at a growth temperature of 1100℃and a pressure of 60 mbar.
The thickness of the intercalating layer is illustratively 1-5 nm. For example 1nm.
An AlN insert layer with good quality can be obtained in the growth environment.
Fig. 3 is a schematic structural diagram of a transistor in a manufacturing process according to an embodiment of the disclosure. Referring to fig. 3, the structure shown in fig. 3 is formed after performing step 201, the transistor comprising: an AlN nucleation layer 301, an AlGaN/GaN superlattice layer 302, a GaN channel layer 303, and an AlGaN barrier layer 304 are sequentially stacked on the surface of the substrate 300.
The AlGaN/GaN superlattice layer 302 has a superlattice structure, and includes a plurality of periodic AlGaN sublayers and GaN sublayers.
Illustratively, the AlGaN/GaN superlattice layer 302 includes 5-10 cycles of AlGaN sublayers and GaN sublayers that are stacked in sequence.
The buffer layer is formed by the AlN nucleation layer 301 and the AlGaN/GaN superlattice layer 302, and the buffer layer with the film layer structure can reduce the influence of stress caused by lattice mismatch and thermal mismatch on the film layer structure which grows subsequently.
Wherein a two-dimensional electron gas is provided between the GaN channel layer 303 and the AlGaN barrier layer 304.
Of course, the above semiconductor layer is merely an example, and the film structure may be added or reduced in the above semiconductor layer in the actual manufacturing process.
For example, an AlN insertion layer may be further provided between the GaN channel layer 303 and the AlGaN barrier layer 304.
The concentration of the two-dimensional electron gas of the device can be increased by fabricating an AlN insertion layer between the GaN channel layer 303 and the AlGaN barrier layer 304.
202. And manufacturing a gate dielectric layer on the surface of the semiconductor layer.
In one example, step 202 includes:
a gate dielectric layer is grown on the semiconductor layer surface by plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) or atomic layer deposition (Atomic Layer Deposition, ALD) techniques.
Wherein the gate dielectric layer is a SiN layer.
Wherein the thickness of the gate dielectric layer is 20 nm-30 nm.
The gate dielectric layer with the thickness range can improve the performance of the transistor.
Fig. 4 is a schematic structural diagram of a transistor in a manufacturing process according to an embodiment of the disclosure. Referring to fig. 4, the structure is formed after the gate dielectric layer 401 is fabricated on the basis of fig. 3.
Wherein the gate dielectric layer 401 is located on the surface of the AlGaN barrier layer 304.
203. And manufacturing a gate metal layer on the surface of the gate dielectric layer.
In one example, step 203 includes:
and evaporating a grid metal layer on the surface of the grid dielectric layer in an electron beam evaporation mode.
Wherein, the gate metal layer can be TiN or Al.
Fig. 5 is a schematic structural diagram of a transistor in a manufacturing process according to an embodiment of the disclosure. Referring to fig. 5, the structure shown in fig. 5 is formed after the gate metal layer 501 is formed on the basis of fig. 4.
The gate metal layer 501 is fabricated to facilitate subsequent gate formation.
204. And manufacturing a patterned first sacrificial oxide layer on the surface of the gate metal layer, wherein the patterned first sacrificial oxide layer covers the gate region of the gate metal layer.
In one example, step 204 includes:
first, a first sacrificial oxide layer is grown.
And growing a first sacrificial oxide layer on the surface of the gate metal layer by PECVD technology or ALD technology.
Fig. 6 is a schematic structural diagram of a transistor in a manufacturing process according to an embodiment of the disclosure. Referring to fig. 6, the structure of fig. 6 is formed by fabricating a first sacrificial oxide layer 601 on the basis of fig. 5.
The first sacrificial oxide layer 601 is fabricated to facilitate the subsequent formation of the gate.
And secondly, patterning the first sacrificial oxide layer.
The first sacrificial oxide layer is patterned using a dry etching technique.
In the embodiment of the disclosure, the thickness of the first sacrificial oxide layer is 1/3 to 1/2 of the thickness of the gate metal layer.
If the thickness of the first sacrificial oxide layer is smaller, the protection effect of the first sacrificial oxide layer on the gate metal layer of the gate region is not good enough, and the gate may be etched by the liquid medicine. If the first sacrificial oxide layer is too thick, the cost is high. The first sacrificial oxide layer with the thickness range has a good protection effect on the gate metal layer of the gate region, and the cost can be limited within a lower range.
Fig. 7 is a schematic structural diagram of a transistor in a manufacturing process according to an embodiment of the disclosure. Referring to fig. 7, the structure shown in fig. 7 is formed by patterning the first sacrificial oxide layer 601 in fig. 6.
The patterned first sacrificial oxide layer 601 only covers the gate region, so that when the gate metal layer 501 is subjected to subsequent wet etching, the liquid medicine does not etch the gate metal layer 501 in the gate region under the protection of the first sacrificial oxide layer 601.
205. And carrying out wet etching on the gate metal layer, removing the uncovered area of the sacrificial oxide layer in the gate metal layer, and reserving the gate area to form a gate.
In one example, step 205 includes:
when the grid metal layer is an Al layer, etching the grid metal layer by adopting a solution with the ratio of hydrochloric acid to water being 1:20 at the temperature of 100-150 ℃.
When the grid metal layer is a TiN layer, the grid metal layer is etched by adopting sulfuric acid and hydrogen peroxide or mixed solution of ammonia water and hydrogen peroxide at the temperature of 100-150 ℃.
Wherein the ratio of sulfuric acid to hydrogen peroxide or the ratio of ammonia water to hydrogen peroxide is 1:0.5-1:100.
It is worth to say that, when the mixed solution of sulfuric acid and hydrogen peroxide or ammonia water and hydrogen peroxide is formed, water can be additionally added besides sulfuric acid and hydrogen peroxide or ammonia water and hydrogen peroxide, and the proportion of water is determined based on the manufacturing requirement.
In an embodiment of the present disclosure, the wet etching duration is determined based on a thickness of the gate metal layer.
Different solutions are adopted for etching the gate metal layers formed by different materials, so that the selection ratio of wet etching, namely the etching rate of the gate metal layers is high, and the etching rate of the first sacrificial oxide layer is low, and the damage to the gate is avoided.
Of course, the above-mentioned wet etching temperature and the composition ratio of the wet chemical are only examples, and the temperature and the solution ratio may be adjusted according to the actual situation in the actual manufacturing process.
Fig. 8 is a schematic structural diagram of a transistor in a manufacturing process according to an embodiment of the disclosure. Referring to fig. 8, the structure shown in fig. 8 is formed after patterning the gate metal layer 501 on the basis of fig. 7.
Referring to fig. 8, after the wet etching, the gate metal layer 501 in the gate region remains to form a gate due to the protection of the first sacrificial oxide layer 601, and the gate metal layer 501 outside the gate region is etched away by the liquid medicine.
206. And manufacturing a gate metal protection layer, wherein the gate metal protection layer covers the gate electrode.
In one example, step 206 includes:
and manufacturing a gate metal protection layer on the surface of the gate dielectric layer by PECVD or ALD technology.
Wherein the gate metal protection layer may be SiN.
Fig. 9 is a schematic structural diagram of a transistor in a manufacturing process according to an embodiment of the disclosure. Referring to fig. 9, the structure shown in fig. 9 is formed after the gate metal cap layer 701 is fabricated on the basis of fig. 8.
Referring again to fig. 9, a gate metal protection layer 701 is located on the surface of the gate dielectric layer 401, and the gate metal protection layer 701 covers the gate (the gate metal layer 501 in the gate region) and the first sacrificial oxide layer 601.
The gate metal protection layer 701 is manufactured, in the first aspect, the gate metal protection layer 701 is used for protecting the gate, so that the gate is prevented from being damaged during etching of the gate dielectric layer, and in the second aspect, the gate metal protection layer 701 can also play a passivation effect, so that the gate is prevented from being oxidized in the subsequent use process.
207. And patterning the gate dielectric layer and the gate metal protection layer by wet etching to form a drain groove and a source groove which penetrate through the gate dielectric layer and the gate metal protection layer and are connected with the semiconductor layer.
In one example, step 207 includes:
a buffered oxide etchant (Buffered Oxide Etch, BOE) or high-level dilute hydrofluoric acid (Dilute Hydro Fluoric acid, DHF) is used to etch the gate dielectric layer and the gate metal cap layer to form drain and source recesses extending to the surface of the semiconductor layer.
It is worth noting that in high DHF corrosion, H 2 The ratio of O to HF was 20: 1-500:1, and the ratio in BOE corrosion is set according to the requirement.
Fig. 10 is a schematic structural diagram of a transistor in a manufacturing process according to an embodiment of the disclosure. Referring to fig. 10, fig. 10 shows a film structure after etching the gate dielectric layer 401 and the gate metal protection layer 701 in fig. 9.
After wet etching is performed on the gate dielectric layer 401 and the gate metal protection layer 701, a drain groove 801 and a source groove 802 extending to the surface of the AlGaN barrier layer 304 are formed.
208. And manufacturing a source drain metal layer, wherein the source drain metal layer covers the source groove, the drain groove and the surface of the gate metal protection layer.
Wherein the source drain metal layer is TiN or Al.
The manufacturing process of this step may refer to step 203, namely, the source/drain metal layer is manufactured by adopting the manufacturing method of the gate metal layer.
Fig. 11 is a schematic structural diagram of a transistor in a manufacturing process according to an embodiment of the disclosure. Referring to fig. 11, the structure shown in fig. 11 is obtained by fabricating a source/drain metal layer 901 on the basis of fig. 10.
The source-drain metal layer 901 covers the drain groove 801 and the source groove 802, and also covers the gate metal protection layer 701.
The source/drain metal layer 901 is fabricated to facilitate the subsequent formation of source and drain.
209. And manufacturing a patterned second sacrificial oxide layer on the surface of the source drain metal layer, wherein the patterned second sacrificial oxide layer covers the source region and the drain region of the source drain metal layer.
Wherein the second sacrificial oxide layer is SiO 2 。
In the embodiment of the disclosure, the thickness of the second sacrificial oxide layer 207 is 1/3 to 1/2 of the thickness of the source-drain metal layer 401 located outside the source recess and the drain recess.
If the thickness of the first sacrificial oxide layer 601 is smaller, the protection effect of the first sacrificial oxide layer 601 on the gate region is not good enough, and the gate 206 may be etched by the liquid medicine. If the first sacrificial oxide layer 601 is too thick, the cost is high. The first sacrificial oxide layer 601 with the thickness range has a better protection effect on the gate metal layer 501, and the cost can be limited in a lower range.
The process of this step may refer to step 204, in which the second sacrificial oxide layer is fabricated by using the fabrication method of the first sacrificial oxide layer, but the patterned shapes of the two sacrificial oxide layers are different.
Fig. 12 is a schematic structural diagram of a transistor in a manufacturing process according to an embodiment of the disclosure. Referring to fig. 12, the structure shown in fig. 12 is obtained after the second sacrificial oxide layer 902 is formed on the basis of fig. 11.
The patterned second sacrificial oxide 902 covers only the drain region and the source region. The drain region refers to a portion of the source-drain metal layer 901 where a drain is formed, and the source region refers to a portion of the source-drain metal layer 901 where a source is formed.
210. And carrying out wet etching on the source drain metal layer, removing the uncovered area of the second sacrificial oxide layer in the source drain metal layer, and reserving the source electrode area and the drain electrode area to form a source electrode and a drain electrode.
The manufacturing process of this step may refer to step 205, namely, etching the source/drain metal layer by using a method of etching the gate metal layer.
The source electrode and the drain electrode are formed by etching the source electrode and the drain electrode metal layer by using wet etching instead of dry etching, so that etching damage to the gate metal protection layer positioned below the source electrode and the drain electrode metal layer when the source electrode and the drain electrode metal layer are etched by using dry etching can be avoided, the situation that the interface state of the gate metal protection layer presents electropositivity or electronegativity is avoided, the concentration of two-dimensional electron gas is reduced after the interface state of the gate metal protection layer presents the electropositivity is avoided, and the current collapse effect of a device caused by the reduction of the concentration of the two-dimensional electron gas can be avoided, thereby improving the performance of the device.
After the drain and the source are manufactured, a transistor can be formed, and the manufactured transistor structure is shown in fig. 13.
Fig. 13 is a schematic structural diagram of a transistor according to an embodiment of the disclosure. Referring to fig. 13, the transistor includes: the semiconductor device comprises a substrate 300, a buffer layer 11, a channel layer 12, a barrier layer 13, a gate dielectric layer 401, a gate 14, a first sacrificial oxide layer 601, a gate metal protection layer 701, a drain 15, a source 16, a second sacrificial oxide layer 902, a drain groove 801 and a source groove 802.
In the embodiment of the present disclosure, the semiconductor layer includes a buffer layer 11, a channel layer 12, and a barrier layer 13.
Wherein the buffer layer 11 comprises an AlN nucleation layer 301 and an AlGaN/GaN superlattice layer 302 which are sequentially laminated; the channel layer 12 includes a GaN channel layer 303; the barrier layer 13 includes an AlGaN barrier layer 304.
Of course, the above semiconductor layer is merely an example, and the film structure may be added or reduced in the above semiconductor layer in the actual manufacturing process.
In the embodiment of the present disclosure, the gate metal layer 501 remained after etching forms the gate 14, and the source drain metal layer 901 remained in the drain recess 801 and the source recess 802 after etching forms the drain 15 and the source 16, respectively.
In the embodiment of the present disclosure, the buffer layer 11, the channel layer 12, the barrier layer 13, and the gate dielectric layer 401 are sequentially stacked on the surface of the substrate 300. The gate electrode 14 is provided on the surface of the gate dielectric layer 401, and the first sacrificial oxide layer 601 is provided on the surface of the gate electrode 14. The gate metal protection layer 701 is located on the surface of the gate dielectric layer 401, and the gate metal protection layer 701 covers the gate 14 and the first sacrificial oxide layer 601. The gate dielectric layer 401 and the gate metal protective layer 701 have a drain groove 801 and a source groove 802, and the drain groove 801 and the source groove 802 penetrate through the gate dielectric layer 401 and the gate metal protective layer 701 and then are connected with the barrier layer 13. The drain electrode 15 and the source electrode 16 are respectively located in the drain recess 801 and the source recess 802, and the drain electrode 15 and the source electrode 16 further include portions located outside the drain recess 801 and the source recess 802. A second sacrificial oxide layer 902 is also provided on the drain 15 and source 16 surfaces.
Of course, the schematic structural diagram of the transistor is an example provided in the disclosure, and is not intended to limit the disclosure, and the transistor may have a film layer structure added or reduced in the above structure in actual manufacturing process.
The foregoing description of the preferred embodiments of the present disclosure is provided for the purpose of illustration only, and is not intended to limit the disclosure to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, alternatives, and alternatives falling within the spirit and principles of the disclosure.

Claims (10)

1. A method of fabricating a transistor, the method comprising:
manufacturing a grid dielectric layer on the surface of the semiconductor layer;
manufacturing a gate metal layer on the surface of the gate dielectric layer;
manufacturing a patterned first sacrificial oxide layer on the surface of the gate metal layer, wherein the patterned first sacrificial oxide layer covers a gate region of the gate metal layer;
wet etching is carried out on the gate metal layer, the area, which is not covered by the sacrificial oxide layer, in the gate metal layer is removed, and the gate area is reserved to form a gate;
manufacturing a gate metal protection layer covering the gate;
patterning the gate metal protection layer and the gate dielectric layer to form a source groove and a drain groove which penetrate through the gate metal protection layer and the gate dielectric layer and are connected with the semiconductor layer;
and manufacturing a source electrode and a drain electrode in the source electrode groove and the drain electrode groove respectively.
2. The method of claim 1, wherein the fabricating a source and a drain in the source recess and the drain recess, respectively, comprises:
manufacturing a source drain metal layer, wherein the source drain metal layer covers the source groove, the drain groove and the surface of the gate metal protection layer;
manufacturing a patterned second sacrificial oxide layer on the surface of the source drain metal layer, wherein the patterned second sacrificial oxide layer covers a source region and a drain region of the source drain metal layer;
and carrying out wet etching on the source drain metal layer, removing the uncovered area of the second sacrificial oxide layer in the source drain metal layer, and reserving the source electrode area and the drain electrode area to form the source electrode and the drain electrode.
3. The method of claim 1, wherein patterning the gate metal cap layer to form source and drain recesses through the gate metal cap layer and the gate dielectric layer and contiguous with the semiconductor layer comprises:
and etching the gate metal protection layer and the gate dielectric layer by high-order dilute hydrofluoric acid DHF or a buffer oxide etchant BOE to form the source electrode groove and the drain electrode groove.
4. A method according to any one of claims 1 to 3, wherein said wet etching of said gate metal layer comprises:
and when the gate metal layer is a TiN layer, etching the gate metal layer by using a mixture of sulfuric acid and hydrogen peroxide or a mixture of ammonia water and hydrogen peroxide.
5. A method according to any one of claims 1 to 3, wherein said wet etching of said gate metal layer comprises:
and when the gate metal layer is an Al layer, etching the gate metal layer by using hydrochloric acid.
6. The method of claim 2, wherein the first sacrificial oxide layer and the second sacrificial oxide layer are each of SiO 2 One or more of SiN.
7. The method of claim 2, wherein the thickness of the first sacrificial oxide layer and the second sacrificial oxide layer is 1/3 to 1/2 of the thickness of the gate metal layer and the source drain metal layer located outside the source recess and the drain recess.
8. A method according to any of claims 1 to 3, wherein the gate dielectric layer has a thickness of 20 to 30nm.
9. A method according to any one of claims 1 to 3, wherein the semiconductor layer comprises a buffer layer, a channel layer and a barrier layer laminated in this order on the surface of the substrate.
10. A transistor formed by the method of any one of claims 1 to 9.
CN202311153066.XA 2023-09-07 2023-09-07 Transistor and preparation method thereof Pending CN117293020A (en)

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